WO2009033967A1 - Systeme et procede de controle de performances de disque dur par l'intermediaire d'un trajet de commande - Google Patents

Systeme et procede de controle de performances de disque dur par l'intermediaire d'un trajet de commande Download PDF

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Publication number
WO2009033967A1
WO2009033967A1 PCT/EP2008/061457 EP2008061457W WO2009033967A1 WO 2009033967 A1 WO2009033967 A1 WO 2009033967A1 EP 2008061457 W EP2008061457 W EP 2008061457W WO 2009033967 A1 WO2009033967 A1 WO 2009033967A1
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WO
WIPO (PCT)
Prior art keywords
mass storage
data
storage modules
individual
performance
Prior art date
Application number
PCT/EP2008/061457
Other languages
English (en)
Inventor
Wolfgang Klausberger
Stefan Abeling
Axel Kochale
Johann Maas
Original Assignee
Thomson Licensing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO2009033967A1 publication Critical patent/WO2009033967A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Definitions

  • the present invention relates to the field of mass storage solutions with multiple storage units such as hard disk drives or HDDs.
  • exemplary embodiments of the present invention relate to monitoring hard disk performance via a control path.
  • U.S. Patent Application Publication No. 20020013871 to Kakiage purports to disclose an improvement to a data processing unit. Improvement of the writing speed and efficiency of demodulated data from demodulating means into the buffer memory is discussed. As solving means thereof, writing of data demodulated in the demodulating means into the buffer memory is continuously performed after waiting for arrival of data of the same kind. Therefore, upon transfer of the demodulated data from the demodulating circuit to a temporary storage sub-means within the bus controller which controls access to the buffer memory, the kind of data of the next demodulated data is also transmitted.
  • U.S. Patent No. 5,987,562 to Glover purports to disclose a read channel having a waveform sampler for use in a disk drive mass storage system.
  • the disk drive mass storage system includes a disk/head assembly, a preamplifier, and a control circuitry.
  • the read channel is coupled to the control circuitry through a data/parameter path.
  • the read channel includes a plurality of circuit modules for processing a waveform data signal received from the preamplifier and to generate a digital data signal in response.
  • the read channel provides the digital data signal to the control circuitry through the data/parameter path.
  • the read channel also includes the waveform sampler for receiving and sampling a processed waveform signal from one of the plurality of circuit modules and for generating a digital waveform sampler signal in response.
  • the read channel can provide either the digital data signal or the digital waveform sampling signal as an output onto the data/parameter path.
  • U.S. Patent No. 5,608,891 to Mizuno, et al. purports to disclose a read unit which governs reading of data and a write unit which governs writing of data.
  • the read unit and the write unit are located separately in a RAID unit which controls array type magnetic disk units.
  • a control circuit uses the read unit to read data through an HDD control unit.
  • the control circuit uses the write unit to write data into the magnetic disk units. Since the read unit and write unit are provided separately, processing performance improves.
  • U.S. Patent No. 5,765,186 to Searby purports to disclose a data storage apparatus that comprises several disc stores connected to respective RAM buffers by respective data interfaces and highways. Sets of data are stored in the disc stores with the data in each set being distributed among the disc stores.
  • the apparatus comprises a controller which, in response to an external request for data, generates control data identifying one or more sets of data to be transferred between the disc stores and the RAM buffers.
  • the control data is transferred to the disc stores via the respective data interfaces and highways.
  • a signal is sent from the interfaces and once the controller has received signals from each of the interfaces it enables data to be transferred between the interfaces and respective RAM buffers.
  • a data highway is provided for connection to external apparatus for a substantially continuous sequential transfer of the data in the identified set or all of the identified sets. Data is transferred between the RAM buffers and the data highway under the control of the controller.
  • the highway may be provided with error checking circuitry.
  • Japanese Patent No. 5127671 A2 to Yoshio purports to disclose a system that enables high-order commands to easily perform other processes in parallel to music performance without directly monitoring the music performance by monitoring the music performance by the CD-ROM device and generating an interruption signal which indicates the end of the music performance when the music performance ends.
  • U.S. Patent No. 4759014 to Decker, et al. purports to disclose a system in which digital data is received on a plurality of input channels at unrelated, asynchronous input clock rates.
  • the data is multiplexed and transmitted via one or more synchronous parallel channels, together with encoded information related to the original asynchronous input clock rate on each channel.
  • the data received from the synchronous channels is demultiplexed and redistributed to proper output channels and clocked out therefrom at rates derived from the encoded and reconstituted asynchronous clock rate information from each channel.
  • a computer system includes a data switch coupled between a host computer and one or more storage devices.
  • a storage controller for managing the storage of data within the one or more storage devices is coupled to the switch.
  • the switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller.
  • information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.
  • the computer system achieves separation of control and data paths using a modified switch and standard host adapter hardware and host driver software.
  • a two party protocol such as the Fibre Channel protocol is not violated.
  • Japanese Patent No. 8095870 A2 to Shuji, et al. purports to disclose a system that facilitates control by eliminating the need for a high-speed data bus control circuit which is enough to follow up the speed of DMA transfer, and that improves the reliability by generating control information for data transfer to a memory, and that transfers data and decides the state of the memory.
  • U.S. Patent No. 4,354,225 to Frieder, et al. purports to disclose a data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller.
  • At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations.
  • At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different.
  • a supervisory processor for initiating configuring and monitoring the system is connected to the main store bus.
  • a communication bus is connected to the processors of the first and second types and to the supervisory processor.
  • a diagnostic bus connects the supervisory processor to each of the processors of the first and second types.
  • An input- output bus ensemble is connected to the supervisory processor and to each auxiliary processor.
  • At least one device and associated device controller can be connected to the input-output bus ensemble.
  • At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.
  • a system and method that facilitates improved monitoring of individual hard disk drive performance is desired.
  • a method in accordance with the present invention is set forth in claim 1.
  • the method relates to generating performance parameters about an individual one of a plurality of mass storage modules of a digital recording apparatus.
  • the method comprises operating the individual one of the plurality of mass storage modules of the digital recording apparatus, the individual one of the plurality of mass storage modules having an access engine connected to the individual one of the plurality of mass storage modules for monitoring data transfers.
  • the method also comprises generating at least one performance parameter about the individual one of the plurality of mass storage modules by observing the data transfers with the access engine.
  • a digital recording apparatus in accordance with the present invention is set forth in claim 6.
  • the digital recording apparatus comprises at least one mass storage module that is adapted to perform data transfers.
  • the digital recording apparatus also comprises an access engine connected to the at least one mass storage module for monitoring data transfers, the access engine being adapted to generate performance parameters about the at least one mass storage module by observing the data transfers.
  • At least one performance parameter may be transferred via a control path to conserve resources of a data path.
  • the performance parameter may comprise a transfer time of a data transfer.
  • a digital recording apparatus may comprise a power supply to power the plurality of mass storage modules.
  • a DMA unit also referred to as an access engine may be adapted to make at least one voltage measurement of the power supply.
  • the DMA unit or access engine may additionally be adapted to make at least one electrical current measurement of the power supply.
  • a digital recording apparatus may comprise a plurality of storage modules, in which an individual one of the storage modules that is involved in a DMA transfer may be referred to as an involved module.
  • An access engine may be connected to the plurality of mass storage modules via a first control path and a first data path.
  • the digital recording apparatus may also include a second control path.
  • the access engine may be adapted to derive, from observations of individual ones of the data transfers and of the respectively involved mass storage modules, performance related parameters related to the individual data transfer.
  • the access engine may be further adapted to derive, from the performance related parameters, the performance parameters as mass storage module related performance parameters.
  • the access engine may be additionally adapted to provide the performance parameters via the second control interface.
  • Fig. 1 is a block diagram of a data storage system in accordance with an exemplary embodiment of the present invention.
  • Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
  • Fig. 3 is a process flow diagram that shows a method in accordance with an exemplary embodiment of the present invention.
  • the data storage system shown in Fig. 1 is generally referred to by the reference number 100.
  • the data storage system 100 comprises a plurality of BusDriver modules, including a first BusDriver module 102, a second BusDriver module 104, a third BusDriver module 106 and a fourth BusDriver module 108.
  • Each of the four BusDriver modules 102, 104, 106, 108 performs the function of managing the operation of a plurality of storage devices such as ATA/ATAPI controlled storage devices, which are shown as Device#0,...,Device#15 in Fig. 1.
  • the first BusDriver module 102 manages the operation of a first group of controlled storage devices 110.
  • the second BusDriver module 104 manages the operation of a second group of controlled storage devices 112.
  • the third BusDhver module 106 manages the operation of a third group of controlled storage devices 114.
  • the fourth BusDhver 108 manages the operation of a fourth group of controlled storage devices 116.
  • the first group of controlled storage devices 110, the second group of controlled storage devices 112, the third group of controlled storage devices 114, and the fourth group of controlled storage devices 116 may comprise a RAID storage array.
  • BusDriver modules 102, 104, 106, 108 comprises a general
  • each Parallel Input Output unit is identified with a label in the form of PIO#n.
  • Each DMA unit is identified with a label in the form of DMA#n.
  • the DMA units shown in Fig. 1 may also be referred to herein as access engines.
  • the BusDriver controller associated with a first one of the first group of controlled storage devices 110 is identified by the reference number 118 in Fig. 1.
  • the PIO unit associated with the first one of the first group of controlled storage devices 110 is identified by the reference number 120 in Fig. 1.
  • the DMA unit associated with the first one of the first group of controlled storage devices 110 is identified by the reference number 122 in Fig. 1.
  • the remaining BusDriver controllers, PIO units and DMA units are not assigned separate reference numbers in Fig. 1 for clarity.
  • an exemplary one of the BusDriver modules 102, 104, 106, 108 is controlled by a system controller FPGA with an embedded software processor system not shown in Fig. 1.
  • each of the four groups of controlled storage devices 110, 112, 114, 116 comprises four controlled storage devices. Accordingly, the exemplary data storage system 100 controls a total of 16 devices.
  • the skilled person will appreciate that other exemplary embodiments of the present invention may comprise configurations involving greater or smaller numbers of storage devices depending on design considerations for each individual system.
  • Each of the exemplary BusDriver modules 102, 104, 106 and 108 comprises a separate control path and data path. Each control path initiates upcoming transactions like commands or the like.
  • the control paths may be implemented, for example, as a serial communication interface, such as an I2C bus.
  • Each data path may comprise a real-time data path having a data bus and strobe signals for data transfer. In Fig.
  • the first BusDriver module 102 comprises a control path 124 and a data path 132.
  • the second BusDriver module 104 comprises a control path 126 and a data path 134.
  • the third BusDriver module 106 comprises a control path 128 and a data path 136.
  • the fourth BusDriver module 108 comprises a control path 130 and a data path 138.
  • a system controller of the data storage system 100 initiates transfers of data in so-called clusters by sending register values for the cluster size, the cluster start address and the related command, namely "read” or "write", via one of the control paths 124, 126, 128, 130 to a respective one of the BusDriver controllers. Registers that hold the status of finished transfers are accessible to be read out by the system controller. This process will also be used to read the information about the data transfer performance of each single disk.
  • each of the respective BusDriver controllers 102, 104, 106, 108 supports its four associated DMA units in order to handle DMA transfers between the system controller and the attached groups of controlled storage devices 110, 112, 114, 116.
  • transfers are done according to the UDMA concept of the ATA interface. Performance information is assembled by monitoring data transfer times of each disk in the RAID storage system.
  • the digital recording apparatus 100 comprises a power supply to power the plurality of mass storage modules 110, 112, 114, 116.
  • the DMA unit 122 or access engine may be adapted to make at least one voltage measurement of the power supply.
  • the DMA unit 122 or access engine may additionally be adapted to make at least one electrical current measurement of the power supply.
  • Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
  • the state diagram is generally referred to by the reference number 200.
  • the state diagram 200 shows, in state-diagram style, exemplary steps for performing read or write transfer actions to or from one single hard disk drive.
  • a DMA control state machine operating in accordance with the state diagram 200 is in an idle state 202 until a DMA transfer call is received at a DMA transfer state 204.
  • the receipt of the DMA transfer call resets a TimeCount variable that is used during a counting state 230.
  • the reset is indicated in Fig. 2 by an arrow from the DMA transfer call state 204 to the counting state 230.
  • DMA transfer may be either a read call or a write call. Additionally, the transfer may be performed according to the UDMA concept of the ATA interface.
  • the access engine controlling the transfer After receiving the DMA transfer request, the access engine controlling the transfer checks for an error condition by reading an error bit from a status register, as shown at state 206. If no error condition is detected, as shown at state 208, the status registers of the device are read, as shown at state 214. If the error check performed at state 206 indicates that the device has an error condition, as shown at state 210, an error register of the device is read, as shown at state 212. Next, the status registers of the device are read, as shown at state 214.
  • the device status registers After the device status registers are read at state 214, they are evaluated. If either a busy status register or a DMA request status register has a logical value of "1 ", as shown at state 216, the status registers are reread at state 214. In the exemplary state 216 shown in Fig. 2, the busy status register is labelled BSY and the DMA request status register is labelled DRQ.
  • the storage device is considered to be ready to transfer data. Thereafter, various ATA/ATAPI registers may be loaded with information that is needed to perform the transfer.
  • the loading of the control registers is shown as a load ATA task file register state 220. Examples of control information that may be loaded include a logical block address or LBA, a sector count, an LBA Mid value, and/or an LBA High value.
  • the device starts the DMA transfer by asserting a DMARQ signal and signalling the end of the DMA transaction by generating an interrupt. Moreover, the access engine remains in a waiting for DMARQ state 222 until the assertion of the DMARQ signal.
  • DMARQ and INTRQ are used to start and stop the measurement of the transfer time of a data cluster.
  • the transfer time value is stored in a register and is available there to be used for performance evaluation.
  • the DMA control state machine enters a counting state 230.
  • a counter is reset and started.
  • the DMA transfer then takes place, as shown at state 226.
  • INTRQ has a logical value of "1 ", as shown at state 228.
  • the value TimeCount is stored in a TimeCount register, as shown at state 232.
  • the TimeCount register may then be read, as shown at state 234, and used to evaluate the performance of the individual hard disk that performed the DMA transfer.
  • the counting state 230 is suspended and the TimeCount variable is not incremented when a pause during a DMA transfer is caused by the system controller.
  • First-in first-out buffer flags or FiFo flags may be used to control those operations, as shown by the FiFo flag input to the counting state 230 in Fig. 2.
  • the counting state 230 is paused and the TimeCount variable is not incremented when an almost_full indication has a logical value of "1 " during a read operation or when an almost_empty indication has a logical value of "1 " during a write operation.
  • the DMA control state machine enters a wait state 236.
  • the wait state lasts for about 400 ns.
  • the status register of the device is read, as shown at state 238. If no error condition exists, as shown at state 240, the state machine returns to the idle state 202 via a done state 246. If, at state 238, an error condition has occurred, as shown at state 242, the error register of the device is read at state 244. Thereafter, the DMA control state machine returns to the idle state 202 via the done state 246.
  • the TimeCount register may be mapped or associated with the particular device to which it refers or on which it was measured. This may be done, for example, by using a disk-id to identify the device.
  • the disk-id may be stored in association with the value of the TimeCount register to be read by the system controller's embedded software processing system via the associated control path.
  • the software processor may be adapted to evaluate the transfer times for each hard disk drive in an array and to indicate weak devices or disks. In one exemplary embodiment, weak disks may be marked on a display or otherwise identified through an alert to a user via a user interface or the like.
  • the resolution of the TimeCount value is reduced, so that a smaller number of bytes is transferred.
  • the TimeCount register or hardware accumulates and holds a maximum value of TimeCount during a number of consecutive transfers. In this manner, communication with the system controller's embedded software processing system may be reduced.
  • Fig. 3 is a process flow diagram that shows a method for generating performance parameters about an individual one of a plurality of mass storage modules 110, 112, 114, 116 of a digital recording apparatus 100 in accordance with an exemplary embodiment of the present invention.
  • the method is generally referred to by the reference number 300.
  • the method 300 involves monitoring the operation of an individual hard disk drive in an array of hard disk drives with an access engine such as the DMA unit 122 shown in Fig. 1.
  • An exemplary method in accordance with the present invention may, in addition, be implemented according to the state diagram 200 shown in Fig. 2.
  • the method begins.
  • the data storage system 100 operates the individual one of the plurality of mass storage modules 110, 112, 114, 116.
  • the individual one of the plurality of mass storage modules 110, 112, 114, 116 has an access engine such as the DMA unit 122 connected to provide the ability to monitor data transfers.
  • performance parameters about the individual one of the plurality of mass storage modules 110, 112, 114, 116 are generated by observing the data transfers with the access engine.
  • the process ends.
  • an exemplary embodiment of the present invention may be useful in a digital recording apparatus having an access engine and a mass storage module connected for data transfers.
  • a digital recording apparatus having an access engine and a mass storage module connected for data transfers.
  • Such a system may employ a connection for nothing but data transfer operations, and performance parameters of individual mass storage modules may be generated by an observation of the data transfers.

Abstract

L'invention concerne un appareil d'enregistrement numérique (100) et un procédé (300) d'exploitation associé. Ce procédé (300) consiste à générer des paramètres de performances pour un module individuel de stockage de masse parmi une pluralité de modules (110, 112, 114, 116) de l'appareil d'enregistrement numérique (100). Le procédé consiste également à exploiter (304) le module individuel de stockage de masse (110, 112, 114 ou 116) de l'appareil d'enregistrement numérique (100), ledit module individuel (110, 112, 114 ou 116) comprenant un moteur d'accès (122) connecté au module individuel (110, 112, 114 ou 116) pour contrôler des transferts de données. Le procédé selon l'invention consiste encore à générer au moins un paramètre de performances relatif au module individuel de stockage de masse (110, 112, 114 ou 116) par observation des transferts de données au moyen du moteur d'accès (122).
PCT/EP2008/061457 2007-09-13 2008-09-01 Systeme et procede de controle de performances de disque dur par l'intermediaire d'un trajet de commande WO2009033967A1 (fr)

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EP07116319 2007-09-13
EP07116319.0 2007-09-13

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520766A2 (fr) * 1991-06-24 1992-12-30 Compaq Computer Corporation Surveillance de bus pour l'administrateur d'un système à ordinateur
US6189071B1 (en) * 1997-10-06 2001-02-13 Emc Corporation Method for maximizing sequential output in a disk array storage device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520766A2 (fr) * 1991-06-24 1992-12-30 Compaq Computer Corporation Surveillance de bus pour l'administrateur d'un système à ordinateur
US6189071B1 (en) * 1997-10-06 2001-02-13 Emc Corporation Method for maximizing sequential output in a disk array storage device

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