WO2009026998A3 - Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors - Google Patents

Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors Download PDF

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Publication number
WO2009026998A3
WO2009026998A3 PCT/EP2008/006011 EP2008006011W WO2009026998A3 WO 2009026998 A3 WO2009026998 A3 WO 2009026998A3 EP 2008006011 W EP2008006011 W EP 2008006011W WO 2009026998 A3 WO2009026998 A3 WO 2009026998A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
connection
pads
strip conductors
substrate
Prior art date
Application number
PCT/EP2008/006011
Other languages
German (de)
French (fr)
Other versions
WO2009026998A2 (en
Inventor
Roger Wyss
Original Assignee
Att Technology Gmbh
Roger Wyss
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Att Technology Gmbh, Roger Wyss filed Critical Att Technology Gmbh
Publication of WO2009026998A2 publication Critical patent/WO2009026998A2/en
Publication of WO2009026998A3 publication Critical patent/WO2009026998A3/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
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    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A connection of an RF chip (1) comprising pads (2; 2') is established by connecting said pads (2; 2') to substrate and strip conductors in an opening (10a; 10f) of a laminate. The connection to the strip conductors (3, 31) integrated into the substrate (4) is established via the chip pads (2). Once the connection has been established, the opening (10, 10', 10f) comprising the chip and the pads is filled with a sealing material that increases the compressive strength of the entire chip module. Preferably, the strip conductor structures are formed once the connection process of the chip (1) has been completed, thus significantly improving the cost efficiency and quality of the chip, simplifying the production processes, and optimizing a permanent safe connection between the chip and the strip conductors. Said connections can also be perfectly used in tough environments, e.g. in laundries.
PCT/EP2008/006011 2007-08-27 2008-07-23 Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors WO2009026998A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH13382007 2007-08-27
CH01338/07 2007-08-27

Publications (2)

Publication Number Publication Date
WO2009026998A2 WO2009026998A2 (en) 2009-03-05
WO2009026998A3 true WO2009026998A3 (en) 2009-04-23

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PCT/EP2008/006011 WO2009026998A2 (en) 2007-08-27 2008-07-23 Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009037627A1 (en) * 2009-08-14 2011-02-17 Giesecke & Devrient Gmbh Portable disk
DE102010041917B4 (en) * 2010-10-04 2014-01-23 Smartrac Ip B.V. Circuit arrangement and method for its production

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048179A (en) * 1986-05-23 1991-09-17 Ricoh Company, Ltd. IC chip mounting method
EP1048483A1 (en) * 1997-12-22 2000-11-02 Hitachi, Ltd. Semiconductor device
WO2002069385A2 (en) * 2001-02-27 2002-09-06 Infineon Technologies Ag Arrangement with a chip comprising an integrated circuit and a support or a support element
EP1394734A1 (en) * 2001-06-07 2004-03-03 Sony Corporation Ic card
WO2005062246A1 (en) * 2003-12-19 2005-07-07 Axalto Sa Identification document

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048179A (en) * 1986-05-23 1991-09-17 Ricoh Company, Ltd. IC chip mounting method
EP1048483A1 (en) * 1997-12-22 2000-11-02 Hitachi, Ltd. Semiconductor device
WO2002069385A2 (en) * 2001-02-27 2002-09-06 Infineon Technologies Ag Arrangement with a chip comprising an integrated circuit and a support or a support element
EP1394734A1 (en) * 2001-06-07 2004-03-03 Sony Corporation Ic card
WO2005062246A1 (en) * 2003-12-19 2005-07-07 Axalto Sa Identification document

Also Published As

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