WO2009022418A1 - 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法 - Google Patents

動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法 Download PDF

Info

Publication number
WO2009022418A1
WO2009022418A1 PCT/JP2007/065913 JP2007065913W WO2009022418A1 WO 2009022418 A1 WO2009022418 A1 WO 2009022418A1 JP 2007065913 W JP2007065913 W JP 2007065913W WO 2009022418 A1 WO2009022418 A1 WO 2009022418A1
Authority
WO
WIPO (PCT)
Prior art keywords
dynamic
program
reconstruction
execution
reconstructor
Prior art date
Application number
PCT/JP2007/065913
Other languages
English (en)
French (fr)
Inventor
Tatsuya Yamamoto
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/065913 priority Critical patent/WO2009022418A1/ja
Priority to JP2009528006A priority patent/JP5035344B2/ja
Publication of WO2009022418A1 publication Critical patent/WO2009022418A1/ja
Priority to US12/656,531 priority patent/US8250501B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
  • Power Sources (AREA)

Abstract

　再構成対象となる一連の処理の実行中に、該一連の処理うちソフトウェアによって実行中の一部の処理の機能を実現する論理回路をハードウェア上に構築し、一部の処理の実行を、ソフトウェアによる実行からハードウェア上に構築された論理回路による実行に切り替える。これを、ソフトウェアによって実行中の処理がなくなるまで段階的におこなうことにより、ハードウェアの再構成にかかるオーバーヘッドを削減しつつ、出力のレスポンスの向上および低消費電力を実現する。
PCT/JP2007/065913 2007-08-15 2007-08-15 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法 WO2009022418A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/065913 WO2009022418A1 (ja) 2007-08-15 2007-08-15 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法
JP2009528006A JP5035344B2 (ja) 2007-08-15 2007-08-15 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法
US12/656,531 US8250501B2 (en) 2007-08-15 2010-02-02 Dynamic reconfiguration computer product, apparatus, and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/065913 WO2009022418A1 (ja) 2007-08-15 2007-08-15 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/656,531 Continuation US8250501B2 (en) 2007-08-15 2010-02-02 Dynamic reconfiguration computer product, apparatus, and method

Publications (1)

Publication Number Publication Date
WO2009022418A1 true WO2009022418A1 (ja) 2009-02-19

Family

ID=40350482

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/065913 WO2009022418A1 (ja) 2007-08-15 2007-08-15 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法

Country Status (3)

Country Link
US (1) US8250501B2 (ja)
JP (1) JP5035344B2 (ja)
WO (1) WO2009022418A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9779244B1 (en) * 2012-08-14 2017-10-03 Rockwell Collins, Inc. Establishing secure initial state in a processing platform containing both high assurance security and safety-critical functions
US8972713B2 (en) * 2012-12-21 2015-03-03 Intel Corporation Cloud transformable device
JP2016111633A (ja) * 2014-12-09 2016-06-20 キヤノン株式会社 回路情報に従って論理回路を構成可能な回路を持つデバイスと、複数の制御手段とを有する情報処理システム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11232081A (ja) * 1998-02-12 1999-08-27 Fuji Xerox Co Ltd 情報処理システムおよび情報処理方法
WO2001095099A1 (fr) * 2000-06-06 2001-12-13 Tadahiro Ohmi Systeme et procede de gestion de circuits de traitement d'informations a fonction variable
JP2004362446A (ja) * 2003-06-06 2004-12-24 Mitsubishi Electric Corp 計算機及び計算方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751967A (en) * 1994-07-25 1998-05-12 Bay Networks Group, Inc. Method and apparatus for automatically configuring a network device to support a virtual network
JPH10320376A (ja) 1997-05-14 1998-12-04 Ricoh Co Ltd デジタル信号処理開発システム
JP3900499B2 (ja) 2004-10-27 2007-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 再構成可能な、命令レベルのハードウェアによる高速化のためにマイクロプロセッサとともにｆｐｇａテクノロジを使用する方法および装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11232081A (ja) * 1998-02-12 1999-08-27 Fuji Xerox Co Ltd 情報処理システムおよび情報処理方法
WO2001095099A1 (fr) * 2000-06-06 2001-12-13 Tadahiro Ohmi Systeme et procede de gestion de circuits de traitement d'informations a fonction variable
JP2004362446A (ja) * 2003-06-06 2004-12-24 Mitsubishi Electric Corp 計算機及び計算方法

Also Published As

Publication number Publication date
JPWO2009022418A1 (ja) 2010-11-11
US20100146257A1 (en) 2010-06-10
JP5035344B2 (ja) 2012-09-26
US8250501B2 (en) 2012-08-21

Similar Documents

Publication Publication Date Title
WO2009120981A3 (en) Vector instructions to enable efficient synchronization and parallel reduction operations
WO2011011295A3 (en) Reducing a rate of data transfer to at least a portion of memory
WO2012071192A3 (en) Sidewall image transfer pitch doubling and inline critical dimension slimming
WO2006099046A3 (en) Automated interface-specification generation for enterprise architectures
WO2012158728A3 (en) Adjusting the clock frequency of a processing unit in real-time based on a frequency sensitivity value
SG151257A1 (en) Method of breeding lipid-producing strain and utilization of the same
WO2005101190A3 (en) Processor having parallel vector multiply and reduce operations with sequential semantics
WO2006096884A3 (en) Process for obtaining pectin
WO2010039532A3 (en) Disabling cache portions during low voltage operations
WO2010082989A3 (en) Analyzing voyage efficiencies
WO2006086792A3 (en) Fermentation product production processes
WO2008118805A3 (en) Processor with adaptive multi-shader
TWI370962B (en) Method, system and computer program product to change the operating frequency of system core logic to maximize system memory bandwidth
WO2011146823A3 (en) Method and apparatus for using cache memory in a system that supports a low power state
GB0919120D0 (en) Apparatus and method for performing multiply accumulate operations
WO2012009252A3 (en) Dynamic enabling and disabling of simd units in a graphics processor
WO2006091846A3 (en) Reducing power by shutting down portions of a stacked register file
WO2008114139A3 (en) System and methods for biomass processing
WO2008002822A3 (en) Mulptiplying two numbers
TWI317969B (en) Rinse processing method, developing processing apparatus, and computer readable medium encoded with a control program to be executed by a computer
WO2008039321A3 (en) Iterative process with rotated architecture for reduced pipeline dependency
WO2009022418A1 (ja) 動的再構成プログラム、該プログラムを記録した記録媒体、動的再構成装置および動的再構成方法
WO2008084210A3 (en) Method and kit for producing plant growth medium by composting
TW200636485A (en) Method, apparatus and system to generate an interrupt by monitoring an external interface
WO2008027567A3 (en) Integral parallel machine

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07792547

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009528006

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07792547

Country of ref document: EP

Kind code of ref document: A1