WO2009021176A2 - Urgence et manipulation de fenêtre temporelle pour traiter des opérations de mémoire imprévisibles - Google Patents

Urgence et manipulation de fenêtre temporelle pour traiter des opérations de mémoire imprévisibles Download PDF

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Publication number
WO2009021176A2
WO2009021176A2 PCT/US2008/072609 US2008072609W WO2009021176A2 WO 2009021176 A2 WO2009021176 A2 WO 2009021176A2 US 2008072609 W US2008072609 W US 2008072609W WO 2009021176 A2 WO2009021176 A2 WO 2009021176A2
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WIPO (PCT)
Prior art keywords
storage device
data
data integrity
operations
errors
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Application number
PCT/US2008/072609
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English (en)
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WO2009021176A3 (fr
WO2009021176A9 (fr
Inventor
James J. Tringali
Sergey A. Gorobets
Shai Traister
Yosief Ataklti
Original Assignee
Sandisk Corporation
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Priority claimed from US11/864,740 external-priority patent/US8099632B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Publication of WO2009021176A2 publication Critical patent/WO2009021176A2/fr
Publication of WO2009021176A3 publication Critical patent/WO2009021176A3/fr
Publication of WO2009021176A9 publication Critical patent/WO2009021176A9/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • ROM read only memory
  • a ROM is typically masked out long in advance for the specific code/application and once masked and subsequently manufactured it cannot be changed in most scenarios. This thus results in large inventories of product that may or may not be well received in the marketplace. For consumer related devices where inventory must be produced before demand can be accurately gauged, this may result in unsold inventory.
  • NAND memory typically includes memory management operations to accommodate for the physical limitations of the NAND memory cells. These operations may be taking place when a read command is received, and thus the called for data may not be immediately received.
  • Various aspects and embodiments allow for a flash memory storage device with variable latency in responding to data storage commands or requests from a host device to be used in demanding environments where a ROM might otherwise be used to provide a program.
  • mechanisms within the flash memory controller allow the memory controller to accommodate both the physical limitations of the flash memory and the needs of a host processor to quickly and regularly access the memory.
  • flash memory storage device allows the flash memory storage device to be used not only in read intensive environments but also in isochronous systems where flow control cannot be introduced.
  • embodiments of the present invention may be used is systems where there is not a wait, busy, or ready signal to assert or de-assert on the bus.
  • FIGS. IA and IB are block diagrams of a non-volatile memory and a host system, respectively, that operate together.
  • FIG. 2 is an illustration of isochronous system read operation.
  • FIG. 3 is a scan and update state diagram.
  • FIGS. 4A and 4B illustrate a first embodiment of command and data structure and flow for normal and wait flow respectively.
  • FIGS. 5 A and 5B illustrate a second embodiment of command and data structure and flow for normal and wait flow respectively.
  • FIGS. 6 A and 6B illustrate a third embodiment of command and data structure and flow for normal and wait flow respectively. DESCRIPTION OF EXEMPLARY EMBODIMENTS
  • a flash memory includes a memory cell array and a controller.
  • the 13 include an array 15 of memory cells and various logic circuits 17.
  • the logic circuits 17 interface with a controller 19 on a separate chip through data, command and status circuits, and also provide addressing, data transfer and sensing, and other support to the array 13.
  • a number of memory array chips can be from one to many, depending upon the storage capacity provided.
  • the controller and part or the entire array can alternatively be combined onto a single integrated circuit chip but this is currently not an economical alternative.
  • a typical controller 19 includes a microprocessor 21, a read-only- memory (ROM) 23 primarily to store firmware and a buffer memory (RAM) 25 primarily for the temporary storage of user data either being written to or read from the memory chips 11 and 13.
  • Circuits 27 interface with the memory array chip(s) and circuits 29 interface with a host though connections 31. The integrity of data is in this example determined by calculating an ECC with circuits 33 dedicated to calculating the code. As user data is being transferred from the host to the flash memory array for storage, the circuit calculates an ECC from the data and the code is stored in the memory.
  • connection 31of memory of Figure IA mate with connections 31' of a host system, an example of which is given in Figure IB.
  • a typical host also includes a microprocessor 37, a ROM 39 for storing firmware code and RAM 41.
  • Other circuits and subsystems 43 often include a high capacity magnetic data storage disk drive, interface circuits for a keyboard, a monitor and the like, depending upon the particular host system.
  • Some examples of such hosts include desktop computers, laptop computers, handheld computers, palmtop computers, personal digital assistants (PDAs), MP3 and other audio players, digital cameras, video cameras, electronic game machines, wireless and wired telephony devices, answering machines, voice recorders, network routers and others.
  • the memory of Figure IA may be implemented as a small enclosed card, cartridge, or drive containing the controller and all its memory array circuit devices in a form that is removably connectable with the host of Figure IB. That is, mating connections 31 and 31' allow a card to be disconnected and moved to another host, or replaced by connecting another card to the host.
  • the memory array devices may be enclosed in a separate card that is electrically and mechanically connectable with a card containing the controller and connections 31.
  • the memory of Figure IA may be embedded within the host of Figure IB, wherein the connections 31 and 31' are permanently made. In this case, the memory is usually contained within an enclosure of the host along with other components.
  • NAND memory media errors are introduced through device cell stresses induced by read and write operations.
  • the useful life of a NAND memory can be maximized by monitoring the increasing error levels and moving the data to a physical location which has experienced lower access activity.
  • this media repair activity is performed as a background operation. These operations happen during bus idle times or during read or write requests extended by hardware flow control techniques.
  • blocks are occasionally copied or updated to other locations when the physical reliability of a particular block cannot be depended upon. For example, if the error rate of a block appears as if it will shortly be unreadable, even with multiple read cycles and thresholds, a block may be updated. For example, if the number of errors is not correctable with ECC, an update would be necessary.
  • NAND NAND
  • read operations cause disturbs, one of the aforementioned cell stresses.
  • Certain systems incorporating NAND memory may be very read intensive, thus increasing the importance of the data correction and scrub techniques.
  • a video game system reads the memory very often to update the image being displayed during the game. While the background display may only be written once, it is read very frequently. Thus the effect of disturbs will be particularly noteworthy in such a case and must be mitigated.
  • the purpose of a scrub operation is to detect disturbed storage elements before the number of bits in error and the level of shifted cells exceed any recovery schemes available on the memory system. To this end, it is generally desirable to detect disturb as early as possible and before much of the guard band for a given voltage threshold level has been lost to disturb.
  • Flash memories usually store data at discrete states, or ranges of charge storage levels, each of which is separated from other states by some guard band. There is generally a nominal sensing level of discrimination between each state above which a storage element is deemed to be in one state, and below which it is deemed to be in another state. As a given storage element is disturbed, the level to which it has been programmed or erased may begin to shift. If the level of the storage element approaches the sensing level of discrimination, or crosses over it, it produces data in a state different that that to which it was programmed or erased. The error will generally manifest itself as one or more bits in error in the data, and will generally be detected through the use of ECC covering the data field.
  • disturb mechanisms are known to affect data storage levels in a specific way, it is possible to target detection of those specific disturb mechanisms by margining read conditions toward the expected level shifts. While the ideal situation would be to target the expected disturb mechanisms with a single read operation under a single set of margin conditions, this may not usually be possible. It may be necessary to perform multiple read operations under different conditions.
  • the scrub read conditions may be margined in order to target certain expected disturb mechanisms, or to simply check for sufficient margin in the stored levels. Whether the data was read under nominal or margined conditions, the decision whether or not to take corrective action may be based on the number of bits in error detected during the scrub read operation. For example, if the number of bits in error are below the ECC correction capabilities of the system, the system may decide to defer the corrective action, or to ignore the error altogether.
  • the system may make the decision to correct based on other factors such as the pattern of bits in error.
  • the ECC correction capabilities may be sensitive to bit error pattern, or bit error patterns may be indicative of a particular known disturb mechanism in the nonvolatile memory. There may be other reasons for basing the threshold on bit error patterns.
  • the bit error pattern is generally revealed during the ECC correction operation.
  • the reasons for doing so may include real-time considerations. For example a host may require a certain data transfer, and dedicating resources to scrub corrective action at certain times might impact the ability of the memory system to meet the guaranteed data rate.
  • the memory system may queue the scrub corrective action operation parameters for later processing, at a time when performing the scrub corrective action would not impact performance to the host.
  • the scrub corrective action operations may be deferred until sometime later in the host command processing, sometime after the command processing, or until a later host command. The main point is that the scrub operation parameters would be stored and processed at a later time when it is most convenient to the host.
  • a scrub read is performed on a small proportion of the memory cells in the block, such as one or a small number of sectors, and the quality of the scrub read data is checked by use of the ECCs stored with the sectors of data.
  • the scrub read most commonly, but not always, reads data stored in one or more pages that were not read in response to the command. If there are an excessive number of errors in the scrub read data, then the entire block is refreshed.
  • a refresh operation involves reading all the data from the block, correcting the errors in the data by use of the ECCs, and then rewriting the corrected data into another block that has been erased.
  • This process is desirably performed often enough to avoid the stored data being disturbed to the extent that they are no longer correctable by use of the ECCs, but not so often that performance of the memory system is excessively degraded.
  • the scrub read By limiting the scrub read to a small amount of the storage capacity of a block, such as just one or a few sectors or one or two pages, the overhead added to the memory operation by the scrub process is minimized.
  • the scrub read and any resulting refresh are preferably performed in the background, when the memory system is not otherwise responding to commands to read or write data therein.
  • the scrub read preferably reads data stored in a page or pages of the block that are more vulnerable to having their data disturbed by the particular partial block command read than other pages of the block. It is preferred to identify a single most vulnerable sector or page, whenever that is possible, and then scrub read the data from it. Either way, a worse case picture of the quality of the data in the block is obtained with only a small amount of data needed to be scrub read. The impact on the performance of the memory system by such scrub reads is therefore minimized.
  • Objective criteria may be established to identify the portion of the group or block of memory cells, such as a page, that is more vulnerable to being disturbed by the command read than other portions of the group. At least some of the criteria are dependent upon the structure of the memory array.
  • Another of the criteria for selecting the more vulnerable page(s) may be established to be dependent upon which pages of the block have been read in response to the command and in what order. For instance, in the above example, even if one or both of the extreme pages of the block has been read in response to the command, one of these pages is desirably scrub read if it was read early in the execution of the command and therefore subject to thereafter being disturbed by the subsequent reading of other pages of the block. In such a case, the ECC check performed as part of the normal command read may no longer represent the quality of the data in that page because of potential disturbs that could have resulted from reading subsequent pages.
  • the ECC bit error checking that occurs as part of a normal data read provides information of the quality of the data in those page(s) so that another scrub read of the same page(s) need not take place.
  • a further possible one of the criteria for identifying a more vulnerable page is to identify a page that has not been read in response to the command but which is physically located adjacent a page that was so read. Disturbs are more likely to occur on this page than other pages in the block, with the possible exception of the two pages at the extreme ends of NAND memory strings. This will depend upon the specific structure of the memory cell array.
  • Yet another of the established criteria can be the relative patterns of data stored in the pages of the block. For example, in the NAND memory array, disturbs of the charge levels of memory cells in states near or at their lowest stored charge levels is more likely than those with charge levels near or at their highest stored charge levels.
  • the ECC threshold for triggering a corrective action may be anywhere in the range of ECC correction capabilities, but is preferably around 75% of the capability. For example, if the ECC is capable of correcting 12 bits, corrective action may be triggered when around 8 bits in error are detected.
  • Handling NAND flash media refresh operations efficiently is important in a low latency operating environment, especially an Isochronous system environment.
  • the memory controller 19 incorporates an isochronous system (“IS”) interface (the "ISI”) in addition to the other interfaces such as those for a Secure Digital (“SD”) card, Memory Stick, Compact Flash card, USB flash drive, or the like.
  • IS isochronous system
  • SD Secure Digital
  • Memory Stick Memory Stick
  • Compact Flash Compact Flash
  • USB flash drive or the like.
  • the ISI monitors media error statistics and take action whenever needed to scrub or update the media, as described earlier. Since the IS environment does not allow flow control at the transaction level, a new approach has been implemented for media repair.
  • IS Isochronous system
  • FIG. 2 One version of the IS read operation is shown in FIG. 2. From the time the last byte of the command is issued until the first byte of read data is returned is 230 usecs.
  • the system processor read operation/structure shown in FIG. 2 has been modified in order to better manage process delays of the NAND memory
  • the system processor command structure is augmented by wrapping the mode dependant RD_PAGE commands with a following READ_ST1 (read status one register) command within the same cycle or period.
  • READ_ST1 read status one register
  • FIG. 4A Each cycle 404A-X contains both a data operation and a status operation.
  • Two bits have been defined in the STATUSl register to relay the need for media error processing (flash memory data integrity operations). These bits can be seen in Table 1.
  • the RefReq bit (D2) will be set as a request for the host to initiate a refresh operation. This request is not considered urgent. The host will honor this request in as timely a manner as possible without sacrificing user interactivity.
  • the second bit, RefReqUrg (D3) is an urgent request for a refresh operation. This host must find a way to honor this request as quickly as possible without regard for effects on the user experience.
  • the queuing of 4 block copies is preferably used to denote an urgent request in the case where the queue holds eight total entries. In other words, when the queue is 50% full the request will be an urgent request.
  • the range in the ratio of entries to available slots of the queue used to indicate an urgent request may be anywhere between ten and ninety percent. The ratio selected will affect the performance of the overall system and may be tailored to each application. A lower ratio will require the host to respond more quickly and may result in higher data reliability or integrity while a higher ratio will allow for better system response because the host will be able to allocate more time to running the processor application (e.g. game).
  • a state diagram of media error processing interacting with the host's refresh status bits is shown in FIG. 3.
  • the All Clear state 302 represents the initial media error free state.
  • the (front end) memory controller firmware will need to post RefReq status (state 306) to STATUSl.
  • the memory controller (front end) firmware will initiate a media scan operation (state 314). If during the time between posting RefReq and receipt of the RFS_BLK command the block update queue goes not empty an update operation rather then a scan operation will be executed.
  • the index save serves to ensure guaranteed error processing across power cycles. Since the index save operation is short, performing the save at the highest priority will not negatively impact the gaming experience. There is a rare but possible situation where the number of copy requests in the queue start to accumulate. Whenever there are more than 4 copies in the queue the system should treat this as a critical event. If this queue overflow is detected the request will be urgent and the time hit will be at a maximum, as represented by state 326.
  • the base assumption is that the host will be timely in it's response to any refresh request, urgent or not.
  • the maximum latency between refresh status requests and the issue of a RFS_BLK command will be less than 6400 read operations. This is 1/10 the number of reads expected to complete successfully before an update event would be required.
  • the maximum latency allowed may be a controlling criteria. For example, a gaming system may specify a maximum latency period, of 230 microseconds
  • a scan and/or copy queue is used to keep track of what blocks or other units of memory need to be scanned and/or copied. The queue may be stored in RAM or alternatively in the NAND flash memory itself. For more information on this, please refer to U.S. Patent Application No. 11/726,648 entitled "Methods For Storing Memory Operations In A Queue" filed 3/21/2007, which is hereby incorporated by reference in the entirety.
  • FIG. 4A illustrates a system processor command structure incorporating the read status (READ-STl discussed above) command 410 in each cycle/period 404A-X in order to read the STATUSl register of Table 1 above.
  • the command/address 406 is followed by the data 408 and the read STATUSl command 410.
  • the register will report that no action is needed.
  • FIGS. 5 A and 5B illustrate another embodiment of a system processor command structure.
  • the mechanism for reporting the need to attend to the flash memory utilizes a data token 510 within each period/cycle 504A-X following the command/address 506 and data 508.
  • the host processor will wait some number of periods/cycles before sending another command.
  • the data token would comprise additional bits of information beyond the data 508 associated with the command (e.g. the data sent in response to a read). This will allow the memory to perform needed data integrity operations.
  • the data token would contain some or all of the information contained in the STATUSl register directly, as opposed to the mechanism in FIGS.
  • FIGS. 6A and 6B illustrate another embodiment of a system processor command structure.
  • the mechanism for reporting the need to attend to the flash memory utilizes a side band bits 510 within each period/cycle
  • the host processor will wait some number of periods/cycles before sending another command.
  • the side band bits 610 contain some or all of the information contained in the STATUSl register directly, or alternatively may direct the processor to read the STATUSl register.
  • FIGS. 4-6 All of the embodiments illustrated in FIGS. 4-6 can be used to signal the need for extra time for data integrity operations in systems where a wait , busy or ready signal is not available and thus can be thought of as alternatives to flow control in isochronous systems lacking flow control.
  • a block refresh cycle is initiated whenever the host issues a RFS_BLK command. Once a RFS_BLK command is issued, only RD_STATUS1 commands are allowed until the refresh operation completes. Completion of refresh is indicated when both RefReq and RefReqUrg bits are set to zero.
  • the embodiments described above ensure that if the power to the NAND memory device is interrupted that the information stored in the memory will be available when the power is restored. For example, a block that needs to be copied to another location that was in the process of being updated will be taken care of upon power restoration because it will be contained in the copy queue. This is true even given the demanding read requirements and timing limitations of an isochronous system such as that of a time sensitive application like video games and the like.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention concerne une latence variable associée à une mémoire Flash du fait que les opérations d'intégrité des données de fond sont gérées afin de permettre d'utiliser la mémoire Flash dans des systèmes isosynchrones. Un processeur système est régulièrement averti de la nature et de l'urgence des requêtes de temps, pour assurer l'intégrité des données. Des interruptions minimum du traitement du système sont obtenues et l'opération est assurée en cas d'interruption de l'alimentation.
PCT/US2008/072609 2007-08-08 2008-08-08 Urgence et manipulation de fenêtre temporelle pour traiter des opérations de mémoire imprévisibles WO2009021176A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US95469407P 2007-08-08 2007-08-08
US60/954,694 2007-08-08
US11/864,740 US8099632B2 (en) 2007-08-08 2007-09-28 Urgency and time window manipulation to accommodate unpredictable memory operations
US11/864,740 2007-09-28
US11/864,793 US8046524B2 (en) 2007-08-08 2007-09-28 Managing processing delays in an isochronous system
US11/864,793 2007-09-28

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WO2009021176A2 true WO2009021176A2 (fr) 2009-02-12
WO2009021176A3 WO2009021176A3 (fr) 2009-04-16
WO2009021176A9 WO2009021176A9 (fr) 2009-05-28

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Cited By (2)

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US8046524B2 (en) 2007-08-08 2011-10-25 Sandisk Technologies Inc. Managing processing delays in an isochronous system
US20120311408A1 (en) * 2011-06-03 2012-12-06 Sony Corporation Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program

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US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques
US20060101210A1 (en) * 2004-10-15 2006-05-11 Lance Dover Register-based memory command architecture
US20060161728A1 (en) * 2005-01-20 2006-07-20 Bennett Alan D Scheduling of housekeeping operations in flash memory systems

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US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US20050073884A1 (en) * 2003-10-03 2005-04-07 Gonzalez Carlos J. Flash memory data correction and scrub techniques
US20060101210A1 (en) * 2004-10-15 2006-05-11 Lance Dover Register-based memory command architecture
US20060161728A1 (en) * 2005-01-20 2006-07-20 Bennett Alan D Scheduling of housekeeping operations in flash memory systems

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Publication number Priority date Publication date Assignee Title
US8046524B2 (en) 2007-08-08 2011-10-25 Sandisk Technologies Inc. Managing processing delays in an isochronous system
US8099632B2 (en) 2007-08-08 2012-01-17 Sandisk Technologies Inc. Urgency and time window manipulation to accommodate unpredictable memory operations
US20120311408A1 (en) * 2011-06-03 2012-12-06 Sony Corporation Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program
US8862963B2 (en) * 2011-06-03 2014-10-14 Sony Corporation Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program

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WO2009021176A9 (fr) 2009-05-28

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