WO2009015276A3 - High integrity and high availability computer processing module - Google Patents

High integrity and high availability computer processing module Download PDF

Info

Publication number
WO2009015276A3
WO2009015276A3 PCT/US2008/071023 US2008071023W WO2009015276A3 WO 2009015276 A3 WO2009015276 A3 WO 2009015276A3 US 2008071023 W US2008071023 W US 2008071023W WO 2009015276 A3 WO2009015276 A3 WO 2009015276A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing module
computer processing
integrity
processing
lane
Prior art date
Application number
PCT/US2008/071023
Other languages
French (fr)
Other versions
WO2009015276A2 (en
Inventor
Jay R Pruiett
Gregory R Sykes
Timothy D Skutt
Original Assignee
Ge Aviat Systems Llc
Jay R Pruiett
Gregory R Sykes
Timothy D Skutt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ge Aviat Systems Llc, Jay R Pruiett, Gregory R Sykes, Timothy D Skutt filed Critical Ge Aviat Systems Llc
Priority to BRPI0813077A priority Critical patent/BRPI0813077B8/en
Priority to CA2694198A priority patent/CA2694198C/en
Priority to JP2010518384A priority patent/JP5436422B2/en
Priority to CN200880109465.3A priority patent/CN101861569B/en
Priority to EP08796546A priority patent/EP2174221A2/en
Publication of WO2009015276A2 publication Critical patent/WO2009015276A2/en
Publication of WO2009015276A3 publication Critical patent/WO2009015276A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1687—Temporal synchronisation or re-synchronisation of redundant processing components at event level, e.g. by interrupt or result of polling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)

Abstract

A high-integrity, N-lane computer processing module (Module), N being an integer greater than or equal to two. The Module comprises one Hosted Application Element and I/O Element per processing lane, a Time Management unit (TM) configured to determine an equivalent time value for a request made by software running on each of the N processing lanes, irrespective as to when the request is actually received and acted on by each of the N processing lanes, and a Critical Regions Management unit (CRM) configured to enable critical regions within the respective lane to be identified and synchronized across all of the N processing lanes.
PCT/US2008/071023 2007-07-24 2008-07-24 High integrity and high availability computer processing module WO2009015276A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BRPI0813077A BRPI0813077B8 (en) 2007-07-24 2008-07-24 computer processing module system
CA2694198A CA2694198C (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module
JP2010518384A JP5436422B2 (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module
CN200880109465.3A CN101861569B (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module
EP08796546A EP2174221A2 (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US93504407P 2007-07-24 2007-07-24
US60/935,044 2007-07-24
US13871708A 2008-06-13 2008-06-13
US12/138,717 2008-06-13

Publications (2)

Publication Number Publication Date
WO2009015276A2 WO2009015276A2 (en) 2009-01-29
WO2009015276A3 true WO2009015276A3 (en) 2009-07-23

Family

ID=40149643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/071023 WO2009015276A2 (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module

Country Status (6)

Country Link
EP (1) EP2174221A2 (en)
JP (1) JP5436422B2 (en)
CN (1) CN101861569B (en)
BR (1) BRPI0813077B8 (en)
CA (1) CA2694198C (en)
WO (1) WO2009015276A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011078630A1 (en) * 2011-07-05 2013-01-10 Robert Bosch Gmbh Method for setting up a system of technical units
US8924780B2 (en) * 2011-11-10 2014-12-30 Ge Aviation Systems Llc Method of providing high integrity processing
CN104699550B (en) * 2014-12-05 2017-09-12 中国航空工业集团公司第六三一研究所 A kind of error recovery method based on lockstep frameworks
US10248156B2 (en) 2015-03-20 2019-04-02 Renesas Electronics Corporation Data processing device
US10599513B2 (en) * 2017-11-21 2020-03-24 The Boeing Company Message synchronization system
US10802932B2 (en) 2017-12-04 2020-10-13 Nxp Usa, Inc. Data processing system having lockstep operation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
EP0969374A2 (en) * 1998-06-30 2000-01-05 Sun Microsystems, Inc. Determinism in a multiprocessor computer system and monitor and processor therefor
WO2006045786A1 (en) * 2004-10-25 2006-05-04 Robert Bosch Gmbh Method and device for mode switching and signal comparison in a computer system comprising at least two processing units
GB2425380A (en) * 2005-04-19 2006-10-25 Hewlett Packard Development Co Trading off reliability and performance in a multiprocessor system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
JP3123844B2 (en) * 1992-12-18 2001-01-15 日本電気通信システム株式会社 Redundant device
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
EP1398700A1 (en) * 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Method and circuit device for synchronizing redundant processing units
US7290169B2 (en) * 2004-04-06 2007-10-30 Hewlett-Packard Development Company, L.P. Core-level processor lockstepping
CN100392420C (en) * 2005-03-17 2008-06-04 上海华虹集成电路有限责任公司 Multi-channel analyzer of non-contact applied chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
EP0969374A2 (en) * 1998-06-30 2000-01-05 Sun Microsystems, Inc. Determinism in a multiprocessor computer system and monitor and processor therefor
WO2006045786A1 (en) * 2004-10-25 2006-05-04 Robert Bosch Gmbh Method and device for mode switching and signal comparison in a computer system comprising at least two processing units
GB2425380A (en) * 2005-04-19 2006-10-25 Hewlett Packard Development Co Trading off reliability and performance in a multiprocessor system

Also Published As

Publication number Publication date
CA2694198C (en) 2017-08-08
BRPI0813077B1 (en) 2020-01-28
BRPI0813077A2 (en) 2017-06-20
JP2010534888A (en) 2010-11-11
WO2009015276A2 (en) 2009-01-29
EP2174221A2 (en) 2010-04-14
JP5436422B2 (en) 2014-03-05
CN101861569A (en) 2010-10-13
CA2694198A1 (en) 2009-01-29
BRPI0813077B8 (en) 2020-02-27
CN101861569B (en) 2014-03-19

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