WO2009015192A1

WO2009015192A1 - Methods for growing selective areas on substrates and devices thereof

Info

Publication number: WO2009015192A1
Application number: PCT/US2008/070866
Authority: WO
Inventors: Philip Lamarre; Theodore Moustakas
Original assignee: Photronix, Inc.
Priority date: 2007-07-23
Filing date: 2008-07-23
Publication date: 2009-01-29

Abstract

Methods for fabrication of semiconductor devices may form one or more retrograde well structures using one or more refractory or high growth temperature resistant materials. The retrograde well structure(s) may thus be used to provide selective growth using one or more growth materials and high temperature growth techniques, such as MBE, MOCVD, VPE, or MOMBE. Articles used for fabrication of semiconductor devices may include one or more retrograde well structures formed of refractory or high growth temperature resistant materials on a substrate or on a growth material on the substrate. Semiconductors, such as a heterojunction bipolar transistor (HBT), may be formed using the methods and/or articles described herein.

Description

METHODS FOR GROWING SELECTIVE AREAS ON SUBSTRATES AND DEVICES THEREOF

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of SBIR Contract No. FA8718-04-C-0070 awarded by the United States Air Force.

FIELD

The invention relates to the manufacture of semiconductor devices and other materials, and more particularly, relates to using refractory or high growth temperature resistant materials to form a retrograde well structure, which may be used with many different high temperature growth techniques to form selective areas of growth.

BACKGROUND

In the fabrication of semiconductor devices, the first step is generally epitaxial layer deposition, followed by standard semiconductor processing steps. The most commonly used patterning techniques are chemical and reactive ion etching and ion implantation. However, such techniques damage the fabrication materials. Selective area epitaxy, which grows epitaxial semiconductor layers selectively on predefined areas of a substrate wafer, allows for significantly more flexibility in device design than the traditional approach and is inherently a "damage free" method. Furthermore, such selective area epitaxy can be performed more than once on the same wafer, each time on different selected areas with a different semiconductor composition or doping, to get complex structures amenable to integration of a variety of functions on a single chip, which could not be achieved by the traditional approaches. In general, to achieve selective growth, substrate regions on which material growth is not desired are masked with mechanical masks. Samples are then loaded into growth systems for the selective regrowth.

Various studies on selective area growth have been performed. Nonetheless, these studies are not without their shortcomings. For example, it is difficult to get high selectivity in molecular beam epitaxy (MBE) growth. MBE, which is basically a multiple-source evaporation process material, deposits material on the mask as well as through the opening onto the substrate. In most applications, it is desirable to remove the polycrystalline matter from the wafer. As mentioned above, to achieve the full potential of selective area growth, one needs to be able to apply it more than once to the same wafer. This is impossible if the polycrystalline deposits remain from the previous step. Mechanical masks are also not practical for integrated circuit type applications, which require micron scale features in micron scale alignment across the entire wafer.

There are also problems associated with simultaneous growth (up from the bottom and out from the walls) of an etched feature. Such problems can change line shapes and hence severely limit the applicability of such a process to fine lithographic features. Other conventional approaches pose issues because nitride semiconductor material can be very difficult to wet etch.

DESCRIPTION OF THE DRAWINGS Other features and advantages of the invention may also be apparent from the following detailed description thereof, taken in conjunction with the accompanying drawings, which may depict preferred aspects by way of example, not by way of limitations.

FIGS. IA- IG are side schematic views illustrating a method for fabrication of a semiconductor device, consistent with embodiments of the present invention.

FIGS. 2A-2G are side schematic views illustrating another method for fabrication of a semiconductor device, consistent with embodiments of the present invention.

FIGS. 3A-3H are side schematic views illustrating a further method for fabrication of a semiconductor device, consistent with embodiments of the present invention.

FIG. 4 is a photograph of a MBE grown GaN based working HBT made in accordance with an embodiment of the present invention.

FIG. 5 illustrates characteristics for a MBE grown HBT made in accordance with an embodiment of the present invention. FIG. 6 illustrates a step height as a function of etching time of an etched depth of a refractory material, consistent with an embodiment.

FIG. 7 is an image illustrating an undercut and lip structure formed by a method, consistent with an embodiment.

FIGS. 8 A and 8B are SEM images of a growth layer deposited by a method, consistent with an embodiment.

FIG. 9 illustrates a room temperature CL spectrum of a growth layer in different areas, consistent with an embodiment.

FIG. 10 is an image illustrating an undercut and lip structure with a deposited growth layer, consistent with an embodiment.

FIG. 11 illustrates thicknesses of the growth layer and layers of refractory materials before and after lift-off, consistent with an embodiment.

FIGS. 12A and 12B are images illustrating regions on the semiconductor device after lift off of the refractory materials, consistent with an embodiment. FIG. 13 illustrates a CL measurement of a semiconductor device after lift off of the refractory materials, consistent with an embodiment.

FIG. 14 is an image of a semiconductor device formed using a method for fabrication of semiconductor devices, consistent with an embodiment.

FIG. 15 illustrates SEM images of a semiconductor device formed using a method for fabrication of semiconductor devices, consistent with an embodiment.

FIG. 16 illustrates CL measurements of areas or regions on a semiconductor device before and after lift-off, consistent with an embodiment.

FIG. 17 is a photomicrograph image of a semiconductor device formed using a method of fabrication of semiconductor devices, consistent with an embodiment. FIG. 18 illustrates three-dimensional images and associated height profiles of semiconductor devices formed using a method of fabrication of semiconductor devices, consistent with an embodiment.

FIG. 19 is an image of semiconductor devices formed using a method of fabrication of semiconductor devices, consistent with an embodiment.

DETAILED DESCRIPTION

Consistent with embodiments described herein, methods for fabrication of semiconductor devices may form one or more retrograde well structures using one or more refractory or high growth temperature resistant materials. The retrograde well structure(s) may thus be used to provide one or more selective growths using one or more growth materials and high temperature growth techniques including, but not limited to, MBE, MOCVD, VPE, or MOMBE. Consistent with the embodiments described herein, articles for fabrication of semiconductor devices may include one or more retrograde well structures formed of refractory or high growth temperature resistant materials on a substrate or on a growth material on the substrate. Semiconductor devices, such as a heterojunction bipolar transistor (HBT), may be formed using the methods and/or articles described herein. The semiconductor devices can be used in a variety of conventional and to be determined applications as will be appreciated by those of ordinary skill in the art.

As used herein, "high growth temperature" refers to temperatures at which high temperature growth techniques, such as, but not limited to, MBE, MOCVD, VPE, or MOMBE, are performed. In an embodiment, a high growth temperature may be about 200° C or greater and more particularly about 400° C or greater. In a MBE chamber, for example, MBE growth may be performed at high temperatures such as 77O⁰C for GaN growth.

High growth temperature materials refers to materials including, but not limited to, refractory materials, which are capable of withstanding such high growth temperatures without substantial damage. One example of such a material is refractory ceramic, such as SiO₂, which can withstand high temperature and can be easily coated on a substrate by various methods such as, but not limited to, PECVD, sputtering, ebeam evaporation and spinning. The material can also be easily removed by spraying or just dipping in a wet HF-based etchant bath. SiO₂ may also be used as a masking material in the selective area growth by CVD, VPE or LPE. In an embodiment, a retrograde well can be formed from a refractory metal, refractory ceramic or combinations thereof (e.g., a multi layer stack of refractory materials). More specifically, a semiconductor wafer or substrate may include a retrograde well formed by a refractory ceramic, such as SiO₂, and a refractory metal, such as chromium, on the refractory ceramic. The growth material may be a nitride layer deposited in the retrograde well and on the refractory metal. The refractory metal may form a lip over the refractory ceramic defining an undercut such that the growth material on the substrate is not connected to the growth material on the refractory metal. The refractory ceramic and refractory metal may then be removed (also referred to as lift off) leaving the selective growth. The retrograde well structure may be formed with a negative slope profile, which facilitates the subsequent deposition and lift-off as it prevents deposition on sidewalls and can allow contact with a sacrificial layer. Characteristics of negative slope profiles or retrograde wells are understood by those of ordinary skill in the art. Preferably, a retrograde well comprises interior angles from the substrate or growth layer(s) of less than about 90 degrees. For example, a retrograde well can comprise interior angles from about 90 to 80 degrees, 80 to 70 degrees, 70 to 60 degrees, 60 to 50 degrees, 50 to 40 degrees, 40 to 30 degrees, 30 to 20 degrees, 20 to 10 degrees or 10 to less than one degree. Each interior angle for a retrograde well also need not be similar or identical. In one aspect, a retrograde well can comprise interior angles from the substrate from about 90 to 85 degrees, 80 to 75 degrees, 70 to 65 degrees, 60 to 55 degrees, 50 to 45 degrees, 40 to 35 degrees, 30 to 25 degrees, 20 to 15 degrees or 15 to less than 5 degrees. The method may also form a well comprising interior angles from the substrate of more than about 90 degrees such as, for example, 120, 150 or less than 180 degrees. Deposits on the substrate may also provide satisfactory adhesion. Satisfactory adhesion can provide for complete or total adhesion or less than complete or total adhesion as characterized by a deposit being lifted or torn from at least one adhesion surface, for example, on a substrate, photoresist, material, refractory ceramic, refractory metal or combinations thereof. In one aspect, satisfactory adhesion can provide for greater than about 99%, 95% or 90% by weight of deposit remaining adhered to one or more adhesion surfaces after lift off or tearing. Preferably, satisfactory adhesion can provide for greater than about 90 to 80%, 80 to 70%, 70 to 60%, 60 to 50%, 50 to 40%, 40 to 30% or 30 to 20% by weight of deposit remaining adhered to one or more adhesion surfaces after lift off or tearing. Preferably, deposits may not be too thin and/or brittle so as to tear along adhesion surfaces.

In an embodiment, the retrograde well may be formed by applying a patterned material to the refractory or high growth temperature material (e.g., the refractory ceramic) and then etching the refractory or high growth temperature material. After the formation of a SiO₂ layer, for example, a photoresist may be applied to the surface of the wafer or substrate. After exposing the photoresist using a mask and developing, the patterned photoresist may then serve as an etching mask for the SiO₂. In one aspect, HF may be used to wet etch the SiO₂ such that oxide leaves an isotropic etch profile and the SiO₂ profiling forms a slope.

A patterned material such as, for example, a metal can be used as an etching mask for any suitable material such as a refractory ceramic including, but not limited to, SiO₂. While any suitable etchant (for example, HF) wet etches SiO₂, it may not attack the patterned material. In one aspect, the positive slope can remain after etching and the patterned material may confine the area where desirable growth takes place to form the retrograde well. In another aspect, a retrograde well can be formed with only one material such as, for example, a metal or ceramic. Although wishing not to be bound by theories or conventions, due to the lip formed by the patterned material during wet etching, other materials or growth layers can be grown discontinuously. Material grown on the patterned material or metal can be easily liftoff by an etchant selected to attack, for example, the refractory ceramic through the undercut. One of ordinary skill in the art will be able to select appropriate etchants based on various process conditions and materials including, but not limited to, a refractory ceramic.

According to embodiments described herein, the refractory metal can be patterned through different procedures or techniques. Exemplary techniques include, but are not limited to, standard lithography and liftoff. In another aspect, selective etching can be performed.

In one aspect, a method or article of the invention includes a substrate that can include includes silicon, sapphire, gallium arsenide, magnesium oxide, zinc oxide silicon carbide or combinations thereof. Preferably, the substrate can include (100) silicon, (111) silicon, (0001) sapphire, (11-20) sapphire, (1-102) sapphire, (111) gallium arsenide, (100) gallium arsenide, magnesium oxide, zinc oxide, silicon carbide or combinations thereof.

Semiconductor devices may include standard substrates such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), silicon carbide, zinc oxide and sapphire. The substrate may also undergo nitridation before any materials are deposited thereon. Semiconductor layers grown or any other layers and materials can be deposited by conventional and to be developed techniques. Examples of these techniques include halide vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). Other conventional or future thin film deposition systems may also be used. A layer of a semiconductor device may also include a group III material such as gallium (Ga), aluminum (Al), indium (In) or any combination of these materials.

In another aspect, one or more growth layers may include an element, group III element, group V element, dopant or combinations thereof. For example, the growth layer(s) can comprise a nitridated layer, buffer layer, epitaxial layer or combinations thereof. The growth layer(s) may be deposited by, for example, HVPE, MBE, MOCVD or combinations thereof.

The growth layer(s) may also include a first growth layer that can include

Al_xGai__xN or In_xGai__xN in which x is from 0 to 1. Exemplary first growth layers can include, but are not limited to, AlGaN, InGaN, GaN and AlN. The growth layer(s) can also include a second growth layer that can include an element, group III element, group V element, dopant or combinations thereof. For example, the second growth layer can include a nitridated layer, buffer layer, epitaxial layer or combinations thereof. In another aspect, the growth layer(s) can also include a second growth layer that can comprise Al_xGai__xN or In_xGai__xN in which x is from 0 to 1. Examples of second growth layers include, but are not limited to, AlGaN, InGaN, GaN and AlN.

In one aspect, a photoresist material used to perform methods described herein may include, but is not limited to, a resin. The photoresist material can comprise a film capable of being photopolymerized, polymerized, thermally cured or photocured after deposition. The photoresist may also be sensitive to ultraviolet (UV) or near UV light. UV or near UV light introduced to the layer may be from a source such as a mercury or hydrogen arc source or discharge lamp. The UV or near UV light can photocure or photopolymerize the photoresist after deposition. A photoresist layer may also include a combination of materials including, but not limited to, polymeric resins.

An example of a resin that can be photocured is the photoresist S 1808 from Shipley. Preferably, a photoresist can adhere well to an underlying surface and exhibit good wettability. UV or near UV curing of a photoresist and post-exposure baking of the resist can also be performed. Deposition of an exemplary photoresist can involve spin- on deposition of the photoresist, a soft bake, exposure to UV or near UV light, a postexposure baking (optional), selective removal of the entire photoresist or portion thereof. In one aspect, the photoresist can be removed chemically, mechanically or by combinations thereof. A photoresist can also be dissolved with, for example, a solvent. Exemplary solvents include cyclopentanone, GBL, diacetone alcohol, methyl isobutyl ketone, ethyl lactate or PGME. The solvent can also be rinsed and the resist subjected to a final cure in, for example, a convection oven. Suitable deposition techniques for a photoresist include, but are not limited to, spin-on deposition, screen printing, tape casting, cold pressing, ink jet printing, hot embossing or chemical vapor deposition.

After deposition, the photoresist can optionally be baked, for example, on a hot plate or in a convection oven so as to remove plasticizers, dispersants, binders, solvents or other materials present within the layer. A hot plate can allow such materials to be driven out, minimizes the formation of off-gassing bubbles. Baking of the layer promotes layer uniformity and adhesion properties. The exposure to UV or near UV light can be through an opening in a photomask so as to harden the photoresist or portions thereof. An exemplary photomask is comprised of chrome on fused silica or glass. After exposure to UV or near UV light, the resist can optionally be subjected to a post-exposure bake.

By way of example only, a substrate can have a thickness from about 0.01 angstrom (A) to 10 microns (μm), preferably, 10 A to 5 μm. A first growth layer can be deposited to a thickness ranging from about 0.01 angstrom (A) to 10 microns (μm), preferably, 10 A to 5 μm. Additional semiconductor or growth layers that are deposited can also have thicknesses ranging from about 0.01 angstrom (A) to 10 microns (μm), preferably, 10 A to 5 μm. These additional growth layers can include a group III elements. Growth layers can also be doped p or n-type by incorporating impurities therein. The layers can by doped by processes such as generally disclosed in U.S. Patent No. 5,633,192, the contents of which are hereby incorporated by reference herein. Such dopants can include selenium, germanium, magnesium zinc, magnesium, beryllium, calcium, Si, sulfur, oxygen or any combinations thereof. Growth layers may be grown by processes such as halide vapor phase epitaxy

(HVPE), metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Typical growth processes, conditions (including, but not limited to, temperatures and depositions rates) have been disclosed in U.S. Patent Nos. 5,725,674, 6,123,768, 5,847,397 and 5,385,862, the contents of each are hereby incorporated by reference herein. A growth layer can also be grown in the presence of nitrogen to yield a nitride layer. Examples of a nitride layer are GaN, indium (In) GaN, AlGaN, InGaN or AlN.

In one aspect, a device fabricated by a method or article described herein can comprise a first and second growth layers doped and arranged so as to form a p-n junction. The p-n junction can be a semiconductor device including, but not limited to, a forward-biased LED or photodetector. These devices can be used in applications that include, for example, electronic displays, solid state lights, computers or solar panels. Such as device may also comprise both p and n-type electrodes. These electrodes are generally integral or associated with (or otherwise in contact with) a correspondingly doped growth layer. Examples of p and n-type electrodes include silver, gold, platinum, titanium and combinations thereof. Several conventional processes are known for integrating an electrode with a device of the invention.

Referring to FIGS. 1A-1G, one method for fabrication of a semiconductor device is described in greater detail. A first refractory or high growth temperature resistant material 112, such as a refractory ceramic (e.g., SiO₂ or Si₃N₄), may be deposited on a substrate 102, such as a sapphire substrate including one or more epitaxial layers (FIG. IA). For example, ebeam deposition of 1,00OA of SiO₂ may be provided on the GaN epitaxial layer of a sapphire substrate. The GaN n-type epitaxial layer may be previously grown the sapphire substrate with the usual buffer layer.

A patterned photoresist material 104 may then be applied to the first refractory or high growth temperature resistant material 112 (FIG. IB). For example, the method may spin coat a photoresist such as Shipley S 1808 (e.g., at 3,000 RPMs), softbake the photoresist (e.g., at 95⁰C, 15 minutes), expose the photoresist with UV or DUV or X-ray or ebeam using photomask or direct write (e.g., 200 mJ on Karl Suss MJB3), image reverse the photoresist (e.g., Ammonia based image reversal), develop the photoresist (e.g., using Shipley developer MF-314 for 30 seconds), rinse in DI water, and oxygen plasma ash develop the photoresist pattern (e.g., to remove about 500A of photoresist). A second refractory or high growth temperature resistant material 114 (e.g., chromium or titanium or tungsten) may then be deposited on the photoresist material 104 and the first refractory or high growth temperature resistant material 112 (FIG. 1C). For example, 800A of chromium metal may be ebeam deposited. The photoresist material 104 may then be dissolved (e.g., using acetone to dissolve resist, followed by alcohol rinse and blow dry) leaving areas of the second refractory or high growth temperature resistant material 114 on top of the first refractory or high growth temperature resistant material 112 and one or more exposed portions 115 of the first refractory or high growth temperature resistant material 112 (FIG. ID).

The exposed portion(s) of the first refractory or high growth temperature resistant material 112 may then be etched (e.g., wet etched using a controlled method) to obtain an undercut beneath a lip 118, thereby forming a retrograde well 116 (FIG. IE). For example, the first refractory or high growth temperature resistant material 112 may be etched using very dilute HF:DI H₂O, 1:30, rinsed and blown dry. A growth layer 122 may then be deposited such that a portion of the growth layer 122 is deposited on the substrate 102 in the retrograde well 116. For example, MBE, MOCVD or other deposition techniques may be used to grow a thin layer of p-type GaN layer on n-type GaN layer.

The first and second refractory or high growth temperature resistant materials 112, 114 may then be removed leaving the selective growth layer 122 (FIG. IG). The first refractory or high growth temperature resistant material 112 (e.g., the dielectric material) may be dissolved to remove both materials 112, 114. For example, SiO₂ may be dissolved with strong HF acid, and the other materials may float off in the HF solution. Alternatively, the first and second materials 112, 114 may be removed using mechanical means or other techniques known to those skilled in the art. Referring to FIGS. 2A-2G, another method for fabrication of a semiconductor device is described in greater detail. According to this method, first and second refractory or high growth temperature resistant materials 212, 214 may be deposited on a substrate 202 (FIG. 2A). For example, a high temperature refractory ceramic (e.g., SiO₂ or Si₃N₄) may be deposited on the substrate 202, and a refractory metal (e.g., chromium or titanium or tungsten) may be deposited on the refractory ceramic.

A patterned photoresist material 204 may then be formed on the materials 212, 214 with exposed portions 215 of the second refractory or high growth temperature resistant material 214 (FIG. 2B). For example, the photoresist may be spin coated, softbaked, exposed with UV or DUV or X-ray or ebeam using photomask or direct write, optionally image reversed, developed, rinsed in DI water, and oxygen plasma ash developed to form the pattern.

The second refractory or high growth temperature resistant material 214 may then be etched (e.g., by wet etching) to leave the second material 214 only under the photoresist layer 204 (FIG. 2C). The patterned photoresist 204 may then be removed (e.g., by dissolving) leaving areas of the second refractory or high growth temperature resistant material 212 on the first refractory or high growth temperature resistant material 214 and one or more exposed portions 213 of the first refractory or high growth temperature resistant material 214 (FIG. 2D). The exposed portion(s) 213 of the first refractory or high growth temperature resistant material 212 may then be etched (e.g., by wet etching using a controlled method) to obtain a dielectric undercut beneath a lip 218 and a retrograde well structure 216. A growth layer 222 may then be deposited such that a portion of the growth layer 222 is deposited on the substrate 202 in the retrograde well 216, for example, using MBE, MOCVD or other deposition techniques (FIG. 2F).

The first and second refractory or high growth temperature resistant materials 212, 214 may then be removed leaving the selective growth layer 222 (FIG. 2G). The first refractory or high growth temperature resistant material 212 (e.g., the dielectric material) may be dissolved to remove both materials 212, 214.

Referring to FIGS. 3A-3H, a further method for fabrication of a semiconductor device is described in greater detail. Through standard techniques an epitaxial layer structure is grown, for example, via MBE (FIG. 3A). A sapphire wafer 302 is cleaned and loaded into an MBE system. A buffer layer 306 may be grown to facilitate the growth of the next epitaxial layers. A thick N layer (N+) of GaN may be grown 307 with a doping greater than 10 xlO¹⁸ approximately 1.4 microns thick. Next, an unintentionally doped N layer of GaN 308 may be grown approximately 0.4 microns thick. A p-type InGaN layer 309 may also be grown 0.14 microns thick with an approximate IxIO¹⁸ doping.

As previously described, first and second refractory or high growth temperature resistant materials 312, 314 may be used to form at least one retrograde well 316. For example, a high temperature dielectric layer (in the present example, SiO₂), may be deposited, for example, by electron beam approximately 3,000 angstroms thick. Next, a thin layer (about 800 angstroms) of high melting point metal (chromium) may be deposited by electron beam into an azide based resist (Shipley S 1808), formed using ammonia based image reversal. The photoresist may be dissolved away transferring the pattern from the photoresist coating to the chromium metal on top of the previously deposited SiO₂. The patterned chromium metal may then be used as a wet etch mask. The structure may be placed in a dilute acid solution (HF:DI water, 1:30) and by monitoring and/or controlling, the first refractory material 312 (e.g., SiO₂) may be etched such that a small lip 318 of the second refractory material 314 (e.g., chromium) overhangs the etched second refractory material 312 (e.g., SiO₂) to form the retrograde well 316 (FIG. 3B).

A growth layer 322 may then be deposited such that a portion of the growth layer 322 is deposited within the retrograde well 322 (FIG. 3C). For example, a thin layer (approximately 1,000 Angstroms) of n-type GaN with a doping of 5xlO¹⁸ may be grown into the patterned double layer structure of dielectric (SiO₂) and high melting point (chromium) metal. The first and second refractory materials 312, 314 may then be removed (FIG. 3D). For example, the patterned SiO₂ may be dissolved away in hydrofluoric acid. When the SiO₂ dissolves it takes with it the chromium metal and the areas of n-type GaN, which was deposited on top of the chromium metal. The remaining part has selective areas of the previously grown growth layer 322 (e.g., n-type GaN). A portion of one or more of the epitaxial layers 306-309 may be removed, for example, using a photoresist 330 and lift-off technique, such that other structures may be formed on one or more of the layers 306-309. For example, a thick layer of azide based photoresist (Shipley S 1827) may be spin coated and patterned on the outermost layer 309 (FIG. 3E). A dry etch (inductively couple plasma, ICP) may be used to transfer the pattern from the thick photoresist layer to the layers 308, 309 exposing the layer 307 (e.g., the highly doped N-layer) which was previously grown (FIG. 3F).

Structures, such as metal pads or contacts 324, 326, 328, may then be formed on the growth layer 309, the growth layer 307 and the growth layer 322 (FIGS. 3G-3H). To form the structure 324, for example, a layer of azide photoresist may be spun coated and patterned. Into the patterned photoresist, a thin stack of p-type GaN ohmic metals (palladium and gold) may be deposited. The photoresist may be dissolved in acetone solvent leaving the structure(s) 324, e.g., small pads of p-type ohmic metal remaining on the p-type GaN layer. To form the structures 326, 328, a layer of azide photoresist may be spun coated and patterned. Into the patterned photoresist, a thin stack of n-type GaN ohmic metals (titanium aluminum and gold) may be deposited. The photoresist may be dissolved in acetone solvent leaving the structures 326, 328, e.g., small pads of n-type ohmic metal remaining on the two different n-type GaN layers. By making an electrical connection with the metal pad 324 that contacts the p- type layer and the two pads 326, 328, which contact the two different n-type GaN layers, the structure can be tested. The common emitter electrical characteristics demonstrate that a fully functional HBT has been formed. In one aspect, the collector contact 328 is formed on the same side of the substrate as the emitter contact 326 and the base contact 324. When using a conducting substrate, the collector contact can also be formed on the backside of the substrate. FIG. 4 shows a completed all MBE grown GaN based working HBT including base contacts 324, emitter contacts 326 and collector contacts 328. FIG. 5 illustrates a common emitter characteristic for an all MBE grown HBT, such as that described above, with base current in 1E-4 steps from 0 to 4E-4. The examples herein are provided to illustrate advantages of the present invention and to further assist a person of ordinary skill in the art with preparing or using the devices of the invention and practicing the methods thereof. The examples herein are also presented in order to more fully illustrate the preferred aspects of the invention. The examples should in no way be construed as limiting the scope of the invention, as defined by the appended claims. The examples can include or incorporate any of the variations, aspects or aspects of the invention described above. The variations, aspects or aspects described above may also further each include or incorporate the variations of any or all other variations, aspects or aspects of the invention.

EXAMPLE I Selective growth of GaN on an Si substrate by MBE

Si can be used as the substrate with GaN selectively grown thereon. A 1.2 μm thick SiO₂ layer was deposited over the entire Si wafer by ebeam evaporation. Thicknesses of a material layer can range from about 10 μm to 5 μm, preferably, 5 μm to less than 1 μm and, more preferably, 2 μm to 1 μm. Preferably, an optional undercut

(described below) can be controllably formed by, for example, varying the material layer thickness. By way of example, a smaller undercut can be achieved by using a less thick SiO₂ layer. For an optional undercut, thicknesses of the SiO₂ layer can range from about 10,00OA to 100 A, preferably, 5,000 A to less than 100 A and, more preferably, 2,000 A to 100 A.

Prior to the deposition, the sample was cleaned thoroughly in a sonicator with acetone, methanol and isopropanol and rinsed by running water and then baked on hot plate for 20 minutes at 200⁰C. The cleaning and baking of the sample can provide for satisfactory adhesion of SiO₂ on the substrate. During the ebeam evaporation, oxygen was supplied at a flow rate of 2.2 seem to maintain a chamber pressure of 1 x 10^"4 Torr. As a SiO₂ source can dissociate at the high temperature due to electron beam bombast (at least to a certain degree) evaporation in an oxygen atmosphere may be used to provide for a high quality SiO₂ film. The level of oxygen can also be adjusted to actual needs. Another aspect that can be adjusted is the deposition rate. Preferably, SiO₂ films can be deposited at rates less than 10A/s, although higher rates can also be used based on certain applications. The rate can also be controlled at lA/s for the first 50nm and then increased to 5A/s for the rest of deposition to provide for satisfactory adhesion. Deposition rates can range from about 50A/s to 10A/s, preferably, 15A/s to lA/s and, more preferably, lOA/s to less than lA/s. Followed by the SiO₂ deposition, the sample was coated by an S 1808 photoresist, which is then patterned using standard photolithographic steps. Image reversal was applied during the photoresist patterning. After performing oxygen plasma etching to remove organic matter, the sample was loaded into an ebeam evaporator for patterned material deposition, for example, metal deposition. The metal can possess satisfactory adhesion characteristics or properties and be capable of withstanding the growth temperature of nitrides. The refractory metal chromium Cr was used in the present example. Thicknesses of the patterned material can range from about 10,000A to 100 A, preferably, 5,000 A to less than 1,000 A and, more preferably, 2,000 A to 500 A. The Cr film can be capable of supporting a growth layer including, but not limited to, nitrides grown thereon. In the present example, a Cr film with thickness of 800 A was deposited. After metal liftoff in acetone, the SiO₂ was carefully wet etched by BOE using the Cr as a mask material. The etching depth was monitored with a surface profiler as depicted as a function of etching time shown in FIG. 6.

The step height before etching can be about 90 nm and can range from about 1,000 nm to less than 10 nm, which may correspond to the thickness of Cr (d_Cr) and be approximately the same thickness as readings from an ebeam thickness controller. The etching rate of BOE on SiO₂ evaporated on Si substrate is about 0.8 μm/min and can range from about 10 μm/min to less than about 0.01 μm/min. The time period to etch away the approximately 1.2 μm thick SiO₂ deposit can vary, for example, it can take several minutes to etch away the SiO₂ deposit in the window region. Another 30 seconds of etching was performed to provide that all or nearly all of the SiO₂ was removed and also to optionally form an undercut for MBE liftoff. FIG. 7 illustrates a portion of an article with a retrograde well formed from the

Cr/SiO₂ structure according to the above example. Region 702 is an area covered by the Cr/SiO₂ structure and region 704 is the bare substrate, where no or almost no GVSiO₂ exists. As shown, the Cr metal was untouched or nearly untouched by BOE and SiO₂ was etched isotropically. An undercut was formed after the etching process. SiO₂ etching can be controlled to avoid an excessive undercut. The sample was then cleaned by acetone, methanol and isopropanol. After rinsing in DI water and blowing dry with nitrogen, the sample was loaded into an MBE system for depositing the growth layer. In the present example, the sample was loaded into an MBE system for a 0.3 μm GaN growth (optionally, undoped). Thicknesses of the first growth layer can range from about 10 μm to 1 μm, preferably, 3 μm to less than lμm and, more preferably, 2 μm to 0.001 μm.

FIGS. 8A and 8B show SEM images of regions 704, 702, respectively, of the sample after GaN growth. The nucleation and growth of GaN took place on the Si substrate (FIG. 8A) as well as on Cr (FIG. 8B). The GaN grown on the Si substrate was comparable with that on Cr.

Cathodoluminescence (CL) spectra were used to assess optical characteristics. FIG. 9 depicts a room temperature CL spectrum of GaN film in a different area. The CL spectrum provided a strong band-to-band emission. The intensity of the emission from the GaN on Si was about two times of that from GaN grown on Cr. A yellow luminescence peak is also depicted in the spectrum.

The Cr lip and the SiO₂ undercut together with the regrown GaN are shown in FIG. 10. The lip and the undercut appear the same as before growth, demonstrating that the structure can withstand high temperature growth during, for example, MBE,

MOCVD or other comparable deposition techniques. Although GaN covers all or nearly all of the surface, it is discontinuous at the edge between desirable areas and undesirable areas.

The sample was then dipped into HF for liftoff. It took less than 3 minutes to dissolve the SiO₂ layer, removing the Cr and GaN deposits thereon with it. The result was GaN remaining only or almost only in the desirable area. Referring to FIG. 11, the surface profiler was used to monitor (control) the step height on the boundary between regions 702 and 704 (labeled as Area A and Area B in FIG. 11). Before lift-off, the thickness of the films in region 702 (Area A) can be the summation of thickness of SiO₂, Cr and GaN, while region 704 (Area B) may be only or almost only the thickness of

GaN. Given that, region 702 (Area A) was about 1.3 μm higher than region 704 (Area B) as confirmed by a step height of 1.25 μm measured from the surface profiler. After liftoff, all the films in region 702 (Area A) were removed and GaN in region 704 (Area B) was untouched or nearly untouched. Accordingly, region 704 (Area B) was higher by about 0.3 μm than region 704 (Area B), which was also confirmed by the profiling measurement. The present example also formed at least one retrograde well comprising at least two materials (for example, SiO₂ and Cr).

SEM was also used to check the surface morphology after liftoff as depicted in FIGS. 12A and 12B. In region 704 (FIG. 12A), the GaN film was untouched or nearly untouched and had almost the same morphology as before liftoff. In region 702 (FIG. 12B), however, given that all films were removed and only the Si substrate was left, the SEM image depicts a very smooth morphology.

CL measurement was also performed on the sample after liftoff as depicted in FIG. 13. The GaN peak and yellow luminescence only show up in region B (region 70, while no peak was observed in region A (region 702), indicating GaN was removed completely or almost completely from region A (region 702).

FIG. 14 shows an image taken on a randomly chosen area of the sample by an optical microscope. As depicted, the majority of features were lifted of and the yield was higher than 90%. Preferably, the yield can range from 99%, 95% or 90%. In one aspect, yield can be greater than about 90 to 80%, 80 to 70%, 70 to 60%, 60 to 50%, 50 to 40%, 40 to 30% or 30 to 20%.

EXAMPLE II

Selective growth of an AlGaN/GaN heterojunction For an GaN HBT, Al_xGai__xN may be selectively grown as the emitter onto a

In_xGai__xN base material. In the present example, an Al_xGai__xN selective growth using MBE liftoff was preformed. The process steps are the similar or identical to those in EXAMPLE I, except that GaN grown by Gen II MBE was used as a substrate, a thinner SiO₂ layer (less than 5,000A) was deposited as the scarifying layer and AlGaN, instead of GaN, was grown. In one aspect, pure BOE can remove about a 4000A SiO₂ film (on GaN) in less than a minute and, more precisely, within several seconds. The BOE can be diluted into different concentrations by DI water to find the appropriate etching rate as can be adjusted or modified by one of ordinary skill in the art based on application and conditions. Preferably, a controllable etching can be achieved by using BOE:DI water= 1:200. For example, the ratio of BOE to DI water can be from less than about

1:10,000, preferably, less than about 1:1,000 and, more preferably, less than about 1:200. The etching rate was about lμm/min under the BOE:DI water=l:200 condition used for the present example. The etching rate can also be about 2 μm/min, preferably, about 1 μm/min and can range from about 10 μm/min to less than about 0.01 μm/min. The AlGaN growth was performed at the temperature of 800⁰C (although any suitable temperature can be used and one skill in the art will be able to adjust or modify the temperature based on application and conditions) using fluxes of 2 x 10^~6 for Ga and 1 x 10^~7 for Al. After the AlGaN growth (regrowth), the sample was dipped into HF for liftoff and then characterized by CL, SEM, AFM and an optical microscope as depicted in FIG. 15.

As shown IN the SEM image, the structure, including Cr lip and SiO₂ undercut, was kept very well after undergoing the high growth temperature (800⁰C). AlGaN grown on GaN substrate also exhibited good morphology. The CL measurement was applied on a different region of the sample before and after liftoff. Referring to FIG. 16, in the region with AlGaN grown on GaN (Area B), AlGaN emission was not affected by the liftoff and CL provided almost the same spectrum. Without wishing to be bound by theories or conventions, for an acceleration voltage of 3KV, an electron may not have enough energy to penetrate into the GaN layer such that AlGaN emission at 336 nm is the only peak observed. In one aspect, when a high acceleration voltage (10KV) was applied, the electron reached the GaN layer and the spectrum showed two peaks at 336 nm and 362 nm, which can be attributed respectively to AlGaN and GaN band-to-band emission as depicted in FIG. 16. The AlN mole fraction was determined to be about 10% based on the CL peak position. The narrow band-to-band emission peak along with no or almost no yellow luminescence provided in the spectrum demonstrates a good AlGaN quality.

In the region where AlGaN was grown on Cr (Area A), the AlGaN peak at 338nm was the only peak observed before liftoff even at 10KV of acceleration voltage as depicted in FIG. 16. Without wishing to be bound by theories or conventions, there was no GaN peak as GaN cannot be reached by an electron due to the existence of the SiO₂ and Cr. After liftoff, no AlGaN peak was detected and the GaN peak showed up at 362nm, demonstrating complete or nearly complete removal of AlGaN, SiO₂ and Cr. In one aspect, the removal of SiO₂ and Cr is accomplished by dissolving SiO₂, which can eliminate the retrograde well. FIG. 16 shows CL from Area B before lift-off in which the acceleration energy was 3KV, CL from Area B after lift-off in which the acceleration energy was 3KV, CL from Area B before lift-off in which the acceleration energy was 10KV, CL from Area A before lift-off in which the acceleration energy was 10KV and CL from Area A after lift-off in which the acceleration energy was 10KV. A photomicrography of the sample demonstrated a very high yield of lift-off as depicted in FIG. 17. For the area examined, all the patterns were lifted off properly. The complete or nearly compete proper etching, without wishing to be bound to theories or conventions, may be attributed to a thin SiO₂ layer as well as a controlled etching.

Three-dimensional images of the surfaces of samples were obtained by AFM and depicted in FIG. 18. Height profiling obtained by a surface profiler are also depicted. Before liftoff, the step height between Areas A and B was determined to be about 500nm, which corresponds to the thickness of Cr and SiO₂. The step height became 150nm after liftoff, corresponding to the thickness of AlGaN. Given that the film was grown for about 30 minutes, the growth rate can be estimated to be about 300nm per hour, which accords with the growth rate of AlGaN by our MBE system.

EXAMPLE III Modified MBE liftoff technique In the present example, after evaporating the SiO₂, the Cr was deposited onto SiO₂ without breaking vacuum of the ebeam evaporator. The Cr was then patterned by wet etching using a photoresist as mask.

The substrates used were GaN grown by Genii MBE. 500 nm SiO₂ was deposited with flowing oxygen followed by 80 nm Cr deposition without breaking vacuum of the ebeam system. HCl was used as the Cr etchant, although any other suitable etchant can be employed. Given that Cr may be the only layer in the structure that is not transparent, whether or not etching has been completed can be readily judged by the transparency of openings. After the openings become transparent, another 20 seconds of etching was given to provide for complete or nearly complete removal of the metal residual.

After the Cr etching, SiO₂ was etched by diluted BOE (1:200) without stripping the photoresist mask. The etching was performed in steps in which the etch depth is repeatedly measured and adjusted until the optionally undercut achieved to desired specifications. The etch rate can be about lμm/min. The etching rate can also be about 2 μm/min, preferably, about 1 μm/min and can range from about 10 μm/min to less than about 0.01 μm/min. The photoresist was then stripped in acetone and the sample was loaded into MBE after complete cleaning for AlGaN growth. The growth temperature was 800⁰C, although any suitable temperature can be used and adjusted by one of ordinary skill in the art. After growth, HF was used to lift off AlGaN in undesired area. In one aspect, growth temperatures range from between about 1,200⁰C to about

400⁰C. Temperatures can also be adjusted during growth, for example, from about 600⁰C to about 900⁰C. In one aspect, first and second growth layers can comprise an element, group III element, group V element, dopant or combinations thereof. For example, the first growth layer can comprise a nitridated layer, buffer layer, epitaxial layer or combinations thereof. The first and second growth layer can also comprise a group III nitride.

As depicted in images from an optical microscope in FIG. 19, liftoff went very well on both samples (regardless of whether extra etching time has been applied). The regrown AlGaN morphology can, however, differ. The sample with 20 seconds of extra etching looks smooth under microscope, while the one without this processing step has some obvious features on the surface. Without wishing to be bound by theories or conventions, these features can be attributed to the uncompleted Cr wet etching. Although the openings look transparent by eye after etching, there may still be small Cr particles left on the surface. The SiO₂ as covered by these particles can be more difficult to remove by HF. As a result, the complexity made by SiO₂ and Cr was on the surface prior to MBE growth, resulting in the nonuniformity after growth. Similar results were seen when AlGaN was regrown.

In the present example, Cr was deposited directly after the SiO₂ deposition without breaking vacuum in the ebeam system, which may result in a clean interface and satisfactory Cr adhesion on SiO₂. For example, the method of the invention provides for high yields during the fabrication of Cr/SiO₂ structure. Given that wet etching is isotropic, it may be preferable for semiconductor devices involving small features to use the method and article of EXAMPLES I or II. The methods and articles described herein provide for selective growth by MBE in which emitter regrowth is possible for HBT fabrication. In general, emitter regrowth has not been carried out by MBE. To achieve a method or article of the invention, substrates were first covered by a Cr/ SiO₂ structure fabricated by photolithography, ebeam evaporation and wet etching. After MBE growth, films on a GVSiO₂ structure can be lifted off by acid, while films on the substrate remain largely untouched.

EXAMPLES I, II and III demonstrate that MBE, MOCVD or other growth techniques can be performed according to embodiments of the invention and nitrides can be grown selectively on different substrates including, but not limited to, those comprising silicon, sapphire, gallium arsenide, magnesium oxide, zinc oxide silicon carbide or combinations thereof.

Embodiments of the invention thus provide a high temperature resistant structure formed in such a manner that there is an optional undercut in the structure. Embodiments of the invention also provide that the material in the structure can be removed without removing the desired selective growth. In one aspect, the first layer could be a high temperature metal and the top layer could be a ceramic. Both layers could be metallic. Any means of forming a retrograde structure or well that is removable after growth leaving the selected areas is contemplated. The structure could also be a single layer of either dielectric or metal or ceramic. Embodiments of the invention also provide for a retrograde (that is, a re-entrant meaning having undercut) profile to the structure. Exemplary semiconductor devices or devices of the invention fabricated by the methods or articles of the invention can include, but are not limited to, an HBT, diodes, high electron mobility transistors, other transistor structures and non-electronic mechanical structures. A selective growth method can be used for selective growth that does not require the optimization of growth conditions to obtain selectivity. The methods or articles described herein may be applicable to many varied materials and growth methods. Embodiments of the invention also provide good control of the size of the selectively grown material, which may be important for small devices. Easy post-growth processing, no photolithography and no etching of polycrystalline material are also contemplated.

Selective area growth with MBE can also be used to perform emitter regrowth for HBT fabrication. The emitter regrowth can overcome conventional problems with HBT fabrication. For example, with selective growth, it may no longer be necessary to etch to a very thin (about 1000A) layer with dry etching down to the base layer. Similarly, there may be no damage associated with dry etching of the base layer because there is no dry etching.

Accordingly, embodiments described herein allow selective growth using high temperature growth techniques. Consistent with one embodiment, a method for fabrication of a semiconductor device includes providing a substrate; forming at least one retrograde well of at least one refractory material on the substrate; depositing at least one growth layer on the substrate and within the retrograde well; and removing the at least one refractory material. Consistent with another embodiment, a method for fabrication of a semiconductor device includes providing a substrate; depositing at least a first growth layer on the substrate; forming at least one retrograde well of at least one refractory material on the first growth layer; depositing at least a second growth layer on the first growth layer and within the retrograde well; and removing the at least one refractory material material.

Consistent with a further embodiment, a method for fabrication of a semiconductor device includes providing a substrate; forming at least one retrograde well of at least one high growth temperature resistant material on the substrate, the high growth temperature resistant material being capable of withstanding temperatures of greater than about 200⁰C; depositing at least one growth layer within the retrograde well using a high growth temperature deposition at a temperature greater than about 200⁰C; and removing the at least one refractory material. Consistent with yet another embodiment, an article may be used for fabrication of a semiconductor device. The article includes a substrate; and at least one retrograde well of at least one refractory material on the substrate.

The disclosures of each and every patent, patent application and publication (for example, journals, articles and/or textbooks) cited herein are hereby incorporated herein by reference in their entirety. As used herein, "almost", "nearly" or similar terms can refer to about 90% or more of total or complete (or all). Also, as used herein and in the appended claims, singular articles such as "a", "an" and "one" are intended to refer to singular or plural. While the present invention has been described herein in conjunction with a preferred aspect, a person with ordinary skill in the art, after reading the foregoing specification, can effect changes, substitutions of equivalents and other types of alterations to the invention as set forth herein. Each aspect described above can also have included or incorporated therewith such variations or aspects as disclosed in regard to any or all of the other aspects. The present invention is also not to be limited in terms of the particular aspects described herein, which are intended as single illustrations of individual aspects of the invention. Many modifications and variations of this invention can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods within the scope of the invention, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. It is to be understood that this invention is not limited to particular methods, reagents, process conditions, materials and so forth, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only, and is not intended to be limiting. Thus, it is intended that the specification be considered as exemplary.

Claims

CLAIMSWhat is claimed is:

1. A method for fabrication of a semiconductor device, the method comprising: providing a substrate; forming at least one retrograde well of at least one refractory material on the substrate; depositing at least one growth layer on the substrate and within the retrograde well; and removing the at least one refractory material.

2. The method of claim 1, wherein the refractory material is capable of withstanding growth temperatures of greater than about 400⁰C, and wherein the at least one growth layer is deposited on the surface of the substrate using high growth temperature deposition at a temperature greater than about 400⁰C.

3. The method of claim 1, wherein the substrate comprises silicon, sapphire, gallium arsenide, magnesium oxide, zinc oxide, gallium nitride, diamond, silicon carbide or combinations thereof.

4. The method of claim 1, wherein the at least one refractory material comprises a refractory metal, a refractory ceramic or combinations thereof.

5. The method of claim 1, wherein the at least one refractory material comprises silicon dioxide, chromium or combinations thereof.

6. The method of claim 1, wherein the growth layer comprises an element, group III element, group V element, dopant or combinations thereof.

7. The method of claim 1, wherein the growth layer comprises a nitridated layer, buffer layer, epitaxial layer or combinations thereof.

8. The method of claim 1, wherein the growth layer comprises Al_xGai__xN or In_xGai_ _XN in which x is from 0 to 1 or Al_xGai__xaS or In_xGai__xaS in which x is from 0 to 1 , or silicon.

9. The method of claim 1, wherein removing the at least one refractory material comprises dissolving the at least one refractory material.

10. The method of claim 1, wherein forming the at least one retrograde well comprises: depositing at least a first refractory material on the substrate; depositing a patterned photoresist material on a surface of the at least a first refractory material; depositing at least a second refractory material on the first refractory material and on the patterned photoresist material; removing the patterned photoresist material leaving an exposed portion of the first refractory material; etching the exposed portion of the first refractory material such that the retrograde well is formed with an undercut beneath the second refractory material.

11. The method of claim 1, wherein forming the at least one retrograde well comprises: depositing at least a first and second refractory materials on the substrate; depositing a patterned photoresist material on a surface of the at least a second refractory material leaving an exposed portion of the at least a second refractory material; etching the at least a second refractory material in the exposed portion leaving an exposed portion of the at least a first refractory material; removing the patterned photoresist material; etching the exposed portion of the first refractory material such that the retrograde well is formed with an undercut beneath the second refractory material.

12. The method of claim 1, wherein the at least one refractory material includes at least a refractory ceramic on the substrate and at least a refractory metal on the refractory ceramic.

13. The method of claim 1, wherein the first growth layer is deposited by HVPE, MBE, MOCVD, MOMBE or combinations thereof.

14. A method for fabrication of a semiconductor device, the method comprising: providing a substrate; depositing at least a first growth layer on the substrate; forming at least one retrograde well of at least one refractory material on the first growth layer; depositing at least a second growth layer on the first growth layer and within the retrograde well; and removing the at least one refractory material material.

15. The method of claim 14, wherein the at least one refractory material includes at least a refractory ceramic on the substrate and at least a refractory metal on the refractory ceramic.

16. The method of claim 14, wherein the second growth layer comprises an element, group III element, group V element, dopant or combinations thereof.

17. The method of claim 14, wherein the second growth layer comprises a nitridated layer, buffer layer, epitaxial layer or combinations thereof.

18. The method of claim 14, wherein the second growth layer comprises Al_xGai__xN or In_xGaj__xN in which x is from 0 to 1 , or Al_xGaj__xaS or In_xGaj__xaS in which x is from 0 to 1, or silicon.

19. The method of claim 14, wherein the second growth layer is deposited by HVPE, MBE, MOCVD or combinations thereof.

20. A method for fabrication of a semiconductor device, the method comprising: providing a substrate; forming at least one retrograde well of at least one high growth temperature resistant material on the substrate, the high growth temperature resistant material being capable of withstanding temperatures of greater than about 200⁰C; depositing at least one growth layer within the retrograde well using a high growth temperature deposition at a temperature greater than about 200⁰C; and removing the at least one refractory material.

21. The method of claim 20 wherein the high growth temperature resistant material is capable of withstanding temperatures of greater than about 400⁰C, and wherein the at least one growth layer is deposited on the surface of the substrate using a high growth temperature deposition at a temperature greater than about 400⁰C.

22. The method of claim 20 further comprising depositing at least a first growth layer on a surface of the substrate, wherein forming the at least one retrograde well comprises forming the at least one retrograde well on a surface of the first growth layer, and wherein depositing the at least one growth layer within the retrograde well comprises depositing at least a second growth layer on the surface of the first growth layer.

23. The method of claim 20 wherein the first growth layer is deposited by HVPE, MBE, MOCVD or combinations thereof.

24. An article for fabrication of a semiconductor device, the article comprising: a substrate; and at least one retrograde well of at least one refractory material on the substrate.

25. The article of claim 24 further comprising at least one growth layer on the surface of the substrate.

26. The article of claim 24 further comprising: at least a first growth layer on a surface of the substrate, wherein the at least one retrograde well is on a surface of the first growth layer; and at least a second growth layer on the surface of the first growth layer.

27. The article of claim 24 wherein the refractory material is capable of withstanding growth temperatures of greater than about 400⁰C, and wherein the at least one growth layer is deposited on the surface of the substrate using high growth temperature deposition at a temperature greater than about 400⁰C.

28. The article of claim 24 wherein the refractory material includes a refractory ceramic deposited on the substrate and a refractory metal deposited on the refractory ceramic.