WO2009006175A3 - Test structure, test structure formation and mask reuse in semiconductor processing - Google Patents

Test structure, test structure formation and mask reuse in semiconductor processing Download PDF

Info

Publication number
WO2009006175A3
WO2009006175A3 PCT/US2008/068273 US2008068273W WO2009006175A3 WO 2009006175 A3 WO2009006175 A3 WO 2009006175A3 US 2008068273 W US2008068273 W US 2008068273W WO 2009006175 A3 WO2009006175 A3 WO 2009006175A3
Authority
WO
WIPO (PCT)
Prior art keywords
test structure
mask
different types
test structures
semiconductor processing
Prior art date
Application number
PCT/US2008/068273
Other languages
French (fr)
Other versions
WO2009006175A2 (en
Inventor
Calvin K Li
Yung-Tin Chen
En-Shing Chen
Paul Wai Kie Poon
Original Assignee
Sandisk 3D Llc
Calvin K Li
Yung-Tin Chen
En-Shing Chen
Paul Wai Kie Poon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/772,137 external-priority patent/US7998640B2/en
Priority claimed from US11/772,130 external-priority patent/US7830028B2/en
Priority claimed from US11/772,128 external-priority patent/US7932157B2/en
Application filed by Sandisk 3D Llc, Calvin K Li, Yung-Tin Chen, En-Shing Chen, Paul Wai Kie Poon filed Critical Sandisk 3D Llc
Priority to CN200880022858.0A priority Critical patent/CN101802995B/en
Publication of WO2009006175A2 publication Critical patent/WO2009006175A2/en
Publication of WO2009006175A3 publication Critical patent/WO2009006175A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/82—Auxiliary processes, e.g. cleaning or inspecting
    • G03F1/84—Inspecting
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/70858—Environment aspects, e.g. pressure of beam-path gas, temperature
    • G03F7/70866—Environment aspects, e.g. pressure of beam-path gas, temperature of mask or workpiece
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • General Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Atmospheric Sciences (AREA)
  • Toxicology (AREA)
  • Environmental & Geological Engineering (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Different types of test structures are formed during semiconductor processing with a mask that is reused to form the same pattern in multiple layers. Reference marks that allow alignment accuracy to be checked are also formed with the mask. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
PCT/US2008/068273 2007-06-30 2008-06-26 Test structure, test structure formation and mask reuse in semiconductor processing WO2009006175A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200880022858.0A CN101802995B (en) 2007-06-30 2008-06-26 Test structure, test structure formation and mask reuse in semiconductor processing

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/772,137 US7998640B2 (en) 2007-06-30 2007-06-30 Mask reuse in semiconductor processing
US11/772,130 US7830028B2 (en) 2007-06-30 2007-06-30 Semiconductor test structures
US11/772,130 2007-06-30
US11/772,128 2007-06-30
US11/772,137 2007-06-30
US11/772,128 US7932157B2 (en) 2007-06-30 2007-06-30 Test structure formation in semiconductor processing

Publications (2)

Publication Number Publication Date
WO2009006175A2 WO2009006175A2 (en) 2009-01-08
WO2009006175A3 true WO2009006175A3 (en) 2009-03-12

Family

ID=40226768

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/068273 WO2009006175A2 (en) 2007-06-30 2008-06-26 Test structure, test structure formation and mask reuse in semiconductor processing

Country Status (4)

Country Link
KR (1) KR20100038319A (en)
CN (1) CN101802995B (en)
TW (1) TW200903687A (en)
WO (1) WO2009006175A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113515007B (en) * 2020-04-10 2023-09-01 长鑫存储技术有限公司 Mask and mask quality testing method
CN112510017A (en) * 2020-12-15 2021-03-16 武汉新芯集成电路制造有限公司 Semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229419A (en) * 1989-03-02 1990-09-12 Fujitsu Ltd Manufacture of semiconductor device
KR19980016943A (en) * 1996-08-30 1998-06-05 문정환 Photomask
KR100189287B1 (en) * 1995-06-27 1999-06-01 다니구찌 이찌로오, 기타오카 다카시 Registration accuracy measurement mark
WO2006105326A1 (en) * 2005-03-31 2006-10-05 Sandisk 3D, Llc Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02229419A (en) * 1989-03-02 1990-09-12 Fujitsu Ltd Manufacture of semiconductor device
KR100189287B1 (en) * 1995-06-27 1999-06-01 다니구찌 이찌로오, 기타오카 다카시 Registration accuracy measurement mark
KR19980016943A (en) * 1996-08-30 1998-06-05 문정환 Photomask
WO2006105326A1 (en) * 2005-03-31 2006-10-05 Sandisk 3D, Llc Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure

Also Published As

Publication number Publication date
CN101802995A (en) 2010-08-11
TW200903687A (en) 2009-01-16
CN101802995B (en) 2012-02-29
KR20100038319A (en) 2010-04-14
WO2009006175A2 (en) 2009-01-08

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