WO2008155840A1 - 命令制御装置及び命令制御方法 - Google Patents

命令制御装置及び命令制御方法 Download PDF

Info

Publication number
WO2008155840A1
WO2008155840A1 PCT/JP2007/062426 JP2007062426W WO2008155840A1 WO 2008155840 A1 WO2008155840 A1 WO 2008155840A1 JP 2007062426 W JP2007062426 W JP 2007062426W WO 2008155840 A1 WO2008155840 A1 WO 2008155840A1
Authority
WO
WIPO (PCT)
Prior art keywords
instructions
decoding section
instruction control
threads
decoding
Prior art date
Application number
PCT/JP2007/062426
Other languages
English (en)
French (fr)
Inventor
Toshio Yoshida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07767264A priority Critical patent/EP2169539A4/en
Priority to CN200780053381A priority patent/CN101689109A/zh
Priority to PCT/JP2007/062426 priority patent/WO2008155840A1/ja
Priority to KR1020097025599A priority patent/KR101122180B1/ko
Priority to JP2009520194A priority patent/JP5168277B2/ja
Publication of WO2008155840A1 publication Critical patent/WO2008155840A1/ja
Priority to US12/654,262 priority patent/US20100100709A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)

Abstract

　本発明は、処理を表す命令の連なりからなるスレッドを複数実行するＳＭＴ機能を有するＣＰＵ１０において、複数のスレッドの命令が表している処理をデコードするデコード部１０９と、スレッドから命令を入手して保持し、保持した命令を、スレッド中での順序に従ってデコード部１０９に投入する命令バッファ１０４と、デコード部１０９で解読された命令の処理を実行する実行パイプライン２２０とを備え、デコード部１０９が、上記の命令のデコードに際して、その命令が実行可能な条件が整っているか否かを確認し、条件が整っていない命令以後の、命令バッファ１０４で保持されている命令についてこのデコード部１０９に対して再投入を求めることとした。
PCT/JP2007/062426 2007-06-20 2007-06-20 命令制御装置及び命令制御方法 WO2008155840A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP07767264A EP2169539A4 (en) 2007-06-20 2007-06-20 INSTRUCTION MANAGEMENT DEVICE AND METHOD
CN200780053381A CN101689109A (zh) 2007-06-20 2007-06-20 指令控制装置以及指令控制方法
PCT/JP2007/062426 WO2008155840A1 (ja) 2007-06-20 2007-06-20 命令制御装置及び命令制御方法
KR1020097025599A KR101122180B1 (ko) 2007-06-20 2007-06-20 명령 제어 장치 및 명령 제어 방법
JP2009520194A JP5168277B2 (ja) 2007-06-20 2007-06-20 命令制御装置及び制御方法
US12/654,262 US20100100709A1 (en) 2007-06-20 2009-12-15 Instruction control apparatus and instruction control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062426 WO2008155840A1 (ja) 2007-06-20 2007-06-20 命令制御装置及び命令制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,262 Continuation US20100100709A1 (en) 2007-06-20 2009-12-15 Instruction control apparatus and instruction control method

Publications (1)

Publication Number Publication Date
WO2008155840A1 true WO2008155840A1 (ja) 2008-12-24

Family

ID=40156006

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062426 WO2008155840A1 (ja) 2007-06-20 2007-06-20 命令制御装置及び命令制御方法

Country Status (6)

Country Link
US (1) US20100100709A1 (ja)
EP (1) EP2169539A4 (ja)
JP (1) JP5168277B2 (ja)
KR (1) KR101122180B1 (ja)
CN (1) CN101689109A (ja)
WO (1) WO2008155840A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10346173B2 (en) 2011-03-07 2019-07-09 Oracle International Corporation Multi-threaded instruction buffer design
US8984511B2 (en) * 2012-03-29 2015-03-17 Advanced Micro Devices, Inc. Visibility ordering in a memory model for a unified computing system
US10095518B2 (en) * 2015-11-16 2018-10-09 Arm Limited Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction
WO2019009374A1 (ja) 2017-07-07 2019-01-10 ダイキン工業株式会社 振動センサおよび圧電素子

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3548132B2 (ja) * 2000-05-04 2004-07-28 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチスレッド・プロセッサ内でのパイプライン・ステージのフラッシュ方法および装置
JP3727324B2 (ja) * 2004-04-26 2005-12-14 松下電器産業株式会社 プロセッサ及びコンパイル装置
JP3769249B2 (ja) * 2002-06-27 2006-04-19 富士通株式会社 命令処理装置および命令処理方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW353732B (en) * 1994-03-31 1999-03-01 Ibm Processing system and method of operation
TW260765B (ja) * 1994-03-31 1995-10-21 Ibm
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US6016542A (en) * 1997-12-31 2000-01-18 Intel Corporation Detecting long latency pipeline stalls for thread switching
US6889319B1 (en) * 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6609193B1 (en) * 1999-12-30 2003-08-19 Intel Corporation Method and apparatus for multi-thread pipelined instruction decoder
JP3564445B2 (ja) * 2001-09-20 2004-09-08 松下電器産業株式会社 プロセッサ、コンパイル装置及びコンパイル方法
US7613904B2 (en) * 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
US7657883B2 (en) * 2005-02-04 2010-02-02 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3548132B2 (ja) * 2000-05-04 2004-07-28 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチスレッド・プロセッサ内でのパイプライン・ステージのフラッシュ方法および装置
JP3769249B2 (ja) * 2002-06-27 2006-04-19 富士通株式会社 命令処理装置および命令処理方法
JP3727324B2 (ja) * 2004-04-26 2005-12-14 松下電器産業株式会社 プロセッサ及びコンパイル装置

Also Published As

Publication number Publication date
US20100100709A1 (en) 2010-04-22
KR20100007972A (ko) 2010-01-22
EP2169539A1 (en) 2010-03-31
JPWO2008155840A1 (ja) 2010-08-26
KR101122180B1 (ko) 2012-03-20
EP2169539A4 (en) 2010-12-29
CN101689109A (zh) 2010-03-31
JP5168277B2 (ja) 2013-03-21

Similar Documents

Publication Publication Date Title
WO2015153121A8 (en) A data processing apparatus and method for executing a stream of instructions out of order with respect to original program order
BRPI1002811A2 (pt) dispostivo e método de processamento de imagem, e, programa de computador.
SG126073A1 (en) Real-time control apparatus having a multi-thread processor
BR112018003950A2 (pt) caracterização de cargas de trabalho de gpu e gerenciamento de energia utilizando sugestão de fluxo de comando
EP2645236A3 (en) Semiconductor device
IN2012DN02567A (ja)
ATE463788T1 (de) Datenverarbeitungseinheit für anweisungen in geschachtelten schleifen
WO2006116650A3 (en) Method, system and apparatus for a transformation engine for use in the processing of structured documents
WO2011088414A3 (en) Systems and methods for per-action compiling in contact handling systems
EP1855205A4 (en) DEVICE FOR IMPLEMENTING DEBINING, AND SOFTWARE TO ENABLE THE COMPUTER TO EXECUTE THE DEBINING PROCESSING METHOD
MY169635A (en) Image coding method, image decoding method, image coding apparatus, image decoding apparatus, and image coding and decoding apparatus
ATE511674T1 (de) Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen
TWI317969B (en) Rinse processing method, developing processing apparatus, and computer readable medium encoded with a control program to be executed by a computer
WO2006122990A3 (es) Aparato, sistema y método de dispositivo de memoria para conjuntos múltiples de instrucciones de tipo especulativo
GB2565940A (en) Method and apparatus for scheduling in a non-uniform compute device
WO2012082661A3 (en) Instruction optimization
GB2480024A (en) Electronic device with overlapped boot task fetches and boot task execution
WO2006083046A3 (en) Methods and apparatus for providing a task change application programming interface
EP3416046A3 (en) Scheduling tasks
WO2008155840A1 (ja) 命令制御装置及び命令制御方法
ATE552551T1 (de) Verfahren, vorrichtung und computerprogrammprodukt zum handhaben des umschaltens zwischen threads auf einem multithread-prozessor
MX2015013682A (es) Aparato y metodo para presentar pagina de html.
EP2570933A4 (en) DATA PROCESSING DEVICE, ENTRY ASSISTING METHOD, AND PROGRAM
ATE462050T1 (de) Membranelement und verfahren zum verkleiden von flächen, insbesondere von decken oder wänden
TW201614481A (en) Flexible instruction execution in a processor pipeline

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780053381.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07767264

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009520194

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20097025599

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2007767264

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE