WO2008155834A1 - 処理装置 - Google Patents

処理装置 Download PDF

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Publication number
WO2008155834A1
WO2008155834A1 PCT/JP2007/062412 JP2007062412W WO2008155834A1 WO 2008155834 A1 WO2008155834 A1 WO 2008155834A1 JP 2007062412 W JP2007062412 W JP 2007062412W WO 2008155834 A1 WO2008155834 A1 WO 2008155834A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
buffer
command
processing device
buffer elements
Prior art date
Application number
PCT/JP2007/062412
Other languages
English (en)
French (fr)
Inventor
Megumi Yokoi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009520188A priority Critical patent/JP5177141B2/ja
Priority to EP07767250.9A priority patent/EP2192483B1/en
Priority to PCT/JP2007/062412 priority patent/WO2008155834A1/ja
Priority to EP12153535.5A priority patent/EP2453350B1/en
Publication of WO2008155834A1 publication Critical patent/WO2008155834A1/ja
Priority to US12/654,209 priority patent/US8291195B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

複数のスレッドを実行可能な処理装置において、命令を実行する実行部と、実行部に命令を供給する供給部と、供給部から供給される命令を保持するバッファ部と、バッファ部を管理する制御部とを備える。そして、バッファ部は、複数のバッファ要素の集合を含み、バッファ要素は、命令を格納するデータ部と、バッファ要素間の接続関係を定義するポインタ部とを含む。制御部は、ポインタ部で接続関係が定義された複数のバッファ要素の系列を処理装置で実行されるそれぞれのスレッドに割り当てるスレッド割り当て部を有する。
PCT/JP2007/062412 2007-06-20 2007-06-20 処理装置 WO2008155834A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009520188A JP5177141B2 (ja) 2007-06-20 2007-06-20 演算処理装置、演算処理方法
EP07767250.9A EP2192483B1 (en) 2007-06-20 2007-06-20 Processing device
PCT/JP2007/062412 WO2008155834A1 (ja) 2007-06-20 2007-06-20 処理装置
EP12153535.5A EP2453350B1 (en) 2007-06-20 2007-06-20 Processing device
US12/654,209 US8291195B2 (en) 2007-06-20 2009-12-14 Processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062412 WO2008155834A1 (ja) 2007-06-20 2007-06-20 処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,209 Continuation US8291195B2 (en) 2007-06-20 2009-12-14 Processing device

Publications (1)

Publication Number Publication Date
WO2008155834A1 true WO2008155834A1 (ja) 2008-12-24

Family

ID=40156000

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062412 WO2008155834A1 (ja) 2007-06-20 2007-06-20 処理装置

Country Status (4)

Country Link
US (1) US8291195B2 (ja)
EP (2) EP2192483B1 (ja)
JP (1) JP5177141B2 (ja)
WO (1) WO2008155834A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
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US20100318998A1 (en) * 2009-06-16 2010-12-16 Golla Robert T System and Method for Out-of-Order Resource Allocation and Deallocation in a Threaded Machine
CN102049272A (zh) * 2009-10-30 2011-05-11 住友化学株式会社 生产用于制备甲基丙烯酸的催化剂的方法和制备甲基丙烯酸的方法
JP2013182507A (ja) * 2012-03-02 2013-09-12 Nec Corp ベクトル処理装置、ベクトルロード命令実行方法、及びベクトルロード命令実行プログラム
JP2020107306A (ja) * 2018-12-27 2020-07-09 グラフコアー リミテッドＧｒａｐｈｃｏｒｅ Ｌｉｍｉｔｅｄ マルチスレッドプロセッサの命令キャッシュ

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JP5173711B2 (ja) 2008-09-30 2013-04-03 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びそのハードウェアスレッドのスケジュール方法
ES2754099T3 (es) * 2009-12-10 2020-04-15 Royal Bank Of Canada Tratamiento sincronizado de datos mediante recursos informáticos en red
JP2012257063A (ja) * 2011-06-09 2012-12-27 Nec Corp アクセス中継ユニット
US9229791B1 (en) * 2012-08-24 2016-01-05 Qlogic, Corporation System and method for high speed multiple buffer allocation
GB2521151B (en) * 2013-12-10 2021-06-02 Advanced Risc Mach Ltd Configurable thread ordering for a data processing apparatus
GB2521155B (en) 2013-12-10 2021-06-02 Advanced Risc Mach Ltd Configuring thread scheduling on a multi-threaded data processing apparatus
US9996354B2 (en) * 2015-01-09 2018-06-12 International Business Machines Corporation Instruction stream tracing of multi-threaded processors
US10430342B2 (en) * 2015-11-18 2019-10-01 Oracle International Corporation Optimizing thread selection at fetch, select, and commit stages of processor core pipeline
US20170337062A1 (en) * 2016-05-19 2017-11-23 Centipede Semi Ltd. Single-thread speculative multi-threading
US11132233B2 (en) * 2018-05-07 2021-09-28 Micron Technology, Inc. Thread priority management in a multi-threaded, self-scheduling processor
CN112540789A (zh) 2019-09-23 2021-03-23 阿里巴巴集团控股有限公司 一种指令处理装置、处理器及其处理方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09218786A (ja) 1996-02-09 1997-08-19 Fujitsu Ltd 情報処理装置
JP3804941B2 (ja) 2002-06-28 2006-08-02 富士通株式会社 命令フェッチ制御装置
JP3806029B2 (ja) 2001-12-17 2006-08-09 株式会社東芝 電力託送における発電電力制御装置
JP3845043B2 (ja) 2002-06-28 2006-11-15 富士通株式会社 命令フェッチ制御装置
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09218786A (ja) 1996-02-09 1997-08-19 Fujitsu Ltd 情報処理装置
JP3683968B2 (ja) 1996-02-09 2005-08-17 富士通株式会社 情報処理装置
JP3806029B2 (ja) 2001-12-17 2006-08-09 株式会社東芝 電力託送における発電電力制御装置
JP3804941B2 (ja) 2002-06-28 2006-08-02 富士通株式会社 命令フェッチ制御装置
JP3845043B2 (ja) 2002-06-28 2006-11-15 富士通株式会社 命令フェッチ制御装置
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Non-Patent Citations (1)

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Title
See also references of EP2192483A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100318998A1 (en) * 2009-06-16 2010-12-16 Golla Robert T System and Method for Out-of-Order Resource Allocation and Deallocation in a Threaded Machine
US9690625B2 (en) * 2009-06-16 2017-06-27 Oracle America, Inc. System and method for out-of-order resource allocation and deallocation in a threaded machine
CN102049272A (zh) * 2009-10-30 2011-05-11 住友化学株式会社 生产用于制备甲基丙烯酸的催化剂的方法和制备甲基丙烯酸的方法
JP2013182507A (ja) * 2012-03-02 2013-09-12 Nec Corp ベクトル処理装置、ベクトルロード命令実行方法、及びベクトルロード命令実行プログラム
JP2020107306A (ja) * 2018-12-27 2020-07-09 グラフコアー リミテッドＧｒａｐｈｃｏｒｅ Ｌｉｍｉｔｅｄ マルチスレッドプロセッサの命令キャッシュ
US11567768B2 (en) 2018-12-27 2023-01-31 Graphcore Limited Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times

Also Published As

Publication number Publication date
EP2453350B1 (en) 2016-04-27
JPWO2008155834A1 (ja) 2010-08-26
US8291195B2 (en) 2012-10-16
JP5177141B2 (ja) 2013-04-03
EP2192483A1 (en) 2010-06-02
US20100100708A1 (en) 2010-04-22
EP2192483A4 (en) 2011-05-04
EP2453350A3 (en) 2012-06-13
EP2453350A2 (en) 2012-05-16
EP2192483B1 (en) 2016-04-20

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