WO2008155807A1 - 情報処理装置と負荷調停制御方法 - Google Patents

情報処理装置と負荷調停制御方法 Download PDF

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Publication number
WO2008155807A1
WO2008155807A1 PCT/JP2007/000665 JP2007000665W WO2008155807A1 WO 2008155807 A1 WO2008155807 A1 WO 2008155807A1 JP 2007000665 W JP2007000665 W JP 2007000665W WO 2008155807 A1 WO2008155807 A1 WO 2008155807A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
threads
information processor
section
control section
Prior art date
Application number
PCT/JP2007/000665
Other languages
English (en)
French (fr)
Inventor
Takashi Suzuki
Toshio Yoshida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000665 priority Critical patent/WO2008155807A1/ja
Priority to EP07790191A priority patent/EP2159692A4/en
Priority to JP2009520148A priority patent/JP5088371B2/ja
Publication of WO2008155807A1 publication Critical patent/WO2008155807A1/ja
Priority to US12/635,801 priority patent/US8561079B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

　スレッド間の負荷バランスを定性的に判断し、スレッド間の性能負荷バランスを調停する同時マルチスレッド方式の情報処理装置と制御方法を提供する。 　メモリから命令を取得し、命令に基づいた演算を実行する演算部に、命令を投入する制御を、スレッド間で共有する命令投入制御部と、命令をデコードした情報を保持するスレッドごとに設けられるコミットスタックエントリと、命令投入制御部から投入された命令の順番に従い演算部により演算された演算結果に応じて、メモリと汎用レジスタの更新をする命令完了順序制御部と、コミットスタックエントリに登録された情報を検知し、検知結果に基づいて命令投入制御部を制御する性能負荷バランス解析部と、を具備する同時マルチスレッディング方式の情報処理装置とスレッド間性能負荷調停制御方法である。
PCT/JP2007/000665 2007-06-20 2007-06-20 情報処理装置と負荷調停制御方法 WO2008155807A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/000665 WO2008155807A1 (ja) 2007-06-20 2007-06-20 情報処理装置と負荷調停制御方法
EP07790191A EP2159692A4 (en) 2007-06-20 2007-06-20 Information processor and load cancellation control method
JP2009520148A JP5088371B2 (ja) 2007-06-20 2007-06-20 情報処理装置と負荷調停制御方法
US12/635,801 US8561079B2 (en) 2007-06-20 2009-12-11 Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000665 WO2008155807A1 (ja) 2007-06-20 2007-06-20 情報処理装置と負荷調停制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/635,801 Continuation US8561079B2 (en) 2007-06-20 2009-12-11 Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit

Publications (1)

Publication Number Publication Date
WO2008155807A1 true WO2008155807A1 (ja) 2008-12-24

Family

ID=40155972

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000665 WO2008155807A1 (ja) 2007-06-20 2007-06-20 情報処理装置と負荷調停制御方法

Country Status (4)

Country Link
US (1) US8561079B2 (ja)
EP (1) EP2159692A4 (ja)
JP (1) JP5088371B2 (ja)
WO (1) WO2008155807A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8042115B2 (en) * 2007-08-16 2011-10-18 International Business Machines Corporation Method and system for balancing component load in an input/output stack of an operating system
US20120017214A1 (en) * 2010-07-16 2012-01-19 Qualcomm Incorporated System and method to allocate portions of a shared stack
US10318356B2 (en) * 2016-03-31 2019-06-11 International Business Machines Corporation Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
CN107357222A (zh) * 2017-09-01 2017-11-17 娄底市简思工控有限公司 嵌入式控制装置及系统

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US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US20040215945A1 (en) 2003-04-24 2004-10-28 International Business Machines Corporation Method for changing a thread priority in a simultaneous multithread processor
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

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JP2882475B2 (ja) * 1996-07-12 1999-04-12 日本電気株式会社 スレッド実行方法
JP3469469B2 (ja) * 1998-07-07 2003-11-25 富士通株式会社 情報処理装置
US6185672B1 (en) * 1999-02-19 2001-02-06 Advanced Micro Devices, Inc. Method and apparatus for instruction queue compression
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US7000233B2 (en) * 2003-04-21 2006-02-14 International Business Machines Corporation Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread
US7469407B2 (en) * 2003-04-24 2008-12-23 International Business Machines Corporation Method for resource balancing using dispatch flush in a simultaneous multithread processor
US20040216103A1 (en) * 2003-04-24 2004-10-28 International Business Machines Corporation Mechanism for detecting and handling a starvation of a thread in a multithreading processor environment
JP2005284749A (ja) * 2004-03-30 2005-10-13 Kyushu Univ 並列処理コンピュータ
JP4327008B2 (ja) * 2004-04-21 2009-09-09 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP4956891B2 (ja) * 2004-07-26 2012-06-20 富士通株式会社 演算処理装置，情報処理装置および演算処理装置の制御方法
US20060212853A1 (en) * 2005-03-18 2006-09-21 Marvell World Trade Ltd. Real-time control apparatus having a multi-thread processor
US8230423B2 (en) * 2005-04-07 2012-07-24 International Business Machines Corporation Multithreaded processor architecture with operational latency hiding
CN101529377B (zh) * 2006-10-27 2016-09-07 英特尔公司 处理器中多线程之间通信的方法、装置和系统
US8521993B2 (en) * 2007-04-09 2013-08-27 Intel Corporation Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
US7707390B2 (en) * 2007-04-25 2010-04-27 Arm Limited Instruction issue control within a multi-threaded in-order superscalar processor
US8219996B1 (en) * 2007-05-09 2012-07-10 Hewlett-Packard Development Company, L.P. Computer processor with fairness monitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
JP3714598B2 (ja) * 1997-10-23 2005-11-09 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチスレッド式プロセッサでのスレッド優先順位の変更
US20040215945A1 (en) 2003-04-24 2004-10-28 International Business Machines Corporation Method for changing a thread priority in a simultaneous multithread processor
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2159692A4 *

Also Published As

Publication number Publication date
US8561079B2 (en) 2013-10-15
US20100095304A1 (en) 2010-04-15
EP2159692A4 (en) 2010-09-15
EP2159692A1 (en) 2010-03-03
JPWO2008155807A1 (ja) 2010-08-26
JP5088371B2 (ja) 2012-12-05

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