WO2008155610A2 - Procédés et appareil de prédistorsion indépendante du temps de propagation d'un amplificateur de puissance - Google Patents

Procédés et appareil de prédistorsion indépendante du temps de propagation d'un amplificateur de puissance Download PDF

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Publication number
WO2008155610A2
WO2008155610A2 PCT/IB2008/000996 IB2008000996W WO2008155610A2 WO 2008155610 A2 WO2008155610 A2 WO 2008155610A2 IB 2008000996 W IB2008000996 W IB 2008000996W WO 2008155610 A2 WO2008155610 A2 WO 2008155610A2
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WO
WIPO (PCT)
Prior art keywords
power amplifier
lookup table
time
signal
predistortion
Prior art date
Application number
PCT/IB2008/000996
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English (en)
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WO2008155610A3 (fr
Inventor
Dali Yang
Jia Yang
Original Assignee
Dali Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dali Systems Co., Ltd. filed Critical Dali Systems Co., Ltd.
Priority to CN200880003130.3A priority Critical patent/CN101606315B/zh
Priority to EP08806836A priority patent/EP2118999A4/fr
Publication of WO2008155610A2 publication Critical patent/WO2008155610A2/fr
Publication of WO2008155610A3 publication Critical patent/WO2008155610A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3294—Acting on the real and imaginary components of the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/57—Separate feedback of real and complex signals being present
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3224—Predistortion being done for compensating memory effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3233—Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion

Definitions

  • the present invention relates systems and methods for using predistortion to linearize the output of a power amplifier (PA), such as those used in wireless transmission systems. More particularly, the present invention uses an adaptive time-delay adjusting methodology to correct the PA's nonlinearity. More particularly, the invention relates to systems and methods which use a time-delay invariant predistortion architecture to linearize the output of a power amplifier (PA) in wireless transmission systems.
  • PA power amplifier
  • the system typically contains multiple signal transmission paths, such as a reference path and a feedback path.
  • a predistortion linearization system when a signal passes through different signal transmission paths, such as a reference path and a feedback path, the occurrence of a timing difference caused by the distinct signal paths is inevitable.
  • This difference usually referred to as a time delay, presents significant problems with respect to the accuracy of the predistortion correction. These problems are made worse by the fact that the time delay can vary with environmental conditions including temperature, system conditions including signal power level, system aging, and so on.
  • the first is to make a special time-delay cable by measuring and calculating the difference of the same signal passing through different transmission paths so as to compensate the time-delay effect, such as the processing in analog feed-forward predistortion systems.
  • This approach suffers the limitation that the time-delay cable imposes a fixed time-delay that cannot be adjusted despite changes in the signal and environment which naturally occur during the operation of practical systems.
  • the second is to use a special digital signal processing (DSP) algorithm and circuitry to calculate and adjust adaptively the time difference of the same signal passing through different transmission paths, and then use the resulting time-delay information to correct the non-linearity of power amplifier.
  • DSP digital signal processing
  • This approach is usually implemented in a digital feedback approach and a wireless environment.
  • an extra circuit, typically a latch, and an associated algorithm are needed, and the accuracy of the time-delay calculation is also related to the convergence rate of the algorithm.
  • Next-generation wireless communication systems will demand improved transmitted signal quality and improved overall RF transmitter system performance for a variety of broadband and multimedia services. These demands upon advanced RF transmitter systems will be satisfied, at least in part, by power amplifiers with higher power efficiency and higher spectrum efficiency than is currently available.
  • the present invention evaluates the time-delay parameter as a variable that is estimated and calculated by a special algorithm and circuitry.
  • the present invention uses, in one implementation, one combined predistortion and time-delay lookup table structure to provide correction factors for both the PA's non-linear distortion and the system's time-delay.
  • This design can be conveniently implemented by an elegantly simple circuit structure and can be used for almost all wireless radio frequency (RF) transmission systems to improve both power efficiency and spectrum efficiency. Examples of some applicable RF transmission systems include wireless base-stations, access points, mobile handsets including but not limited to cellular and GPRS protocols, mobile wireless terminals, portable wireless devices, and other wireless communication systems such as microwave and satellite communications.
  • RF radio frequency
  • the new time-delay invariant method presented herein uses a combination of (i) an adaptive time-delay adjusting methodology to process the PA's nonlineahty, and, at the same time, (ii) time-delay compensation without the additional circuitry and/or an algorithm tailored for the special time-delay adjustment.
  • This novel algorithm-based methodology can be implemented by a predistortion processing unit that includes a time-delay addressing lookup table that can store and memorize the PA's non-linearity, time-delay information and other interference in the system such as noise.
  • Figure 1 illustrates a system and apparatus in accordance with the present invention.
  • Figure 2 illustrates in simplified form one implementation for serial addressing of the lookup table as well as the entry of the accumulated history into the lookup table.
  • Figure 3 illustrates in simplified form an implementation of parallel addressing of the lookup table, which is otherwise as shown in Figure 2.
  • the entries for the lookup table are developed in accordance with the techniques described in pending U.S. patent application S. N. 1 1/262,079, filed 10/27/05, and U.S. Patent Application S.N. S.N. 1 1/799,239, filed 4/30/2007, both of which are incorporated herein by reference and attached as Appendices A and B. It will be appreciated by those skilled in the art that the range of errors which occur in a real-world system are bounded; that is, there is a range which has a minimum value and a maximum value, and in all but rare circumstances the correction factor applicable at the time of any given sample will fall within that range.
  • the correction factor which is appropriate for each sampling of the input signal will be one of the values already in the lookup table.
  • the correction factors of the present invention do not vary with time; that is, they are time-invariant.
  • lookup table can vary significantly with the particular implementation, and could for some systems be as small as sixteen entries, for more complex implementations such as those appropriate for wireless RF transmission systems the table will have on the order of 2 12 entries or more, and may have significantly more entries depending on the permissible power consumption, cost, and related system factors. For certain implementations, a table size between 2 12 and 2 14 entries has been found to be acceptable.
  • the lookup table of the predistortion processing unit, or predistorter is addressed by a set of time-related addresses that can be structured by a shift register, although parallel addressing may be implemented in some schemes, as discussed in greater detail hereinafter.
  • the shift register technique will be used for illustration.
  • the addressing of the lookup table is based upon a stored-compensation or memory- compensation principle that stores information at different time by a vector form and maps the input vector into one of the entries in the lookup table.
  • the set of addressed entries in the lookup table will result in an output signal that is a mapping function of the corresponding input vector.
  • the output signal of the lookup table is actually related to the different time information, including the current signal and previous N transmitted signals, where N > 1 and N is an integer.
  • the signal stored in each entry of the lookup table can be considered as a combination of all past transmitted signals rather than the sole response of the current input signal.
  • the bit length of the address vector in the lookup table determines the duration of time-delay signal to be covered.
  • the predistortion algorithm utilizes a function to incorporate the time-delay signal combination.
  • the lookup table stores the non-linear information derived from the PA together with a time-delay factor that is caused by the different signal transmission paths.
  • the lookup table provides a correction factor which includes both the appropriate predistortion correction and the appropriate time delay compensation.
  • the output of the lookup table is then combined with the original input signal to provide an input to the PA that results in a linearized output, with substantially no time delay error.
  • the non-linear characteristics of the PA that are to be corrected by the lookup table are not limited by the time-based data.
  • the time-independent feature of the lookup table's adaptive processing is one benefit of at least some implementations of the addressing arrangement of the lookup table.
  • the addressing of the lookup table is implemented by a set of ⁇ /-bit vector data that comprises the current input signal as well as the previous N input signals. Therefore, the address of the lookup table is a combination of series of input sequences with the length of N. The longer the address of the lookup table (and therefore the larger the lookup table), the wider the range of time-delay information that the system can accommodate, i.e.
  • the lookup table of the predistortion processor is based upon the stored-compensation principle that maps a set of input vectors to a real signal output. Since the address of lookup table contains the input information stored from different time, each output signal generated by the lookup table is closely related to the transmitted multi-signals combination. Therefore, based upon the arrangement of the lookup table, the table update entries are also closely related to the combination information of input signals stored from different time points.
  • the illustrated embodiment includes an Analog Multiplier 1 1 which receives a modulated RF signal v RF from the RF modulator portion 10 of the base station, and also receives a predistortion correction signal v p from a lookup table and related components which can be generally described as a predistortion processor, discussed in greater detail below.
  • the predistortion processor can be thought of as all of the components between the ADC's 21 and 25 and the DAC 30.
  • the output of the analog multiplier 1 1 is provided as the input V m to the power amplifier (PA) 12, which in turn transmits an output signal V 0 to an Antenna 13.
  • the RF modulator 10 is typically although not necessarily a quadrature modulator or an orthogonal modulator. It will be appreciated that multiplier 1 1 can be implemented as multiple multipliers, each associated with one or more quadrature signals.
  • An input down-converter circuit 20 receives an idealized reference signal V RF from modulator in base station, and is biased by a local oscillator 40, such that it provides an output Vd to an analog-to-digital converter 21 .
  • the ADC 21 converts the signal V d to digital form (as I and Q signals), whereupon it is provided as one input pair to the Digital Predistortion Processor, and more specifically to variables 22I and 22Q, respectively.
  • a feedback down-converter circuit 26 also biased by a local oscillator 40, receives a raw feedback signal V 0 (t) from the output of the PA, and provides a feedback signal V f to an feedback ADC 25.
  • the digital output of the ADC 25 then provides a second input, i.e. feedback signal, to the Digital Predistortion Processor, and more particularly to variables 24I and 24Q.
  • the Digital Predistortion discussed in greater detail below, provides a digital output signal Vr to a DAC 30, which converts the digital signal to an analog form, where it is combined with the modulated RF signal in the multiplier 1 1 .
  • address data formers 32I-32Q receive inputs from the ADC 21 1/Q, and are designed to generate the required signal format for a lookup table 33I/Q.
  • the data formers 32I/Q address memory units within the lookup tables 331/Q, where the lookup table provides separate I and Q outputs to an adder 31.
  • the lookup table 33 can be implemented as one or more lookup tables.
  • the address provided by the address formers 32I-32Q can be considered a lookup-table key or address.
  • the predistortion controller lookup tables 33I-33Q are designed memory units to store the predistortion signal for high power amplifier linearization.
  • the predistortion signals in the tables are based on the error generated by a comparison of the ideal signal v d and the feedback signal V f and the presented adaptive algorithm.
  • the data stored in the tables 331-Q can be updated by adaptive iteration as described hereinafter, and forms digitally indexed data reflecting the nonlinear characteristics of the power amplifier.
  • the Digital Predistortion Processor calculates the error in the amplitude and phase components of the output signal V 0 (t) caused by the non-linear transmission characteristics of the high power amplifier 12.
  • the predistortion processor Based on the error information obtained by the foregoing comparison, the predistortion processor, based on the lookup table algorithm disclosed in U.S. Patent No. 6,985,704, calculates and generates adaptively a compensation signal that is of inverse characteristics with the transform function of the PA 12 to pre-distort the AM-AM and AM-PM distortion caused by the PA 12.
  • the outputs v p of the predistortion lookup table 33I-33Q are fed to multiplier 1 1 , after an adder 31 and a digit-to-analog converter 30, to modify the modulated RF signal from modulator 10.
  • the output of the multiplier is the required predistortion signal v ⁇ n (k) that is of an inverse non-linearity with that of the power amplifier 12 to yield a pre-compensation to the input of high power amplifier.
  • look-up tables 33 permits a memory function to be introduced into at least some embodiments of the present invention.
  • the lookup table of the predistortion controller is based on a stored compensation principle that maps a set of input data into a digital output, and updated adaptively. Based on the stored function, each output signal of lookup table is actually related to both the current and the previously transmitted signal, and therefore has a memory function which compensate not only for the non-linearity of the PA, but also avoids the need for a special time-delay compensation circuit such as typically used in the prior art.
  • the signal v p is multiplied with the modulated RF signal
  • the input signal of power amplifier is a complex gain signal that can be controllable in the amplitude/envelope and be adjustable in phase.
  • the relation of the input and output can be described as the following complex gain expression
  • v p is the output of predistortion processor generated by a mapping
  • mapping function F of lookup table is unknown and is difficult to express mathematically.
  • F may be determined adaptively by updating the entries in the lookup table in accordance withthe adaptive algorithm to realize all possible mapping that corresponds to the relations with
  • the lookup table therefore maps each set of ⁇ /-bit input address vector V to a real output v p .
  • V(k) ⁇ d ⁇ (k), d 2 (k) ,..., d N (k)) T (2)
  • the address of the lookup table 200 is formed by a serial shift register 205 that addresses each corresponding entry of the lookup table during the predistortion processes. Due to the addressed information being related to the current and previous N transmitted signal, the output signal 210 of the lookup table can be considered as a function of the last N transmitted data, and therefore incorporates a time delay correction element.
  • the lookup table is adaptively updated by combining the adaptive error 215 and a table update 220 in combiner 225.
  • the arrangement of the lookup table configured as a predistortion processor, can systematically utilize the combined correction signal for the processing of both non-linearity correction of PA and time-delay compensation, even if time-delay effects are present when the same signal passes through different transmission paths.
  • the memory table is addressed by its address register.
  • the bit-number length of shift register determines the size of lookup table and therefore the covered time-delay range, i.e., the maximum limit of time-delay effects.
  • Each set of data stored in a lookup table entry has a unique address index. This address index of a data set corresponds to the data set's sampled time point of the input signal. The address indices are then utilized as time stamps for time calibration purpose of PA's non-linear error correction calculations.
  • the predistortion algorithm selects only one set of data from a specific addressed entry as the output of the lookup table for further PA's non-linearity error correction processing. If the selected output signal is only related to the current- time transmitted signal without any relation with other transmitted signal, then the time-delay, caused by the current transmitted signal passing through different transmission paths, must be considered during the predistortion processing in order to provide an accurate signal matching between the reference and feedback signal.
  • the time-delay range to be covered by lookup table is related to the bit number of the address register.
  • the set of input address vectors, A can be expressed as
  • V(k) is an input address vector at time k, which records M possible predistorted information to PA nonlineahty and each information recoded the current transmitted signal and the time-delay signal components.
  • the combined time-delay lookup table structure involves simple logic operations and signal processing to capture the time-delay of signal passing through different transmission paths. More specifically, due to the time-delay invariant characteristic, this predistortion architecture can process and correct PA non- linearities in a wider dynamic range and without the needs of additional circuitries and algorithms.
  • a parallel addressing scheme can be used, such as that shown in Figure 3, which is essentially identical to Figure 2 except for the use of a parallel input 300 to the lookup table. If the sampled data points are taken close together (i.e., a comparatively fast sampling rate) so that the correction factors for sample t and sample t+1 effectively become identical, then we can use the parallel addressing approach to address the lookup table. In some embodiments, if the size of the lookup table is sufficiently large, and computing power and other device issues are satisfied, then the parallel addressing approach can offer better performance over a serial addressing approach in environments which use a very fast sampling rate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

Un mode de réalisation de l'invention est une approche par prédistorsion indépendante du temps de propagation pour linéariser des amplificateurs de puissance dans des émetteurs RF sans fil. L'architecture de prédistorsion est basée sur le principe de compensation stockée ou de compensation par mémoire par l'utilisation d'un procédé d'adressage par temps de propagation combiné, et en conséquence, l'architecture a une fonction de compensation de temps de propagation intrinsèque, à auto-étalonnage. L'architecture de prédistorsion utilise seulement une table de consultation pour effectuer à la fois la correction de réponses non linéaires d'un amplificateur de puissance et la compensation de n'importe quels effets de temps de propagation présentés dans le même système. En raison de la caractéristique indépendante du temps de propagation, la conception de prédistorsion a un avantage de traitement de plus large gamme dynamique pour des signaux RF sans fil, et peut donc être mise en œuvre dans des systèmes sans fil multi-porteuses et multi-canaux.
PCT/IB2008/000996 2007-01-26 2008-01-28 Procédés et appareil de prédistorsion indépendante du temps de propagation d'un amplificateur de puissance WO2008155610A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200880003130.3A CN101606315B (zh) 2007-01-26 2008-01-28 功率放大器时间延迟不变的预失真方法和装置
EP08806836A EP2118999A4 (fr) 2007-01-26 2008-01-28 Procédés et appareil de prédistorsion indépendante du temps de propagation d'un amplificateur de puissance

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US89774607P 2007-01-26 2007-01-26
US60/897,746 2007-01-26
US89831207P 2007-01-29 2007-01-29
US60/898,312 2007-01-29

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WO2008155610A2 true WO2008155610A2 (fr) 2008-12-24
WO2008155610A3 WO2008155610A3 (fr) 2009-04-30

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CN (2) CN103997301B (fr)
WO (1) WO2008155610A2 (fr)

Cited By (4)

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US11129076B2 (en) 2006-12-26 2021-09-21 Dali Wireless, Inc. Method and system for baseband predistortion linearization in multi-channel wideband communication systems
US11159129B2 (en) 2002-05-01 2021-10-26 Dali Wireless, Inc. Power amplifier time-delay invariant predistortion methods and apparatus
US11418155B2 (en) 2002-05-01 2022-08-16 Dali Wireless, Inc. Digital hybrid mode power amplifier system
US20220295487A1 (en) 2010-09-14 2022-09-15 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods

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US6985704B2 (en) * 2002-05-01 2006-01-10 Dali Yang System and method for digital memorized predistortion for wireless communication
US8064850B2 (en) * 2002-05-01 2011-11-22 Dali Systems Co., Ltd. High efficiency linearization power amplifier for wireless communication
US7109792B2 (en) * 2003-09-17 2006-09-19 Andrew Corporation Table-based pre-distortion for amplifier systems
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Cited By (6)

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Publication number Priority date Publication date Assignee Title
US11159129B2 (en) 2002-05-01 2021-10-26 Dali Wireless, Inc. Power amplifier time-delay invariant predistortion methods and apparatus
US11418155B2 (en) 2002-05-01 2022-08-16 Dali Wireless, Inc. Digital hybrid mode power amplifier system
US11129076B2 (en) 2006-12-26 2021-09-21 Dali Wireless, Inc. Method and system for baseband predistortion linearization in multi-channel wideband communication systems
US11818642B2 (en) 2006-12-26 2023-11-14 Dali Wireless, Inc. Distributed antenna system
US20220295487A1 (en) 2010-09-14 2022-09-15 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US11805504B2 (en) 2010-09-14 2023-10-31 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods

Also Published As

Publication number Publication date
WO2008155610A3 (fr) 2009-04-30
EP2118999A2 (fr) 2009-11-18
CN103997301A (zh) 2014-08-20
CN101606315B (zh) 2014-07-02
CN101606315A (zh) 2009-12-16
CN103997301B (zh) 2018-09-28
EP2118999A4 (fr) 2010-01-27

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