WO2008155418A1 - Étalement/désétalement multiple de signaux à spectre étalé, par séquences d'étalement multiples - Google Patents

Étalement/désétalement multiple de signaux à spectre étalé, par séquences d'étalement multiples Download PDF

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Publication number
WO2008155418A1
WO2008155418A1 PCT/EP2008/057897 EP2008057897W WO2008155418A1 WO 2008155418 A1 WO2008155418 A1 WO 2008155418A1 EP 2008057897 W EP2008057897 W EP 2008057897W WO 2008155418 A1 WO2008155418 A1 WO 2008155418A1
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Prior art keywords
correlator
signal
spreading
despreading
sequence
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PCT/EP2008/057897
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German (de)
English (en)
Inventor
Martin Opitz
Thomas Reisinger
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Continental Automotive Gmbh
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Publication of WO2008155418A1 publication Critical patent/WO2008155418A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H04B1/7093—Matched filter type

Definitions

  • the invention relates to a method for wireless communication with at least one peripheral unit and in particular a spread spectrum method with multiple spreading / despreading of the data transmission signal by means of multiple spreading sequences.
  • a radio link in license-free frequency bands is used for the transmission from and to the motor vehicle.
  • RKE systems remote keyless entry systems
  • these are so-called “remote keyless entry” systems (RKE systems, for example), such as those used for centralized radio interlocking, for example
  • RKE systems remote keyless entry
  • centralized radio interlocking for example
  • mitteis integrated in a Fahrzeu ⁇ knowl, battery-powered radio control which is also used in addition to the locking and unlocking of the doors and the boot also the theft protection and the immobilizer accordingly activated or
  • Other functions such as the convenient opening and closing of windows, sunroofs, sliding doors or tailgates, can also be integrated in the car.
  • Other comfort function and safety feature is the activation of the vehicle's apron lighting One cares in the.
  • Key Integrated so-called emergency button that triggers an audible and visual alarm on the vehicle when pressed.
  • RKE systems work with unidirectional or bidirectional communication in the wide area shared ISM frequencies.
  • Other features include secure data transmission with optionally increased security, a challenge-response authentication method (bidirectional) and low energy consumption.
  • bidirectional challenge-response authentication method
  • RKS systems Personalization of the functions of a RKE system to selected persons.
  • the range of such RKS systems is usually up to 100 m.
  • PASE PAssive Start and Entry
  • PASE PAssive Start and Entry
  • the driver only has to carry an identification transmitter (ID) with him and gets access to the vehicle by simply touching the door handle.
  • ID identification transmitter
  • the engine can be started by pressing a button.
  • the PASE system locks the vehicle either automatically or at the push of a button.
  • the driver's identification card replaces conventional mechanical or radio controlled keys to provide maximum comfort and ease of use for the driver.
  • a multi-channel bidirectional data transmission is used, which also takes place wirelessly and encrypted, for example in the field of shared ISM frequencies worldwide.
  • Radio links with longer ranges than those described in the RKE and PASE systems refer to the motor vehicle from a long distance retrievable status information, such as the current closed state, the current interior temperature and results of technical system checks (technology check). A transmission of alarm messages is desirable over a longer distance.
  • long-range applications All functions that require wireless data transmission over long distances are also summarized under the term "long-range applications.”
  • One goal for long-range applications is to make data transmission or communication bidirectional over distances of at least 600 m
  • Spread spectrum arrangements are characterized by a transmission bandwidth which is substantially larger than the bandwidth of the information to be transmitted.
  • This code-based spreading of a data signal before its transmission is achieved by multiplying the data signal by a fixed bit sequence (pseudorandom number) of higher bit rate, the so-called chip rate.
  • a spread in the modulated high-frequency spectrum is achieved while maintaining the net data rate.
  • the demodulation of such a spread spectrum signal essentially takes place by correlation of the received signal with a copy of the so-called spread signal used in the transmitter for spreading.
  • a fundamental component of a spread spectrum arrangement are pseudo-random sequences whose autocorrelation function is in
  • a data signal to be transmitted d (k) of the data rate D (kbit / sec) with a so-called
  • k denotes the bit clock and 1 the chip clock of an arrangement for band spreading.
  • a high-frequency carrier signal is arbitrarily modulated (AM, FM, PSK, etc.). This multiplication of the original data rate to the chip data rate results in a broadening or spreading of the frequency range required for radio transmission.
  • the required length m of the spreading sequence results from one or more of these requirements.
  • Previous arrangements use a single spreading sequence to multiply the data signal once. This results in the available spreading gain, the spectrum spread, etc. In order to achieve the largest possible spreading gain, the longest possible spreading sequences s (1) must be used. However, this disadvantageously results in an increased effort for despreading the transmitted data signal on the receiver side of such an arrangement. This increased complexity is evident, for example, in the number of elements required for a correlator for despreading the data signal, such as delay elements, logic operation elements and storage registers for the spread sequences.
  • the object of the present invention is to specify a spread spectrum method for wireless communication in which the most varied requirements are largely met.
  • the object is achieved in particular by a spread spectrum method for wireless bidirectional communication with multiple spreading / despreading of the data signal with the aid of shortened spreading sequence lengths and with at least one corresponding correlator on the respective receiver side of the bidirectional radio transmission arrangement.
  • FIG. 1 is a block diagram showing a general structure of a despreading correlator of the prior art
  • Figure 2 is a flowchart showing the process of spreading and despreading a data signal according to the prior art
  • FIG. 3 shows a block diagram of a structure of a correlator required for despreading in the case of binary input signals and despreading in baseband
  • FIG. 4 is a block diagram of embodiments (a), (b) and (c) for generating the baseband modulation signal
  • Figure 5 is a block diagram showing an embodiment of the structure of a despreading correlator in the case of a multiple spread input signal
  • FIG. 6 is a flowchart showing a sequence of despreading by the correlator according to FIG. 5;
  • FIG. 7 is a flowchart showing three exemplary embodiments of the invention.
  • Figure 8 is a block diagram of an alternative embodiment of the structure of a despreading correlator in the case of a final logical value decision
  • FIG. 9 shows in a table a general representation of the calculation rule for the number of elements required in a correlator
  • FIG. 10 shows in a block diagram an exemplary embodiment of the structure of the correlator used for despreading according to FIG. 8 for the case of a successive logic value decision;
  • FIG. 11 is a table showing the calculation rules for the number of elements required in a successive logic value decision correlator
  • FIG. 12 shows in a table the calculation specifications for the number of times in a correlator with successive logic value decision or final the logic value decision and double spreading or despreading required elements
  • FIG. 13 shows in a table the number of elements required in a correlator with successive logic value decision or concluding logic value decision and 225-fold spreading or despreading
  • FIG. 14 shows a diagram of the autocorrelation function of a data signal which has once been spread or despread with a ZigBee spreading sequence
  • FIG. 15 shows a diagram of the autocorrelation function of a data signal which is twice spread or despread using a ZigBee spreading sequence.
  • 15 bit or 15 chip spreading sequences have already been implemented in various other embodiments by ASICS.
  • the exemplary embodiments shown below offer approximately 15 times the approximate cost of despreading in an ASIC Performance in terms of spreading profit.
  • the 15-bit ZigBee spreading sequence is used twice. This will also ensure compatibility with future ZigBee applications.
  • ZigBee describes a new industry standard for the networking of devices and sensors or for wireless communication and control in almost all areas (see IEEE Working Group 802.15.4).
  • ZigBee Typical areas of application for ZigBee include home networking, automation and safety technology in facility management and machine-to-machine communication (M2M). Due to the technical functionality and the comparatively low costs, ZigBee can be used to build completely wireless, infrastructure-independent device and sensor networks.
  • M2M machine-to-machine communication
  • ZigBee Data rates of 20, 40 and 250 kBit / s in the frequency ranges 868 MHz, 915 MHz and 2.4 GHz, respectively.
  • the connection to ZigBee is instantaneous, while it takes up to 3 seconds for Bluetooth applications.
  • the number of components in a ZigBee network with more than 250 is significantly less limited than with Bluetooth (7 components).
  • the ZigBee standard is particularly suitable against the background of low energy consumption compared to WLAN or Bluetooth, which is particularly advantageous for battery-powered devices, for example.
  • a data signal d (k) of the data rate D (kbit / sec) multiplied by a so-called spreading sequence s (1) of a length m (s (l ... m)).
  • k denotes the bit clock and 1 the chip clock of an arrangement for band spreading.
  • a corresponding despreading of the received data signal is carried out based on this one spreading sequence s (l... M).
  • the received signal r (l) digitized with the resolution bit width b is correlated with the spreading sequence s (l... M) in a receiving-side correlator.
  • correlation sums in the chip clock cor (1) result.
  • the signal cor (k) is obtained from this by synchronized down-clocking, and the despread signal d (k) is obtained by a subsequent decision ("0" or "1").
  • the synchronization for the down-clocking and the decision can in principle be exchanged in the order.
  • FIG. 1 shows a block diagram of a corresponding correlator according to the prior art.
  • FIG. 1 includes m-1 delay elements Z 1 , Z 2 ,..., Z m _i, m multipliers Mi, M 2 ,..., M m , a summer ⁇ , an arrangement 1 for downsampling and a Decision unit 2.
  • the received signal r (1, b) digitized with the resolution bit width b is correlated with the spreading sequence s (1... M).
  • r (l, b) is multiplied by the value s (l) of the spreading sequence s (l...
  • the signal r (l, b) delayed by the delay element Z 1 is also included multiplied by the value s (2) of the spreading sequence s (l... m) and the result is fed to the summer ⁇ .
  • the signal r (1, b), which is further delayed by the delay elements Z 2 is multiplied by the value s (3) of the spreading sequence s (1... M) and the result is fed to the summer ⁇ .
  • a spread or despreading of the data signal does not have to be in the baseband and accordingly the spreading or despreading of the data signal also does not have to be done with binary signals.
  • the spreaders or despreaders illustrated here are merely exemplary embodiments of correlators, so that the necessary synchronization of the signals for down-clocking can be implemented in any desired manner.
  • FIG. 2 The entire sequence of an exemplary spreading and despreading of a data signal is shown in simplified form in the form of a flowchart in FIG.
  • digitized chips of the chip rate 1 are generated from a data signal to be transmitted with the aid of a spreading sequence of length m.
  • this bit sequence is correlated in clock 1 with the spreading sequence (sequence s) of length m (see FIG. 1).
  • decision unit 2 By means of a subsequent decision unit "decision" (compare decision unit 2 according to FIG.
  • the frequency spreading method used is also referred to as the Direct Sequence Spread Spectrum (DSSS) method. This method is also used in wireless LANs according to the IEEE 802.11 standard.
  • the user data are linked by Exklusiv-Or (EXOR) with a predetermined sequence (spreading sequence) and then modulated to the bandwidth.
  • EXOR Exklusiv-Or
  • the spreading sequence used represents a bit sequence. If this spreading sequence has, for example, 8 bits or chips, each bit of the data signal to be transmitted must be linked to this spreading sequence EXOR. For an exemplary
  • the despreading in the baseband is carried out for the specified special case of binary input signals and spreading as described above.
  • the correlator according to FIG. 3 again comprises the delay elements Zi, Z 2 ,..., Z m _i known from FIG. 1 and one
  • FIG. 3 also comprises m negated exclusive OR arrangements negEXORi, negEXOR2,... NeGEXOR m and m memory register 3 for the spreading sequence, and an ne further negated exclusive-OR (negEXOR) arrangement 4.
  • the binary received signal c (l, 2) is in turn correlated with the spreading sequence s (l ... m).
  • c (l, 2) is associated with the value s (l) of the spreading sequence s (l... M) negatively connected with exclusive-or (negEXORi) and the result is fed to the summer ⁇ ; the signal c (l, 2) delayed by the delay element Z 1 with the value s (2) of the spreading sequence s (l...
  • Figure 4a comprises N multipliers Mi, M 2 , ..., M N.
  • the original data signal d (k) is multiplied by a spreading sequence sl (II) via a first multiplier Mi.
  • the signal c (11) resulting from this multiplication is multiplied by a second multiplier M 2 with a spreading sequence s 2 (12), which produces the signal c (12).
  • This process is continued using a total of N multipliers Mi, M 2 ...
  • FIG. 4 b shows how this principle can be used to expand an existing ZigBee architecture or hardware for a long-range application (data rate exemplary 1 kbit / s):
  • the ZigBee hardware expects input data with 40 kbit / s. s and spreads these with the Zig-Bee spreading sequence s2 of length 15, resulting in a transmission signal with 600 kchip / s.
  • sl s2.
  • a second embodiment also comprises N multipliers Mi, M 2 ... M N.
  • N the spreading sequences sl (II), s2 (12)... SN (IN) are multiplied by themselves. This takes place starting with the multiplication of the spreading sequences sl (II) and s2 (12) via the multiplier Mi (see FIG. 4c below). The result of this multiplication is subsequently multiplied by the multiplier M 2 with the third spreading sequence s3 (13). This process is continued for the further spreading sequences until the last spreading sequence sN (IN) is multiplied by the multiplication action of all preceding spreading sequences via the multiplier M N -i.
  • a correlator may also be used, as is shown by way of example in FIG.
  • FIG. 5 shows by way of example how the despreading of the received data signal can also be achieved by an arrangement of N simplified correlators, which in total require a smaller number of components than a conventional correlator for a spread sequence length n tot .
  • the correlator Ki comprises n-1 delay elements Z N , i, Z N , 2,..., Z S
  • c (l, b b ⁇ ) multiplied by the value sN (l) of the spreading sequence sN (l ... nN) via the multiplier Mi, and the result is fed to the summer ⁇ , which is supplied via the
  • the result of the summation of the individual signal components 1 to n of the multipliers Mi, M 2 ... M n in the summer ⁇ leads according to FIG. 5 to an output signal of the correlator Ki with the chip rate 1, which is made available to the subsequent correlator K 2 as an input signal becomes.
  • the correlator K 2 correlates the output signal of the correlator Ki with the spreading sequence s (NI) (1... NN).
  • the output signal of the correlator Ki multiplied by the multiplier Mi with the value s (N-1) (1) of the spreading sequence s (NI) (1 ... nN) and the
  • the result is fed to the summer ⁇ , which via the delay element Z N -i, 1 delayed output signal of the correlator Ki is the multiplier M 2 with the value s (NI) (2) of the Spreading sequence s (NI) (1 ... nN) is multiplied and the result is fed to the summer ⁇ , which via the delay elements Z N -i, 2 further delayed output of the correlator K 1 with the value s (NI) (3) the spreading sequence s (NI) (1 ... nN) multiplied and the result is fed to the summer ⁇ .
  • These steps are repeated in the correlator K 2 according to Figure 5, until the all the n-1 delay elements Z N -i, i, -i N Z 2 ...
  • This process described for the correlators Ki and K 2 is continued in correspondingly executed correlators K 3 to K N - 1 until the output signal of the correlator K N - 1 (not shown) is made available to the last correlator K N of the arrangement according to FIG becomes. As in all previous steps, this output signal of the correlator K N -i has the chip rate 1.
  • the final correlator K N of the row 1 to N of correlators comprises n-1 delay elements Zi, 1, Zi, 2 ...
  • Output of the correlator K N -1 is multiplied by the multiplier M 2 with the value sl (2) of the spreading sequence sl (l ... nl) and the result is fed to the summer ⁇ , the via the delay elements Z 1 , 2 further delayed output signal of the correlator K N -i is multiplied by the value sl (3) of the spreading sequence sl (l ... nl) and the result is fed to the summer ⁇ .
  • the desired despread bit signal d (k) is obtained by a decision in bit "0" or bit "1", which is the original input to the transmitting unit fed and to be transmitted data signal corresponds.
  • the procedure in accordance with FIG. 5 corresponds to a depletion of the transmitted data signal in the reverse order of spreading in the transmitter of a radio transmission arrangement, whereby in the correlators Ki to K N also the spreading sequences used to spread the data signal are applied in reverse order to despreading.
  • the correlators Ki to K N By this division into N individual correlators Ki to K N on the receiver side, there is a saving in the number of multipliers required compared to a single conventional correlator.
  • the exemplary embodiment of the despreading of a data signal according to FIG. 5 leads to the same result as the despreading of a data signal with a conventional correlator if the data signal to be transmitted has a single spreading sequence Si (ni)...
  • FIG. 6 shows in a flowchart in a clear form the course of the despreading by the multi-stage correlator according to FIG. 5.
  • the signal received on the receiver side is correlated stepwise in reverse order with the spreading sequences used in accordance with the spreading.
  • the received digital chip signal with the chip rate 1 is made available to the first correlator Ki with an incoming bit width b ⁇ .
  • the incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator Ki.
  • the incoming and the outgoing clock chip or the chip rate be for the correlator K2 respectively 1.
  • oversampling nN
  • the second despreading here is s (NI) (penultimate spreading sequence for the signal spreading) with the Sp Dahlfol- gene length n (NI) is applied (see correlator K 2 according to Figure 5).
  • the output signal of the correlator K 2 is obtained in this way after correlation with the despreading sequence s (NI) (compare correlator K 2 according to FIG. 5) to cor (NI) (1, b2) with the chip rate 1 and the outgoing bit width b2.
  • This process is subsequently repeated stepwise via the correlators K 3 to K N - 1 with corresponding input signals cor from the preceding correlators and corresponding bit widths, oversampling, spreading sequences and spreading sequence lengths and the chip rate 1 until, as the output signal of the correlator K N -1, the output signal cor2 (1, b (NI)) with the chip rate 1 and the bit width b (NI) is available.
  • This over-sampled signal cor2 (1, b (NI)) overclocked by the correlator K N -1 with the chip rate 1 and the bit width Id (b (N-2) -n 2) b (N 1) is shown in FIG passed on to the last correlator K N (ld: is the dual logarithm, the result rounded up to the next larger number of bits).
  • the incoming and the outgoing clock chip or the chip rate be for the correlator K N, respectively 1.
  • the last despreading sequence s1 (first spreading sequence in the case of signal spreading) with the spreading sequence length n1 is used in correlator K N (compare correlator K 2 according to FIG. 5).
  • the output signal of the correlator K N results in this way after the correlation with the despreading sequence sl (see Correlator K N according to FIG. 5) to corl (1, b N ) with the chip rate 1 and the outgoing bit width b N.
  • Bit 0 or 1, resulting in the final and desired output d (k, 1) of the original bit rate k and bit width 1.
  • the sequence of downclocking and decision is again interchangeable, without this having an effect on the result of the arrangement according to FIGS. 5 and 6.
  • correlators with a stepwise correlation are derived below. These include stepwise correlators with final separation into logical bit values "0" and “1”, in which a down-sampling of the chip rate is performed after each partial correlator (successive down-clocking) so that no overclocked data signal is fed to the respective subsequent correlator (see below) Figure 7a). Furthermore, the following alternative embodiments include
  • Correlators with only a final down-clocking of the chip rate in which after each partial correlator a decision is made in logical bit values "0" and "1" (sukzes- sive decision), so that an IBit of broad chip signal with overclocking is made available to the respective subsequent correlator (see the following FIG. 7b).
  • correlators include sub-correlators in which the respective subsequent sub-correlators are provided with a 1-bit-wide chip signal without overclocking. This means that after each partial correlator, a down-clocking of the chip signal and a decision in logical bit values "0" and
  • FIG. 7 shows in a flowchart in a clear form the course of the despreading by multistage correlators.
  • FIG. 7a shows the sequence of despreading of a data signal by stepwise correlators with final decision into logical bit values "0" and "1", with down-sampling of the chip rate being carried out after each partial correlator (successive down-clocking), so that the respectively following correlator is not over-clocked Data signal is supplied.
  • the first despreading sequence sN last spreading sequence in the signal spreading
  • the spreading sequence length nN is used here (compare correlator Ki according to FIG. 5).
  • the output signal of the correlator Ki results after correlation with the despreading sequence sN (compare correlator Ki according to FIG. 5) to corN (10, bl) with the chip rate 10 and the outgoing bit width bl.
  • This signal corN (10, bl) with the chip rate 10 generated by the correlator Ki is converted in the following arrangement 1 for down-sampling into a signal corN (II, bl) with the chip rate 10 / nN and subsequently forwarded to the second correlator K 2 ,
  • This process is subsequently stepwise through the correlators K 3 to K N _ i with corresponding Input signals cor from the previous correlators and corresponding bit widths, oversampling, spreading sequences and spreading sequence lengths and down-clocks in arrangements 1 are repeated until the input signal for the correlator K N is the signal cor2 (1 (NI), b (NI)) Chip rate 1 (N-2) / (NI) and the bit width b (NI) is available.
  • the here last despreading sequence sl first spreading sequence in the signal spreading
  • the spreading sequence length nl applied see correlator K2 according to Figure 5).
  • the output signal of the correlator K N results in this way after correlation with the despreading sequence sl (see correlator K N according to Figure 5) to corl (1 (NI), bN) with the chip rate 1 (NI) and the outgoing bit width bN.
  • the chip clock is re-clocked via the arrangement 1 and thus down-converted to the original bit clock (compare arrangement 1 according to FIG. 5).
  • FIG. 7b shows the sequence of the despreading of a data signal by means of stepwise correlators with final downshifting after the last partial correlator, whereby after each
  • Partial correlator a decision in logical bit values "0" and "1" is performed (successive decision), so that the respective subsequent correlator an overclocked chip data signal is fed with IBit width.
  • the incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator Ki.
  • the first despreading sequence sN last spreading sequence
  • nN spreading sequence length
  • This signal corN (1, bl) with the chip rate 1 generated by the correlator Ki becomes in the subsequent decision unit (decision in logical bit values "0" and "1") a signal corN (1, 1) with the chip rate 1 and the bit width 1 converted and subsequently forwarded to the second correlator K 2 .
  • the incoming and the outgoing clock chip or the chip rate be 2 K for the correlator in each case 1.
  • the second despreading is applied here s (NI) (penultimate spreading sequence for the signal spreading) with the Sp Grande Kunststoffmaschine n (NI) (see correlator K 2 according to Figure 5).
  • the output signal of the correlator K 2 results in this way after correlation with the despreading sequence s (N-1) (compare correlator K 2 according to Figure 5) to cor (NI) (1, b2) with the chip rate 1 and the outgoing bit width b2.
  • this output signal is converted in the following decision unit 2 (decision into logical bit values "0" and "1") into a signal cor (NI) (1, 1) with the chip rate 1 and the bit width 1.
  • This process is subsequently repeated stepwise via the correlators K 3 to K N -i with corresponding input signals cor from the preceding correlators and corresponding incoming and outgoing bit widths, O-sampling, spreading sequences and spreading sequence lengths and decisions in arrangements 2 until as input signal for the correlator K N the signal cor2 (1, 1) with the chip rate 1 and the bit width 1 is available.
  • This signal cor2 (1, 1) with the chip rate 1 and the bit width 1 made available by the correlator K N -i is subsequently forwarded to the last correlator K N according to FIG. 7b.
  • the incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K N.
  • the last despreading sequence s1 first spreading sequence in the case of signal spreading
  • the spreading sequence length n1 is used in the correlator K N (compare correlator K 2 according to FIG. 5).
  • the output signal of the correlator K N is converted in the following decision unit 2 (decision into logical bit values "0" and "1") into a signal corl (1, bN) with the chip rate 1 and the bit width bN.
  • the chip clock is clocked down via the arrangement 1 to the original bit clock (compare arrangement 1 according to FIG. 5).
  • d (k, 1) of the original bit rate k and the bit width 1 of the data signal to be transmitted is again interchangeable, without this having an influence on the result of the arrangement according to FIG. 7b.
  • FIG. 7c shows the sequence of despreading of a spread data signal or chip signal by stepwise correlators, whereby after each partial correlator a decision is made in logical bit values "0" and "1" (successive decision) and after each partial correlator a downclocking of the output signal is carried out (successively Downclocking), so that the respective subsequent correlator, a non-overclocked chip data signal is supplied with IBit width.
  • the decision and the Down-clocking is interchangeable after each correlator in the order, without affecting the final signal provided to the subsequent correlator.
  • the first despreading sequence sN last spreading sequence in the case of signal spreading
  • the spreading sequence length nN is used (compare correlator Ki according to FIG. 5).
  • This signal corN (10, bl) with the chip rate 1 generated by the correlator Ki is converted in the following arrangement 1 for down-sampling to a signal corN (II, bl) with the chip rate 10 / nN.
  • decision unit 2 decision in logical bit values "0" and "1" this is
  • Signal corN (ll, bl) is converted into a signal corN (l, 1) with the chip rate 11 and the bit width 1 and subsequently forwarded to the second correlator K 2 .
  • the incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K 2.
  • the second depletion sequence s (NI) (penultimate spreading sequence in the signal spreading) with the spreading sequence length n (NI) is used (compare correlator K 2 according to FIG. 5).
  • This signal cor (NI) (11, b2) with the chip rate 1 generated by the correlator Ki is used in the following arrangement 1 for down-clocking into a signal cor (NI) (12, b2) with the chip rate 11 / n (NI ) transformed.
  • the sequence of down-clocking and decision after the correlator is in turn interchangeable, without this having an influence on the result of the arrangement according to FIG. 7c.
  • the described process is subsequently performed stepwise via the correlators K 3 to K N - 1 with corresponding input signals cor from the preceding correlators and corresponding incoming and outgoing chip rates, bit widths, oversampling,
  • Spreading sequences, spreading sequence lengths, downtuning in arrangements 1 and decisions in arrangements 2 are repeated until, as input signal for the correlator K N, the signal cor2 (1 (n-1), 1) with the chip rate l (N-2) / (nl) and the bit width 1 is available.
  • This signal cor2 (l (nl), 1) provided by the correlator K N - 1 with the chip rate l (N-2) / (nl) and the bit width 1 is subsequently forwarded to the last correlator K N according to FIG ,
  • the incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K N.
  • the last sequence of despreading s 1 first spreading sequence in the case of signal spreading
  • the spreading sequence length n 1 is used here (compare correlator K 2 according to FIG. 5).
  • This signal corl (1 (N-1), bN) generated by the correlator Ki at the chip rate 1 (NI) is converted in the following arrangement 1 for down-clocking into a signal corl (IN, bN) at the chip rate IN, this being Chip rate of the original bit rate k of the non-spread data signal corresponds.
  • this signal corl (lN, bN) is converted into a signal d (k, 1) with the bit rate k and the bit width 1.
  • the result is a desired output signal d (k, 1) corresponding to the original data signal with the original bit rate k and the bit width 1 of the data signal to be transmitted.
  • the sequence of downclocking and decision after the last correlator K N is again interchangeable, without this having an influence on the result of the arrangement according to FIG. 7c.
  • two-stage embodiments of correlators (application of 2 spreading sequences to the data signal) for the cases concluding decision are subsequently converted into logical bit values "0" and "1” and final Down-clocking of the output signal or successive decision in logical bit values "0" and "1” and final down-clocking of the output signal described.
  • the embodiment of an exemplary two-stage correlator shown in FIG. 8 is suitable for the despreading of binary signals in the baseband after the signal demodulation.
  • Another special feature of the embodiment illustrated in FIG. 8 is that two identical spreading sequences s (l)... S (n) of length n are used to spread the data signal to be transmitted. nals and for the receiver-side despreading be used in the correlator of Figure 8. The despreading further takes place using a final decision in logical bit values "0" and "1" and a final down-clocking of the output signal.
  • Figure 8 comprises n-1 delay elements Zi, i, Zi, 2, ..., Zi, n _i each having a time delay z "1 and a summer ⁇ i.
  • Figure 8 further comprises n negated exclusive-or (negEXOR) arrangements negEXORi , i, negEXORi, 2 ••• negEXORi, n and a SpeI ⁇ cherregisteran extract 3 the length Id (n) bits.
  • n negated exclusive-or negEXOR
  • n negated exclusive or (negEXOR) arrangements negEXOR 2, i, negEXOR 2, 2, ..., negEXOR 2, n and a memory register array 4 of the length ld (nn) bit and another negated exclusive-OR (negEXOR) arrangement 5.
  • the binary input signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-or (negEXORi, i) linked and the result is fed to the summer ⁇ i, which delayed over the delay element Zi
  • 1 Input signal is negated with the value s (2) of the spreading sequence s (l ... n) Exclusive OR (negEXORi, 2 ) linked and the result supplied to the summer ⁇ i, via the delay element Zi
  • 2 further delayed input signal is the value s (3) of the spreading sequence s (l ... n) negates exclusive-or (negEXORi, 3) and the result is fed to the summer ⁇ i.
  • the result of the summation of the first partial correlator in the second partial correlator is in turn correlated with the spreading sequence s (l... N).
  • the binary signal with the value s (l) of the spreading sequence s (l... N) is negated exclusive-or (negE
  • the signal delayed by the delay element Z 2 , 1 is transmitted to the storage register arrangement S 2 , 2 and is multiplied by the value s (2) of the spreading sequence s (l .. n) negates exclusive-OR (negEXOR 2 , 2 ) linked and the result supplied to the summer ⁇ i, via the delay element Z 2 , 2 further delayed signal is transmitted to the storage register arrangement S 2 , 3 and from there with the value s (3) the spreading sequence s (l... N) negates exclusive-or (negEXORi, 3) and the result is fed to the summer ⁇ 2 .
  • FIG. 8 shows a tabulation of the components required for a two-stage correlator according to FIG. 8 for the two mentioned embodiments of the down-clocking with final decision in binary values (logic values "0" and "1") the two embodiments differ only in the number of delay elements (z "1 ) required for the realization.
  • nn is the number of delay elements (z "1) for an embodiment with a final down-sampler (n-1) • 1 + n • Id (n)) and in the embodiment with successive down-sampler (n- 1) • (l + ld (n))
  • the number of logic elements required for the two-stage correlator according to FIG. 8 is n • (1 + ld (n)) +1 in both cases, the number of required
  • FIG. 10 shows an embodiment of a two-stage correlator for the case of the successive decision in binary logic values "0" and "1" after each sub-stage of the correlator.
  • Figure 10 comprises n-1 delay elements Zi, i, Zi, 2, ..., Zi, n _i each having a time delay z "1 and a summer ⁇ i.
  • Figure 10 further comprises n negated exclusive-or (negEXOR) arrangements negEXORi , i, negEXORi, 2, ⁇ , negEXORi, n and a SpeI ⁇ cherregisteran inch 3 the length Id (n) bits.
  • the exemplary embodiment according to Figure 10 furthermore comprises n negated exclusive-OR (negEXOR) arrangements negEXOR 2 , i, negEXOR 2 , 2 , ..., negEXOR 2 , n and a memory register arrangement 4 of length
  • the binary received signal in the first partial correlator is correlated with the spreading sequence s (l... N).
  • the binary input signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-or (negEXORi, i) linked and fed the result to the summer ⁇ i; the delayed via the delay element Zi, 1 input signal with the value s (2) of the spreading sequence s (l ... n) negated exclusive-or (negEXORi, 2 ) linked and fed the result to the summer ⁇ i; the input signal with the value s (3) of the spreading sequence s (l... n) further negated via the delay element Zi, 2 negates the exclusive-or (negEXORi, 3) and supplies the result to the summer ⁇ i.
  • the binary signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-OR (negEXOR2, i) linked and the result is fed to the summer ⁇ 2 , via the delay element Z 2 , i delayed signal is negated with the value s (2) of the spreading sequence s (l ... n) exclusive-or (negEXOR2,2) ver ⁇ ties and the result to the summer ⁇ i fed, via the delay element Z 2 , 2 on delayed signal is negated with the value s (3) of the spreading sequence s (l ... n) exclusive-or (negEXORi, 3) and the result is fed to the summer ⁇ 2 .
  • FIG. 11 shows a tabulation of the components required for a two-stage correlator according to FIG. 10 for the two mentioned embodiments of the downclocking with successive decision in binary values (logic values "0" and "1").
  • the number of logic elements required for the two-stage correlator according to FIG. 10 is 2-n + 2 in both cases, the number of required storage registers for the spreading sequence s (l... N) is n and both Summer ⁇ i as well as summer ⁇ 2 each add over a width of n bits.
  • the number of delay elements is (m-1)
  • the number of logic elements required is (m + 1)
  • the number of required storage registers for the spreading sequence s is m
  • the (single) totalizer adds over a width of m bits.
  • the number of required logic elements neg. EXOR
  • the number of required storage registers for the spreading sequence s (l ... m) is 225 and the (single) summer must be designed for addition over a width of 225 bits.
  • a two-stage correlator using two spreading sequences s (l... N) of length 15 according to FIG. 13 in the case of a final decision in binary mode requires values "0" and "1" (see FIG. 8) and, in the event of a final down-clocking, 854 delay elements, 76 logic elements (neg. EXOR), 15 memory registers and two summers, each once across the width of 15 bits or 60 bits.
  • the same two-stage correlator requires only 70 delay elements to implement in the case of a final decision in binary values "0" and "1” and, in the case of a successive down-clocking, again 76 logic elements (neg. EXOR), 15 memory registers and two summers the width of 15 bits or 60 bits.
  • a two-stage correlator using two spreading sequences s (l... N) of length 15 according to FIG. 13 in the case of a successive decision requires binary values "0" and "1" (see FIG Case of a final down-clocking 225 delay elements, 32 logic elements (neg EXOR), 15 memory registers and two summers across the width of 15 bits each.
  • the same two-stage correlator requires only 28 delay elements, again 32 logic elements (neg. EXOR), 15 memory registers and two summers, once in the event of a successive decision in binary values "0" and "1” and in the case of a successive down-clocking the width of 15 bits or 60 bits.
  • the embodiments shown form only a small part of a variety of implementation options.
  • the despreading of the signals does not have to take place, as shown by way of example, in the baseband after demodulation.
  • a despreading can be carried out in a corresponding manner in every other subarea of a receiver, for example also before the demodulation at the intermediate frequency or high frequency level.
  • any other spreading sequences which satisfy the required autocorrelation properties can be used. It is not necessary to use identical spreading sequences of the same length for spreading or despreading the data signals in multistage correlators, as shown in the examples.
  • the resolution of 1 bit in the data signal shown here by way of example is also not defined, so that any resolution and processing bandwidths can be used.
  • FIG. 14 shows the autocorrelation function of a simple, 511-bit PRBS-9 spreading sequence, which has optimum despreading characteristics with respect to a noisy message channel.
  • FIG. 14 shows the autocorrelation function over a range of bit positions from 0 to 1000 (abscissa). The strongly pronounced maximum of the correspondences of the autocorrelation (ordinate) at bit position 511 is very clear. In the remaining range, the values of the autocorrelation function are at zero, as well as from the spread representation in FIG.
  • FIG. 15 shows the autocorrelation function of a two-fold, 15-bit long (15x15) ZigBee spreading sequence, which does not have optimal despreading characteristics with respect to a noisy message channel.

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Abstract

Étalement/désétalement multiple de signaux à spectre étalé, par séquences d'étalement multiples. L'invention concerne un procédé de désétalement d'un signal reçu (c) à spectre étalé, selon lequel le désétalement s'effectue en au moins deux phases. Chaque phase comprend l'étape consistant à produire un signal de corrélateur par corrélation d'un signal à spectre étalé (c, corN,..., cor2) avec une séquence d'étalement (sN,…, s1), et au moins une phase comprend les étapes consistant à décimer le signal de corrélateur (corN, cor(N-1),…, cor1) d'un facteur correspondant à la longueur de la séquence d'étalement (sN,..., s1), et/ou à décider, à l'aide du signal de corrélateur, si un symbole donné a été reçu.
PCT/EP2008/057897 2007-06-21 2008-06-20 Étalement/désétalement multiple de signaux à spectre étalé, par séquences d'étalement multiples WO2008155418A1 (fr)

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DE102009005119B4 (de) 2009-01-19 2018-03-29 Continental Automotive Gmbh Signalverarbeitungsanordnung und Verfahren zur Signalverarbeitung
DE102017206008A1 (de) * 2017-04-07 2018-10-11 Bayerische Motoren Werke Aktiengesellschaft Schlüsseleinrichtung, Authentifizierungseinrichtung, Authentifizierungssystem, Verfahren zum Freigeben eines Fahrzeugs und computerlesbares Speichermedium

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WO2000067405A1 (fr) * 1999-04-29 2000-11-09 Siemens Aktiengesellschaft Procede pour former et pour determiner une sequence de synchronisation, procede de synchronisation, unite d'emission et unite de reception
US20050074054A1 (en) * 2003-09-24 2005-04-07 Spectrum5, Inc. Matched filter for scalable spread spectrum communications systems
US20050249268A1 (en) * 2004-05-05 2005-11-10 Texas Instruments Incorporated (Updated) preamble for FDMA

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WO2000067405A1 (fr) * 1999-04-29 2000-11-09 Siemens Aktiengesellschaft Procede pour former et pour determiner une sequence de synchronisation, procede de synchronisation, unite d'emission et unite de reception
US20050074054A1 (en) * 2003-09-24 2005-04-07 Spectrum5, Inc. Matched filter for scalable spread spectrum communications systems
US20050249268A1 (en) * 2004-05-05 2005-11-10 Texas Instruments Incorporated (Updated) preamble for FDMA

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* Cited by examiner, † Cited by third party
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US11611369B2 (en) 2018-04-20 2023-03-21 Fraunhofer-Gesellschaft Zur F Rderung Der Angewandten Forschung E.V. Packet correlator for a radio transmission system

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