WO2008149806A1 - Method for evaluating contamination of semiconductor manufacturing apparatus - Google Patents

Method for evaluating contamination of semiconductor manufacturing apparatus Download PDF

Info

Publication number
WO2008149806A1
WO2008149806A1 PCT/JP2008/060023 JP2008060023W WO2008149806A1 WO 2008149806 A1 WO2008149806 A1 WO 2008149806A1 JP 2008060023 W JP2008060023 W JP 2008060023W WO 2008149806 A1 WO2008149806 A1 WO 2008149806A1
Authority
WO
WIPO (PCT)
Prior art keywords
contamination
semiconductor manufacturing
manufacturing apparatus
semiconductor wafer
film
Prior art date
Application number
PCT/JP2008/060023
Other languages
French (fr)
Japanese (ja)
Inventor
Kenji Araki
Takao Takenaka
Masanori Mayusumi
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to JP2009517843A priority Critical patent/JP5120789B2/en
Publication of WO2008149806A1 publication Critical patent/WO2008149806A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Chemical Vapour Deposition (AREA)
  • Sampling And Sample Adjustment (AREA)

Abstract

Provided is a method for evaluating contamination of semiconductor manufacturing apparatuses, such as a vapor phase growing apparatus, by which a contamination quantity in processing (for instance, vapor phase growing) can be grasped by evaluation. In the method for evaluating contamination of the semiconductor manufacturing apparatus, a semiconductor wafer to be evaluated is manufactured by performing prescribed process to a sample semiconductor wafer by using the semiconductor manufacturing apparatus, and contamination of the manufactured semiconductor wafer is evaluated. The surface of the sample semiconductor wafer is covered with at least one type of film selected from among a group composed of silicon thermally-oxidized film, a silicon oxide film deposited by CVD, amorphous silicon film and a polysilicon film.
PCT/JP2008/060023 2007-06-05 2008-05-30 Method for evaluating contamination of semiconductor manufacturing apparatus WO2008149806A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009517843A JP5120789B2 (en) 2007-06-05 2008-05-30 Method for evaluating contamination of semiconductor manufacturing equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007149659 2007-06-05
JP2007-149659 2007-06-05

Publications (1)

Publication Number Publication Date
WO2008149806A1 true WO2008149806A1 (en) 2008-12-11

Family

ID=40093624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060023 WO2008149806A1 (en) 2007-06-05 2008-05-30 Method for evaluating contamination of semiconductor manufacturing apparatus

Country Status (3)

Country Link
JP (1) JP5120789B2 (en)
TW (1) TW200915459A (en)
WO (1) WO2008149806A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012058078A (en) * 2010-09-09 2012-03-22 Sumco Corp Method for evaluating impurity contamination of environmental atmosphere
JP2014045007A (en) * 2012-08-24 2014-03-13 Shin Etsu Handotai Co Ltd Method for evaluating contamination of vapor phase growth apparatus and method for producing silicon epitaxial wafer
JP2014099479A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination in furnace of epitaxial growth device and test wafer for contamination evaluation
JP2014099478A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination of epitaxial silicon wafer and method for evaluating contamination in furnace of epitaxial growth device
TWI584352B (en) * 2013-03-12 2017-05-21 環球晶圓日本股份有限公司 Saturation voltage estimation method and silicon epitaxial wafer manufacturing method
KR20200095661A (en) * 2019-02-01 2020-08-11 에스케이실트론 주식회사 Method of analyzing a metal contamination in an epitaxial wafer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150620A (en) * 1984-01-18 1985-08-08 Toshiba Corp Method for evaluation of cleanness
JPH11204604A (en) * 1998-01-12 1999-07-30 Shin Etsu Handotai Co Ltd Method and apparatus for collecting metallic impurity in wafer periphery
JP2001174375A (en) * 1999-12-20 2001-06-29 Toshiba Corp Wafer for evaluation of metal contamination and method therefor
JP2002252179A (en) * 2001-02-22 2002-09-06 Shin Etsu Handotai Co Ltd Method of cleaning tube for heat treatment of semiconductor substrate, and metallic contamination getter substrate, and regenerative metal contamination getter substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4761179B2 (en) * 2001-07-19 2011-08-31 信越半導体株式会社 Method for measuring concentration of boron adsorbed on wafer surface and method for evaluating boron level in environmental atmosphere

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150620A (en) * 1984-01-18 1985-08-08 Toshiba Corp Method for evaluation of cleanness
JPH11204604A (en) * 1998-01-12 1999-07-30 Shin Etsu Handotai Co Ltd Method and apparatus for collecting metallic impurity in wafer periphery
JP2001174375A (en) * 1999-12-20 2001-06-29 Toshiba Corp Wafer for evaluation of metal contamination and method therefor
JP2002252179A (en) * 2001-02-22 2002-09-06 Shin Etsu Handotai Co Ltd Method of cleaning tube for heat treatment of semiconductor substrate, and metallic contamination getter substrate, and regenerative metal contamination getter substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012058078A (en) * 2010-09-09 2012-03-22 Sumco Corp Method for evaluating impurity contamination of environmental atmosphere
JP2014045007A (en) * 2012-08-24 2014-03-13 Shin Etsu Handotai Co Ltd Method for evaluating contamination of vapor phase growth apparatus and method for producing silicon epitaxial wafer
JP2014099479A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination in furnace of epitaxial growth device and test wafer for contamination evaluation
JP2014099478A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination of epitaxial silicon wafer and method for evaluating contamination in furnace of epitaxial growth device
TWI584352B (en) * 2013-03-12 2017-05-21 環球晶圓日本股份有限公司 Saturation voltage estimation method and silicon epitaxial wafer manufacturing method
KR20200095661A (en) * 2019-02-01 2020-08-11 에스케이실트론 주식회사 Method of analyzing a metal contamination in an epitaxial wafer
KR102261633B1 (en) 2019-02-01 2021-06-04 에스케이실트론 주식회사 Method of analyzing a metal contamination in an epitaxial wafer

Also Published As

Publication number Publication date
TW200915459A (en) 2009-04-01
JP5120789B2 (en) 2013-01-16
JPWO2008149806A1 (en) 2010-08-26

Similar Documents

Publication Publication Date Title
WO2008149806A1 (en) Method for evaluating contamination of semiconductor manufacturing apparatus
WO2011071937A3 (en) Method of cleaning and forming a negatively charged passivation layer over a doped region
WO2010042577A3 (en) Advanced platform for processing crystalline silicon solar cells
WO2011133965A3 (en) Passivation methods and apparatus for achieving ultra-low surface recombination velocities for high-efficiency solar cells
JP2013546169A5 (en)
EP2533305A3 (en) Method for blister-free passivation of a silicon surface
WO2006107532A3 (en) Single wafer thermal cvd processes for hemispherical grained silicon and nano-crystalline grain-sized polysilicon
MY173674A (en) Passivation stack on a crystalline silicon solar cell
JP2017504186A5 (en)
TW200636827A (en) Silicon oxide cap over high dielectric constant films
EP2618365A3 (en) Method for depositing a chlorine-free conformal SiN film
WO2011126660A3 (en) Method of forming a negatively charged passivation layer over a diffused p-type region
WO2009149167A3 (en) Low temperature deposition of silicon-containing films
TW200710963A (en) Method for forming silicon-containing materials during a photoexcitation deposition process
WO2013003676A3 (en) Systems and methods for controlling etch selectivity of various materials
WO2006007077A3 (en) Composition and method for low temperature chemical vapor deposition of silicon-containing films including silicon carbonitride and silicon oxycarbonitride films
TW200729303A (en) Method for manufacturing semiconductor device
WO2012116259A3 (en) Dry chemical cleaning for gate stack preparation
WO2007126482A3 (en) Methods for forming thin oxide layers on semiconductor wafers
JP2012114423A5 (en)
WO2012085155A3 (en) Method for heterojunction interface passivation
TW200802696A (en) Method and semiconductor material for forming silicon device
SE0900641L (en) Process for manufacturing semiconductor device
SG159436A1 (en) Method for fabricating a semiconductor on insulator substrate with reduced secco defect density
CN110349875B (en) Method for measuring change of surface charge density of wafer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08777034

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009517843

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08777034

Country of ref document: EP

Kind code of ref document: A1