WO2008148416A1

WO2008148416A1 - Electronic circuit device and method for operating an electronic circuit device

Info

Publication number: WO2008148416A1
Application number: PCT/EP2007/005143
Authority: WO
Inventors: Matthias Schweikart
Original assignee: Siemens Aktiengesellschaft
Priority date: 2007-06-06
Filing date: 2007-06-06
Publication date: 2008-12-11

Abstract

The invention relates to an electronic circuit device (ES) having at least one state machine (ZM) having states (S1, S2, S3, S4), each allowing at least one state transition (ST1, ST2, ST3, ST4). For this purpose, the electronic circuit device (ES) according to the invention comprises at least one observation outlet (A) for each of the state machines (ZM), and is configured for the output of a bit succession characterizing the respectively activated state transition (for example, ST2) via the at least one observation outlet (A). The invention further relates to a method for operating an electronic circuit device (ES).

Description

description

Electronic circuit unit and method for operating an electronic circuit unit

The present invention relates to an electronic circuit unit having at least one state machine with states which respectively allow at least one state transition.

Such an electronic circuit unit is known for example from the published German patent application DE 37 19 181 Al. This describes a finite state machine and the use of this state machine in an electrical circuit unit in the form of an integrated circuit. The known state machine is constructed using programmable logic arrays and has a state register which stores the last state of the state machine. Starting from the respective current state, different state transitions are possible, which change the existing state into a new state or follow-up state.

State, whereby also a transition of the state back to itself, i. a persistence in the existing state, is possible.

Typically, state machines, also referred to as finite state machines, are implemented in digital electronic circuits using logic gates, flip-flops, and Programmable Logic Controllers (PLCs). In this case, a memory unit, for example in the form of a register, is used to store the respective state, a logic unit in the form of a programmable logic controller for determining state transitions, for example, and a further logic unit to output data. Corresponding state machines are common especially in electronic circuit units in the form of digital integrated circuits. The state machines react to events at the inputs of the electronic circuit unit and trigger the internal processing of the data present at the inputs.

If an electronic circuit unit behaves differently than expected, it would be exceedingly helpful for clarifying the cause of the error to be able to observe or understand the exact sequence of the states of the auxiliary machines of the electronic circuit unit. However, the problem here is that a state vector describing the respective state of the state machine typically has a size of approximately 4 to 6 bits. In order to make this information visible at the outputs of the electronic circuit unit, approximately 50 corresponding observation outputs would thus already be required in the case of an electronic circuit unit with, for example, 10 state machines contained. Since, however, the number of outputs of an electronic circuit unit is usually strictly limited, in practice usually corresponding monitoring outputs are dispensed with.

The present invention has for its object to provide an electronic circuit unit of the type mentioned, which allows a powerful and versatile monitoring of the state machines of the electronic circuit unit.

This object is, Inventive ^¬ dissolved for an electronic circuit unit having at least one state machine with states, each ^¬ weils at least allow a state transition according to characterized in that the electronic circuit unit for each of the state machines each have at least one Has observation output and is designed to output a respective activated state transition characterizing bit sequence on the at least one observation output.

The electronic circuit unit according to the invention, which is preferably an integrated circuit, is advantageous because it allows instead of identifying the respective state information characterizing the respective activated state transition bit sequence on the at least one observation output, the electronic Circuit unit for each of the state machines, can be output. In this case, the bit sequence which characterizes the respectively activated state transition preferably consists of one bit or two bits for each of the state machines. Since, in one state, the number of possible state transitions is usually significantly less than the total number of states of the state machine, the amount of information that is output via the at least one observation output for each of the state machines is advantageously as compared to that at the current state State itself considerably reduced.

By way of example, assume that a state has four possible follow-state, ie four different state transitions allowed, wherein one of the possible Folgezu ^¬ unable may also be the previous state itself. An encoding of the possible state transitions can be coded using a bit sequence with two bits, ie the temporal sequence of the states of the respective state machine is observable on the basis of the output bit sequence. If a state in individual cases should have more possible state transitions, ie has more than four different sequence states, then provides a corresponding coding with two bits no immediately clear statement. Nevertheless, even in this case, the sequence of states can be recognized if, for example, not all four possible values are needed in the state transitions of the following states and, for example, only the values 0 and 1 in one possible branch, but only those in the other possible branch Values 2 and 3 are used. If a bit sequence with two bits should not be sufficient for a meaningful description of the respectively activated state transition, it is also possible, for example, to use a bit sequence of length 4, by means of which 16 state transitions can be distinguished.

The electronic circuit unit according to the invention advantageously makes it possible to significantly reduce the required observation outputs, which makes it possible to use appropriate observation outputs for electronic circuit units with at least one state machine in practice in many cases.

In a particularly preferred development, the electronic circuit unit according to the invention is configured such that the electronic circuit unit has a number of memory units corresponding to the number of bits in a bit sequence with a plurality of bits for each of the state machines, and the electronic circuit unit is designed such that that the content of at least one of the memory units is output on a rising edge of a clock signal and the content of at least one other of the memory units on a falling edge of the clock signal via the at least one observation output. This embodiment of the inventive electronic circuit unit is advantageous because it further Redu ^¬ cation of the number of required observation outputs allows. If the bit sequence characterizing the respectively activated state transition has, for example, a length of 2 bits, it is advantageously possible to output this bit sequence via a single observation output for the respective state machine. This is made possible by outputting one of the two rising edge bits and the other bit with the following falling edge of the clock signal. Since state machines usually make state changes only with increasing or only falling clock edges, all state changes in the case described can thus be output completely via a single observation output.

In a further particularly preferred embodiment of the electronic circuit unit according to the invention, the memory units for each of the state machines are each connected to the at least one observation output by means of a multiplexer. This is advantageously a particularly simple way of outputting the contents of the two storage units to the at least one observation output.

Preferably, the electronic circuit unit according to the invention can also be designed such that the memory units are each designed as flip-flops. This offers the advantage that it is at the flip-flop to the übli ^¬ cherweise in connection with state machines used type of memory units so that the thus formed further electronic circuit unit according to the invention is inexpensive and versatile.

Preferably, the electronic scarf ^¬ processing unit according to the invention can also be designed such that they are for outputting from the respective state of at least one Standsmaschine characterizing data has at least one further observation output. Due to limited storage capacity, it will generally not be possible to record all state changes starting when the electronic circuit unit is switched on until the time when a malfunction occurs. For this reason, it is advantageous if the electronic circuit unit additionally has a further observation output for outputting data characterizing the respective state of the at least one state machine, for example in the form of a state vector. In this case, the data characterizing the respective state of the at least one state machine is preferably output serially via only a single further observation output for all state machines. This can be done, for example, in such a way that a protocol is defined for this further observation output according to which the characteristic data is output in blocks. The output of the data preferably takes place for all state machines in blocks of the same size, ie identical number of bits. In a particularly preferred embodiment, the number of bits of the blocks may be larger by one than the largest of the state vectors of the state machines. In this case, for example, the first data block can only contain bits with the value 1 and thus identify the beginning of the characteristic data. In the following blocks of the current to the ^¬ sem time state of each state machine can now be output in each case in a separate data block. Advantageously, the additional bit contained in each block can be assigned the value 0 in order to enable a differentiation from the first data block. In order to output the characteristic data more quickly from the electronic circuit unit via the further observation output, in this case again a part of the data can be used on a rising edge of a Clock signal and another part of the data are output on a falling edge of a clock signal.

The invention further relates to a method for operating an electronic circuit unit having at least one state machine with states which respectively allow a state transition.

With regard to the method, the present invention has for its object to provide a method of the aforementioned type, which allows a powerful and versatile monitoring of the state machines of the electronic circuit unit

This object is achieved according to the invention for a method for operating an electronic circuit unit having at least one state machine with states that permit at least one state transition, in each case one bit sequence characterizing the respective state transition for each of the state machines via one of the state machines output to the respective state machine associated observation output of the electronic circuit unit.

The bit sequence which characterizes the respective state transition is advantageously a bit sequence of length 1 or 2. According to the invention, a suitably short bit sequence, which also results in a correspondingly small number of required monitoring outputs, is made possible by a bit sequence characterizing the respective state transition and not a bit sequence characterizing the respective state itself is output. In practice, this results in a considerable reduction of the monitoring outputs required for monitoring the state machines of the electronic circuit unit, so that a corresponding monitoring of the state machines of electronic circuit units is made possible in many cases only by the inventive method.

Preferably, the method according to the invention can also be such that, in the case of a bit sequence with a plurality of bits and an electronic circuit unit, which has a number of memory units corresponding to the number of bits for each of the state machines, the content of at least one of the memory units at a rising edge of a memory unit Clock signal and the contents of at least one other of the memory units is output on a falling edge of the clock signal via the respective observation output. In accordance with the previous statements in connection with the corresponding embodiment of the electronic circuit unit according to the invention, this advantageously doubles the number of bits output per clock signal. This offers the advantage that, for example, in the case of a bit sequence of length 2 which characterizes the respective state transition, i. with 2 bits, a single observation output is sufficient to output the bit sequence.

In a further preferred embodiment, the method according to the invention is so pronounced that the content of the memory units for each of the state machines is output in each case by means of a multiplexer to the at least one observation output assigned to the respective state machine. This is advantageous because by means of a Multiple ^¬ xers a simple Zusammenfuhrung the contents of the storage chereinheiten on the at least one of the respective state machine associated observation output is possible.

In a particularly preferred development of the method according to the invention, flip-flops are used as memory units used. With appropriate flip-flops is a common, widely used and inexpensive type of storage unit.

Preferably, the method according to the invention can also take place in the form that data indicative of the respective state of the at least one state machine is output via at least one further observation output. This embodiment of the method according to the invention offers the advantage that, in addition to the output of the bit sequence characterizing the respectively activated state transition, an output of data characterizing the state of the at least one state machine is made possible over a period of time that generally extends over a plurality of clocks , Thus, for monitoring at intervals, which depend in particular on the number of state machines, the size of the data to be output and the number of other observation outputs, the complete information about the respective state of all state machines of the electronic circuit unit is preferably output. This information can be used in succession as a reference or reference point for the state transitions described by means of the activated state transition characterizing bit sequence. Thus, to fully understand the states of the state machines of the electronic circuit unit, it is only necessary to store those state transitions which have occurred since the time at which the data indicating the particular state of the at least one state machine is output have been referring. Preferably, only one additional observation output is used for all state machines of an electronic circuit unit. In the following the invention will be further explained by means of exemplary embodiments. This shows

1 shows a schematic sketch of an embodiment of the inventive electronic

Circuit unit,

2 shows in a circuit diagram a section of a further exemplary embodiment of the inventive electronic circuit unit and

FIG. 3 shows a schematic representation of the structure of data used in an exemplary embodiment of the method according to the invention, which characterizes the respective state of the at least one state machine.

FIG. 1 shows in a schematic sketch an exemplary embodiment of the electronic circuit unit according to the invention. Shown is an electronic circuit unit

ES, which has a schematically indicated state machine ZM. In addition, the electronic circuit unit ES, which is designed as a digital integrated circuit in the form of an ASIC (Application Specific Integrated Circuit), contains a plurality of further state machines as well as a multiplicity of further components, which however are not shown in FIG. 1 for reasons of clarity.

According to FIG. 1, the illustrated state machine ZM of the electronic circuit unit ES is in a state S1, from which the state machine ZM can proceed in successive states S1, S2, S3, S3 by means of state transitions ST1, ST2, ST3, ST4. The state transition ST1 causes the State machine ZM remains in the state Sl or goes back into this state.

As already explained above, the electronic circuit unit ES will generally have several corresponding state machines ZM. These react in each case to events in FIG. 1, for reasons of clarity also not shown, inputs of the electronic circuit unit ES and cause the processing of the data present at these inputs in the electronic circuit unit ES.

In order to be able to undertake a clarification of the reason in a simple and fast and hence also cost-effective manner in the event that the electronic circuit unit ES behaves differently than expected, the electronic circuit unit ES has an observation output A. As indicated in FIG. 1, the state transitions ST1, ST2, ST3, ST4 can be generated by outputting a bit sequence characterizing the respectively activated state transition with the possible bit sequences

Values 00, 01, 10, 11 are identified via the observation output A. This advantageously makes it possible to monitor the sequence of the state machine ZM at the observation output A. In the context of a preferred embodiment of the inventive electronic circuit unit described in more detail in connection with FIG. 2, only one observation output A per state machine ZM is required since information about the respectively activated state transition ST1, ST2, ST3 is output via the observation output A. , ST4 and not about the respective active or activated state Sl, S2, S3, S4 itself is output.

Advantageously, the electronic circuit unit ES has another observer, not shown in FIG. output for outputting the respective state of the at least one state machine characterizing data. If the electronic circuit unit ES has, for example, ten state machines, this means that in the exemplary embodiment described, the ten state machines each have an observation output for outputting the bit sequence that characterizes their respective activated state transition and an eleventh, jointly used further observation output for outputting the has respective state of at least one state machine characterizing data. Since the state of a state machine characterizing data typically consist of about 4 to 6 bits per state machine, however, would be at a complete provision of the state of the state machine ZM indicative data at each clock for monitoring the state machines a total of about 50 observation outputs required , The electronic circuit unit ES according to the invention or the use of the method according to the invention thus make it possible to reduce the number of required monitoring outputs to approximately one fifth of this value. Since the number of available outputs of an electronic circuit unit ES is usually limited, for example, for cost and design reasons, only in this case is it possible in most cases to monitor the sequence of the state machine ZM.

FIG. 2 shows a detail of a further exemplary embodiment of the electronic circuit unit according to the invention in a circuit diagram. In this case, a first memory unit SP1 and a second memory unit SP2 are shown, wherein a first bit B1 is applied to the first memory unit SP1 and a second bit B2 to the second memory unit SP2. In order to be able to output both the content of the first memory unit SP1, ie Bl, and the content of the second memory unit SP2, ie B2, to a common observation output A, the content of the first memory unit SP1 advantageously becomes at a rising edge a clock signal TS and the content of the second memory SP2 output at a falling edge of the clock signal TS via the observation output A. Thus, advantageously per clock signal TS per observation output A, information of the length 2 bits can be output. Since state machines usually make state changes only with increasing or only falling clock edges, all state transitions, for example the state transitions ST1, ST2, ST3, ST4 shown in FIG. 1, can thus be output via the one observation output A.

FIG. 3 shows a schematic representation of the structure of data used in an exemplary embodiment of the method according to the invention, which characterizes the respective state of the at least one state machine. Usually, due to limited storage capacity, it will not be possible to record any number of state transitions. In addition, a regular post-processing of the issued state transition to determine the resulting from the state machine for each condition is usually too expensive. For this reason, it is advantageous if, at least at regular time intervals, the respective state of the at least one state machine characterizing data, for example in the form of a state vector, is output via at least one further observation output. This is preferably done for all the state machines of the electronic circuit unit ei ^¬ NEN single further observation output. For outputting the data characterizing the state of the at least one state machine in serial form via the at least one further observation output, for example, a protocol can be defined which specifies the data format shown in FIG. In this case, the data characterizing the respective state of the at least one state machine consist of blocks of the same size whose length is larger by one bit than the size of the state vector of the state machine, which can occupy the largest number of different states.

In the exemplary embodiment of FIG. 3 it is assumed that the first data block HB contains only bits with the value 1 in the form of a "header field" and thus defines the start time or the start of the data characterizing the respective state of the at least one state machine Blocks DAT _FSM i, DAT _FSM2 , DAT _FSM 3r DATFSMn contain the data characterizing the respective state of the n state machines of the electronic circuit unit ES

Block DATFSMi, DAT _FS M2, DAT _FSM3 , DAT _FSMn are assigned the value 0 to distinguish the corresponding blocks DATFSMi, DAT _FS M2, DAT _FS M3, DATFSMΠ from the first data block HB. For an accelerated output of the data of preferably only one further observation output shown in FIG. 3, which characterizes the respective state of the at least one state machine, advantageously the circuit shown in FIG. 2 can again be used, in which both the rising and the falling edge of the Clock signal is used for output.

If the state machines of the electronic circuit unit are operated with clocks that are asynchronous with respect to one another, then advantageously for each of these asynchronous clocks te, ie for each of the so-called clock worlds, a separate further observation output for outputting the respective state of the state machines of the respective clock world characterizing data are provided.

Advantageously, the number of observation outputs required for monitoring or observing the state machines of an electronic circuit unit is thus considerably reduced, preferably to one observation output per state machine, within the scope of the above-described exemplary embodiments of the present invention.

Claims

claims

1. Electronic circuit unit (ES) with at least one state machine (ZM) with states (Sl, S2, S3, S4), each of which allow at least one state transition (STl, ST2, ST3, ST4), characterized in that the electronic circuit unit (ES) for each of the state machines (ZM) in each case - has at least one observation output (A) and

- For outputting a respective activated state transition (for example, ST2) characterizing bit sequence on the at least one observation output (A) is formed.

2. Electronic circuit unit according to claim 1, characterized in that a

- The electronic circuit unit (ES) in a bit sequence with multiple bits for each of the state machines (ZM) each having a number of bits corresponding number of storage units (SPL, SP2) and

- The electronic circuit unit (ES) is designed such that the content (eg Bl) of at least one of the memory units (SPl) at a rising edge of a clock signal (TS) and the content (B2) of at least one other of the memory units (SP2) at a falling edge of the clock signal (TS) via the at least one observation output (A) is output.

3. Electronic circuit unit according to claim 2, characterized in that the memory units (SPL, SP2) for each of the state machines (ZM) are each connected by means of a multiplexer (MUX) with the at least one observation output (A).

4. Electronic circuit unit according to claim 2 or 3, characterized in that the memory units (SP1, SP2) are each designed as flip-flops.

5. Electronic circuit unit according to one of the preceding claims, characterized in that it is for outputting from the respective state of the at least one state machine (ZM) characterizing data (DATF _S MI,

DAT _F SM2Γ DAT _FS M _{3 /} DATF _S MΠ) has at least one further observation output.

6. A method for operating an electronic circuit unit (ES) with at least one state machine (ZM) with

States (S1, S2, S3, S4), which in each case allow at least one state transition (ST1, ST2, ST3, ST4), characterized in that for each of the state machines (ZM) one each the respective state transition (eg ST2) characterizing bit sequence via one of the respective state machine (ZM) associated observation output (A) of the electronic circuit unit (ES) is output.

7. The method according to claim 6, characterized in that in a bit sequence with a plurality of bits and an electronic circuit unit (ES), for each of the state machines (ZM) one of the number of bits corresponding number of storage units (SPL, SP2), the content (eg Bl) to ^{¬ at} least one of the memory units (SPL) at a rising edge of a clock signal (TS) and the content of at least one other of the memory units (SP2) in a falling Edge of the clock signal (TS) via the respective observation output (A) is output.

8. The method according to claim 7, characterized in that the content (Bl, B2) of the memory units (SPL, SP2) for each of the state machines (ZM) each by means of a multiplexer (MUX) on the at least one of the respective state machine (ZM) associated observation Output (A) is output.

9. Method according to claim 1 or 8, characterized in that flip-flops are used as memory units (SP1, SP2).

10. The method according to any one of claims 6 to 9, characterized in that the respective state of the at least one state machine (ZM) characterizing data (DAT _FSM i, DAT _FSM 2, DAT _FSM 3, DAT _FS Mn) over at least one further observation Output are output.