WO2008147113A2 - High efficiency solar cell, method of fabricating the same and apparatus for fabricating the same - Google Patents

High efficiency solar cell, method of fabricating the same and apparatus for fabricating the same Download PDF

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Publication number
WO2008147113A2
WO2008147113A2 PCT/KR2008/002999 KR2008002999W WO2008147113A2 WO 2008147113 A2 WO2008147113 A2 WO 2008147113A2 KR 2008002999 W KR2008002999 W KR 2008002999W WO 2008147113 A2 WO2008147113 A2 WO 2008147113A2
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Prior art keywords
semiconductor layer
intrinsic semiconductor
impurity
process chamber
intrinsic
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PCT/KR2008/002999
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French (fr)
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WO2008147113A3 (en
Inventor
Jae Ho Kim
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Jusung Engineering Co Ltd
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Jusung Engineering Co Ltd
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Priority to US12/597,497 priority Critical patent/US20100132791A1/en
Priority to CN2008800178717A priority patent/CN101681945B/en
Publication of WO2008147113A2 publication Critical patent/WO2008147113A2/en
Publication of WO2008147113A3 publication Critical patent/WO2008147113A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/164—Polycrystalline semiconductors
    • H10F77/1642—Polycrystalline semiconductors including only Group IV materials
    • H10F77/1645—Polycrystalline semiconductors including only Group IV materials including microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/166—Amorphous semiconductors
    • H10F77/1662—Amorphous semiconductors including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/244—Electrodes made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell, and more particularly, to a high efficiency solar cell including an intrinsic semiconductor layer of gradually varying crys- tallinity, a method of fabricating the solar cell and an apparatus for fabricating the solar cell.
  • Solar cells generate an electromotive force from diffusion of minority carriers, which are excited by sunlight, in P-N (positive-negative) junction layer.
  • P-N positive-negative
  • Single crystalline silicon, poljcrystalline silicon, amorphous silicon or compound semiconductor may be used for the solar cells.
  • FIG. 1 is a cross-sectional view of an amorphous silicon thin film type solar cell according to the related art.
  • a front electrode 12, a semiconductor layer 13 and a rear electrode 14 are sequentially formed on a substrate 11.
  • the transparent substrate 11 includes glass or plastic.
  • the front electrode 12 includes a transparent conductive oxide (TCO) material for transmission of incident light from the transparent substrate 11.
  • the semiconductor layer 13 includes amorphous silicon (a-Si:H).
  • the semicondvctor layer 13 includes a p-type semiconductor layer 13a, an intrinsic semicondvctor layer 13b and an n-type semiconductor layer 13c sequentially on the front electrode 12, which form a PIN (positive-intrinsic- negative) junction layer.
  • the intrinsic semiconductor layer 13b which may be referred to as an active layer, functions as a light absorption layer increasing efficiency of the thin film type solar cell.
  • the rear electrode 14 includes a TCO material or a metallic material such as aluminum (Al), copper (Cu) and silver (Ag).
  • the amorphous silicon thin film type solar cell has a relatively low energy- converting efficiency as compared with a single crystalline silicon solar cell or a poly- crystalline silicon solar cell.
  • the efficiency is further reduced according to a property-deterioration phenomenon, which is referred to as Staebler- Wronski effect.
  • micro-crystalline silicon as an intermediate material between amorphous silicon and single crystalline silicon has a grain size of several tens nano meters (nm) to several hundreds nm.
  • the microcrystalline silicon does not have a property-deterioration phenomenon of amorphous silicon.
  • the intrinsic semiconductor layer of microcrystalline silicon has a thickness of about
  • amorphous silicon 1 ⁇ m to about 3 ⁇ m because of lower absorption coefficient of light, while the intrinsic semiconductor layer of amorphous silicon has a thickness of about 200 nm to about 500nm.
  • a deposition rate of microcrystalline silicon is lower than a deposition rate of amorphous silicon layer, thicker microcrystalline silicon is much lower productivity than thinner amorphous silicon.
  • a band gap of amorphous silicon is about 1.7 eV to about 1.8 eV, while a band gap of microcrystalline silicon is about 1.1 eV, which is the same as a band gap of single crystalline silicon. Accordingly, amorphous silicon and microcrystalline silicon have difference in light absorption property. As a result, amorphous silicon absorbs light having a wavelength mostly of about 350 nm to about 800 nm, while microcrystalline silicon absorbs light having a wavelength mostly of about 350 nm to about 1200nm.
  • a solar cell of a tandem (double) structure or a triple structure where PIN junction layers of amorphous silicon and microcrystalline silicon are se- quentially formed has been widely used on the basis of the difference in light absorption property between amorphous silicon and microcrystalline silicon.
  • a first PIN junction layer of amorphous silicon that absorbs light mostly in a shorter wavelength band is formed on a transparent substrate onto which sunlight is irradiated and a second PIN junction layer of microcrystalline silicon that absorbs light mostly in a longer wavelength band is formed on the first PIN junction layer of amorphous silicon
  • light absorption of the first and second PIN junction layers is improved, thereby improving energy-converting efficiency. Disclosure of Invention Technical Problem
  • the solar cell of a tandem structure or a triple structure has advantages in energy -converting efficiency as compared with a solar cell of a single stricture of amorphous silicon or microcrystalline silicon, the solar cell of a tandem structure or a triple structure still has a relatively complicated fabrication process. Moreover, since the fabrication process for the solar cell of a tandem structure or a triple structure includes a deposition step of microcrystalline silicon, there exists a limitation in improvement of productivity.
  • the present invention is directed to a solar cell, a method of fabricating the solar cell and an apparatus for the solar cell that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
  • An object of the present invention is to provide a high efficiency solar cell having a simplified fabrication process and an improved productivity, a method of fabricating the solar cell and an apparatus for the solar cell.
  • Another object of the present invention is to provide a high efficiency solar cell using microcrystalline silicon and amorphous silicon as a light absorbing layer, a method of fabricating the solar cell and an apparatus for the solar cell.
  • a method of fabricating a high efficiency solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
  • a high efficiency solar cell includes: a transparent substrate; a first electrode on the transparent substrate; a first impurity-doped semiconductor layer on the first electrode; an intrinsic semiconductor layer on the first impurity-doped semiconductor layer, the intrinsic semiconductor layer having a gradually varying crys- tallinity; a second impurity-doped semiconductor layer on the intrinsic semiconductor layer; and a second electrode on the second impurity-doped semiconductor layer.
  • an apparatus for fabricating a solar includes: a transfer chamber including a transfer means for transferring a substrate; a load lock chamber coupled with a first side portion of the transfer chamber, the load lock chamber alternately having a vacuum state and an atmospheric pressure state for inputting and outputting the substrate; a first process chamber coupled with a second side portion of the transfer chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a third side portion of the transfer chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a fourth side portion of the transfer chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and a fourth process chamber coupled with a fifth side portion of the transfer chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer.
  • an apparatus for fabricating a solar includes: a loading chamber alternately having a vacuum state and an atmospheric pressure state for inputting a substrate; a first process chamber coupled with a side portion of the loading chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a side portion of the first process chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a side portion of the second process chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; a fourth process chamber coupled with a side portion of the third process chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer; and an unloading chamber coupled with a side portion of the fourth process chamber, the unloading chamber alternately having a vacuum state and an atmospheric pressure state for outputting the substrate.
  • a method of fabricating a solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a light absorbing layer on the first impurity-doped semiconductor layer; heating the light absorbing layer; and sequentially forming a second impurity- doped semiconductor layer and a second electrode on the light absorbing layer.
  • a method of fabricating a solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; crystallizing the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
  • a high efficiency solar cell since an intrinsic semiconductor layer of linearly crystallized silicon used as a light absorbing layer includes amorphous silicon and microcrystalline silicon, light absorption band is broaden and energy-converting efficiency is improved.
  • a separate step of forming a microcrystalline silicon layer that has a relatively low deposition rate is omitted, a fabrication process for a high efficiency solar cell according to an embodiment of the present invention is simplified as compared with a fabrication process for a tandem structure solar cell or a triple stricture solar cell. As a result, productivity is improved.
  • FIG. 1 is a cross-sectional view of an amorphous silicon thin film type solar cell according to the related art
  • FIG. 2 is a flow chart showing a fabrication process of a solar cell according to an embodiment of the present invention
  • FIGs. 3 to 7 are cross-sectional views showing a fabrication process of a solar cell according to an embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a RTP for a solar cell according to another embodiment of the present invention.
  • FIG. 9 is a plan views showing a cluster type apparatus for a solar cell according to an embodiment of the present invention.
  • FIG. 10 is a plan views showing an in-line type apparatus for a solar cell according to an embodiment of the present invention. Mode for the Invention
  • FIG. 2 is a flow chart showing a fabrication process of a solar cell according to an embodiment of the present invention
  • FIGs. 3 to 7 are cross-sectional views showing a fabrication process of a solar cell according to an embodiment of the present invention.
  • a transparent substrate 110 is provided, and a front electrode 120 (i.e., a first electrode) and a p-type semiconductor layer (i.e., a first impurity-doped semiconductor layer) of amorphous silicon 130 are sequentially formed on the transparent substrate 1 IQ
  • the front electrode 120 includes a transparent conductive oxide (TCO) material for transmission of incident light from the transparent substrate 1 IQ
  • TCO transparent conductive oxide
  • the front electrode 120 may have a thickness of about 700 nm to about 2000 nm.
  • the p-type semiconductor layer 130 of amorphous silicon may have a thickness of about 30 nm.
  • the p-type semiconductor layer 130 of amorphous silicon may be formed by a plasma enhanced chemical vapor deposition (PECVD) method using SiH 4 , H 2 , B 2 H 6 and CH 4 .
  • PECVD plasma enhanced chemical vapor deposition
  • a first intrinsic semiconductor layer 140 of amorphous silicon is formed on the p-type semiconductor layer 130 of amorphous silicon.
  • the first intrinsic semiconductor layer 140 of amorphous silicon functions as a light absorbing layer and may have a thickness of about 1/M to about 3 /M.
  • the first intrinsic semiconductor layer 140 of amorphous silicon may be formed by a PECVD method using SiH 4 and H 2 .
  • a buffer layer may be formed between the p-type semiconductor layer 130 and the first intrinsic semiconductor layer 140 in order to eliminate interface defects and adjust band gap levels.
  • the buffer layer may include a thin layer of microcrystalline silicon or amorphous silicon.
  • a rapid thermal process is performed for the first intrinsic semiconductor layer 140 of amorphous silicon.
  • the first intrinsic semiconductor layer 140 of amorphous silicon is heated up to about 500 0 C to about 6D0 0 C for a predetermined time period under a hydrogen (H 2 ) ambient using a heating means such as a xenon (Xe) lamp or a halogen lamp applying heat optically.
  • the predetermined time period for heating may be within a range of several minutes to several tens minutes.
  • the first intrinsic semiconductor layer of amorphous silicon is not completely crystallized by the RTP. Instead, the first intrinsic semiconductor layer 140 of amorphous silicon is heated such that about 30 % to about 40 % of the whole amorphous silicon of the first intrinsic semiconductor layer 140 is crystallized by the RTP.
  • the first intrinsic semiconductor layer 140 of amorphous silicon is crystallized by the RTP to form a second intrinsic semiconductor layer 150 of linearly crystallized silicon.
  • the second intrinsic semiconductor layer 150 has a gradually varying crystallinity along a vertical direction perpendicular to the transparent substrate 1 IQ Accordingly, a portion of the second intrinsic semiconductor layer 150 closer to the heating means has higher crystallinity than a portion of the second intrinsic semiconductor layer 150 farther from the heating means.
  • the crystallinity of the second intrinsic semiconductor layer 150 is proportional to a distance from a bottom surface of the second intrinsic semiconductor layer 15Q
  • the crystallinity of the second intrinsic semiconductor layer 150 may linearly increase along a direction from a bottom surface adjacent to the transparent substrate 110 to a top surface adjacent to the heating means.
  • the second intrinsic semiconductor layer 150 of linearly crystallized silicon has a linearly increasing crystallinity from the bottom surface contacting the p-type semiconductor layer 130 to the top surface adjacent to the heating means.
  • a portion near the bottom surface contacting the p-type semiconductor layer 130 may have amorphous silicon and a portion near the top surface adjacent to the heating means may have micro- crystalline silicon.
  • the second intrinsic semiconductor layer 150 may be classified into first to n" 1 very thin layers Ll to Ln having first to n" 1 crystallinities Xc(I) to Xc(n), respectively.
  • the first to nth crystallinities Xc(I) to Xc(n) satisfy a following equation 1.
  • n" 1 band gap Bg(n) is a band gap of macrocrystalline silicon having about
  • the first band gap Bg(I) is a band gap of amorphous silicon within a range of about 1.7 eV to about 1.8eV.
  • the solar cell a ⁇ jording to an embodiment of the present invention does not include PIN junction layers of amorphous silicon and PIN junction layers of micro- crystalline silicon of a tandem structure or a triple structure as an absorption layer
  • the light absorption band of the solar cell is broadened to cover a range from a shorter wavelength band to a longer wavelength band because the second intrinsic semiconductor layer has a continuous distribution of crystallinity, e.g., from amorphous silicon to microcrystalline silicon.
  • FIG. 8 is a cross-sectional view showing a RTP for a solar cell a ⁇ jording to another embodiment of the present invention.
  • a metal layer 190 is formed on the first intrinsic semiconductor layer 140 of amorphous silicon for reducing a temperature of an RTP and increasing a speed of crystallization.
  • the metal layer 190 may include at least one of nickel (Ni), aluminum (Al) and palladium (Pd).
  • the RTP is performed for the metal layer 190 and the first intrinsic semiconductor layer 140 of amorphous silicon using a heating means such as a xenon (Xe) lamp or a halogen lamp applying heat optically. While the RTP is performed, metallic materials of the metal layer 190 are diffused into the first intrinsic semiconductor layer 140 to form a metal silidde.
  • the first intrinsic semiconductor layer 140 is crystallized under a relatively low temperature of about 350 0 C to about 450 0 C to form a second intrinsic semiconductor layer of linearly crystallized silicon.
  • the first intrinsic semiconductor layer 140 is crystallized by the RTP for a relatively shorter predetermined time period due to function of the metal silidde, the speed of crystallization increases. Spedfically, the RTP with a metal layer may be advantageously applied to a fabrication method for a solar cell including a transparent substrate of plastic having a relatively low heat resistance. After the RTP, the metal layer may remain and be used as a portion of electrode, or may be removed from the second intrinsic semiconductor layer.
  • an n-type semiconductor layer (i.e., second impurity- doped semiconductor layer) of amorphous silicon and a rear electrode 170 (i.e., second electrode) are sequentially formed on the second intrinsic semiconductor layer 150 of linearly crystallized silicon.
  • the n-type semiconductor layer 160 of amorphous silicon may have a thickness of about 50 nm.
  • the n-type semiconductor layer 160 of amorphous silicon may be formed by a PECVD method using SiH 4 , H 2 and PH 3 .
  • the rear electrode 170 may include a TCO material or one of aluminum (Al), copper (Cu) and silver (Ag).
  • the second intrinsic semiconductor layer 150 of linearly crystallized silicon absorbs the sunlight through the p-type semiconductor layer 13Q Since a portion of the second intrinsic semiconductor layer 150 adjacent to an interface with the p-type semiconductor layer 130 has a lower crystallinity, i.e., a higher ratio of amorphous silicon, the portion of the second intrinsic semiconductor layer 150 adjacent to the interface with the p-type semiconductor layer 133 absorbs the sunlight mostly corresponding to a shorter wavelength band.
  • the portion of the second intrinsic semiconductor layer 150 adjacent to an interface with the n-type semiconductor layer 163 has a higher crystallinity, i.e., a higher ratio of mi- crocrystalline silicon, the portion of the second intrinsic semiconductor layer 150 adjacent to the interface with the n-type semiconductor layer 163 absorbs the sunlight mostly corresponding to a longer wavelength band. Accordingly, light absorption and energy -converting efficiency of the solar cell according to an embodiment of the present invention are improved.
  • FIGs. 5 and 6 are plan views showing a cluster type apparatus and an in-line type apparatus, respectively, for a solar cell according to an embodiment of the present invention.
  • a cluster type apparatus 200 for a solar cell includes a transfer chamber
  • the transfer chamber 210 may include a transfer means such as a robot (not shown) therein to transfer a substrate between chambers.
  • the transfer chamber 210 maintains a vacuum state during the fabrication process of the solar cell.
  • the load lock chamber 220 is used as a buffer space for transferring a substrate between the transfer chamber 210 under a vacuum state and an exterior under an atmospheric pressure state. Accordingly, the load lock chamber 220 alternately has a vacuum state and an atmospheric pressure state.
  • the first to fourth process chambers 230 to 263 are coupled with side portions of the transfer chamber 21Q
  • the p-type semiconductor layer 130 (of FIG. 3) is formed on the transparent substrate 110 (of FIG. 3) in the first process chamber 230, and the first intrinsic semiconductor layer 140 (of FIG. 4) of amorphous silicon is formed on the p-type semiconductor layer 130 in the second process chamber 24Q
  • the first intrinsic semiconductor layer 140 is crystallized by the RTP to become the second intrinsic semiconductor layer 150 (of FIG. 6) of linearly crystallized silicon in the third process chamber 250
  • the n-type semiconductor layer 160 (of FIG. 7) is formed on the second intrinsic semiconductor layer 150 in the fourth process chamber 263
  • a slot valve 270 selectively opening and closing a substrate path is disposed between the transfer chamber 210 and each of the load lock chamber 220 and the first to fourth process chambers 230 to 263
  • the load lock chamber 220 is evacuated to have a vacuum state predetermined pressure.
  • the slot valve 270 between the load lock chamber 220 and the transfer chamber 210 is opened and the transparent substrate 110 is transferred from the load lock chamber 220 to the first process chamber 230 through the transfer chamber 210 by the transfer robot.
  • the p- type semiconductor layer 130 is formed on the front electrode 12Q
  • the first intrinsic semiconductor layer 140 is formed on the p-type semiconductor layer 130 after the transparent substrate 110 is transferred to the second process chamber 240, and the first intrinsic semiconductor layer 140 is crystallized to become the second intrinsic semiconductor layer 150 after the transparent substrate 110 is transferred to the third process chamber 250
  • the n-type semiconductor layer 163 is formed on the second intrinsic semiconductor layer 150 after the transparent substrate 110 is transferred to the fourth process chamber 263
  • the transparent substrate 110 is transferred from the fourth process chamber 263 to the load lock chamber 220 through the transfer chamber 210, and the transparent substrate 110 having the front electrode 120, the p-type semiconductor layer 133, the second intrinsic semiconductor layer 150 and the n-type semiconductor layer 163 thereon is outputted from the load lock chamber 22Q
  • an in-line type apparatus 300 for a solar cell includes a loading chamber
  • the loading chamber 310, the first to fourth process chambers 320 to 350 and an unloading chamber 360 are serially coupled with each other.
  • a substrate is inputted into the loading chamber 310 and outputted from the unloading chamber 363
  • Each of the loading chamber 310, the first to fourth process chambers 320 to 350 and the unloading chamber 360 includes an in-line type transferring means such as a roller or a linear motor to transfer a substrate.
  • the first to fourth process chambers 320 to 350 maintains a vacuum state during the fabrication process of the solar cell. Since a substrate is transferred between an exterior under an atmospheric pressure state and each of the first and fourth process chambers 320 and 350, each of the loading chamber 310 and the unloading chamber 363 alternately has a vacuum state and an atmospheric pressure state.
  • FIG. 3 thereon is transferred to the first process chamber 320, the p-type semiconductor layer 130 (of FIG. 3) is formed on the front electrode 12Q
  • the first intrinsic semiconductor layer 140 (of FIG. 4) is formed on the p-type semiconductor layer 130 after the transparent substrate 110 is transferred to the second process chamber 330, and the first intrinsic semiconductor layer 140 is crystallized to become the second intrinsic semiconductor layer 150 (of FIG. 6) after the transparent substrate 110 is transferred to the third process chamber 34Q
  • the n-type semiconductor layer 160 (of FIG.
  • the rear electrode 170 (of FIG. 7) may be formed on the n-type semiconductor layer 160 in another apparatus such as a sputter.

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Abstract

A method of fabricating a solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.

Description

Description
HIGH EFFICIENCY SOLAR CELL, METHOD OF FABRICATING THE SAME AND APPARATUS FOR FABRICATING
THE SAME
Technical Field
[1] The present invention relates to a solar cell, and more particularly, to a high efficiency solar cell including an intrinsic semiconductor layer of gradually varying crys- tallinity, a method of fabricating the solar cell and an apparatus for fabricating the solar cell. Background Art
[2] As concerns about clean energy such as solar power for coping with exhaust of fossil resources and environmental pollution increase, a solar cell generating an electromotive force using sunlight has been the subject of recent research.
[3] Solar cells generate an electromotive force from diffusion of minority carriers, which are excited by sunlight, in P-N (positive-negative) junction layer. Single crystalline silicon, poljcrystalline silicon, amorphous silicon or compound semiconductor may be used for the solar cells.
[4] Although solar cells using single crystalline silicon or poljcrystalline silicon have a relatively high energy -converting efficiency, solar cells using single crystalline silicon or poljcrystalline silicon have a relatively high material cost and a relatively complicated fabrication process. Accordingly, a thin film type solar cell using amorphous silicon or compound semiconductor on a cheap substrate such as glass or plastic has been widely researched and developed. Specifically, a thin film type solar cell has advantages in a large-sized substrate and a flexible substrate so that a flexible large-sized solar cell can be produced.
[5] FIG. 1 is a cross-sectional view of an amorphous silicon thin film type solar cell according to the related art. In FIG. 1, a front electrode 12, a semiconductor layer 13 and a rear electrode 14 are sequentially formed on a substrate 11. The transparent substrate 11 includes glass or plastic. The front electrode 12 includes a transparent conductive oxide (TCO) material for transmission of incident light from the transparent substrate 11. The semiconductor layer 13 includes amorphous silicon (a-Si:H). In addition, the semicondvctor layer 13 includes a p-type semiconductor layer 13a, an intrinsic semicondvctor layer 13b and an n-type semiconductor layer 13c sequentially on the front electrode 12, which form a PIN (positive-intrinsic- negative) junction layer. The intrinsic semiconductor layer 13b, which may be referred to as an active layer, functions as a light absorption layer increasing efficiency of the thin film type solar cell. The rear electrode 14 includes a TCO material or a metallic material such as aluminum (Al), copper (Cu) and silver (Ag).
[6] When sunlight is irradiated onto the transparent substrate 11, minority carriers diffusing across the PIN junction layer of the semiconductor layer 13 on the transparent substrate 11 generate a voltage difference between the front electrode 12 and the rear electrode 14, thereby generating an electromotive force.
[7] The amorphous silicon thin film type solar cell has a relatively low energy- converting efficiency as compared with a single crystalline silicon solar cell or a poly- crystalline silicon solar cell. In addition, as the amorphous silicon thin film type solar cell is exposed to light for a longer time period, the efficiency is further reduced according to a property-deterioration phenomenon, which is referred to as Staebler- Wronski effect.
[8] To solve the above problems, a thin film type solar cell using microcrystalline silicon
(μc-Si:H or mc-Si:H) instead of amorphous silicon has been suggested. The micro- crystalline silicon as an intermediate material between amorphous silicon and single crystalline silicon has a grain size of several tens nano meters (nm) to several hundreds nm. In addition, the microcrystalline silicon does not have a property-deterioration phenomenon of amorphous silicon.
[9] The intrinsic semiconductor layer of microcrystalline silicon has a thickness of about
1 μm to about 3 μm because of lower absorption coefficient of light, while the intrinsic semiconductor layer of amorphous silicon has a thickness of about 200 nm to about 500nm. In addition, since a deposition rate of microcrystalline silicon is lower than a deposition rate of amorphous silicon layer, thicker microcrystalline silicon is much lower productivity than thinner amorphous silicon.
[10] Furthermore, a band gap of amorphous silicon is about 1.7 eV to about 1.8 eV, while a band gap of microcrystalline silicon is about 1.1 eV, which is the same as a band gap of single crystalline silicon. Accordingly, amorphous silicon and microcrystalline silicon have difference in light absorption property. As a result, amorphous silicon absorbs light having a wavelength mostly of about 350 nm to about 800 nm, while microcrystalline silicon absorbs light having a wavelength mostly of about 350 nm to about 1200nm. Recently, a solar cell of a tandem (double) structure or a triple structure where PIN junction layers of amorphous silicon and microcrystalline silicon are se- quentially formed has been widely used on the basis of the difference in light absorption property between amorphous silicon and microcrystalline silicon. For example, when a first PIN junction layer of amorphous silicon that absorbs light mostly in a shorter wavelength band is formed on a transparent substrate onto which sunlight is irradiated and a second PIN junction layer of microcrystalline silicon that absorbs light mostly in a longer wavelength band is formed on the first PIN junction layer of amorphous silicon, light absorption of the first and second PIN junction layers is improved, thereby improving energy-converting efficiency. Disclosure of Invention Technical Problem
[11] Although the solar cell of a tandem structure or a triple structure has advantages in energy -converting efficiency as compared with a solar cell of a single stricture of amorphous silicon or microcrystalline silicon, the solar cell of a tandem structure or a triple structure still has a relatively complicated fabrication process. Moreover, since the fabrication process for the solar cell of a tandem structure or a triple structure includes a deposition step of microcrystalline silicon, there exists a limitation in improvement of productivity. Technical Solution
[12] Accordingly, the present invention is directed to a solar cell, a method of fabricating the solar cell and an apparatus for the solar cell that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
[13] An object of the present invention is to provide a high efficiency solar cell having a simplified fabrication process and an improved productivity, a method of fabricating the solar cell and an apparatus for the solar cell.
[14] Another object of the present invention is to provide a high efficiency solar cell using microcrystalline silicon and amorphous silicon as a light absorbing layer, a method of fabricating the solar cell and an apparatus for the solar cell.
[15] A method of fabricating a high efficiency solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
[16] In another aspect, a high efficiency solar cell includes: a transparent substrate; a first electrode on the transparent substrate; a first impurity-doped semiconductor layer on the first electrode; an intrinsic semiconductor layer on the first impurity-doped semiconductor layer, the intrinsic semiconductor layer having a gradually varying crys- tallinity; a second impurity-doped semiconductor layer on the intrinsic semiconductor layer; and a second electrode on the second impurity-doped semiconductor layer.
[17] In another aspect, an apparatus for fabricating a solar includes: a transfer chamber including a transfer means for transferring a substrate; a load lock chamber coupled with a first side portion of the transfer chamber, the load lock chamber alternately having a vacuum state and an atmospheric pressure state for inputting and outputting the substrate; a first process chamber coupled with a second side portion of the transfer chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a third side portion of the transfer chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a fourth side portion of the transfer chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and a fourth process chamber coupled with a fifth side portion of the transfer chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer.
[18] In another aspect, an apparatus for fabricating a solar includes: a loading chamber alternately having a vacuum state and an atmospheric pressure state for inputting a substrate; a first process chamber coupled with a side portion of the loading chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a side portion of the first process chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a side portion of the second process chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; a fourth process chamber coupled with a side portion of the third process chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer; and an unloading chamber coupled with a side portion of the fourth process chamber, the unloading chamber alternately having a vacuum state and an atmospheric pressure state for outputting the substrate. [19] In another aspect, a method of fabricating a solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a light absorbing layer on the first impurity-doped semiconductor layer; heating the light absorbing layer; and sequentially forming a second impurity- doped semiconductor layer and a second electrode on the light absorbing layer.
[20] In another aspect, a method of fabricating a solar cell includes: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; crystallizing the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
Advantageous Effects
[21] In a high efficiency solar cell according to an embodiment of the present invention, since an intrinsic semiconductor layer of linearly crystallized silicon used as a light absorbing layer includes amorphous silicon and microcrystalline silicon, light absorption band is broaden and energy-converting efficiency is improved. In addition, since a separate step of forming a microcrystalline silicon layer that has a relatively low deposition rate is omitted, a fabrication process for a high efficiency solar cell according to an embodiment of the present invention is simplified as compared with a fabrication process for a tandem structure solar cell or a triple stricture solar cell. As a result, productivity is improved. Brief Description of the Drawings
[22] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention.
[23] FIG. 1 is a cross-sectional view of an amorphous silicon thin film type solar cell according to the related art
[24] FIG. 2 is a flow chart showing a fabrication process of a solar cell according to an embodiment of the present invention;
[25] FIGs. 3 to 7 are cross-sectional views showing a fabrication process of a solar cell according to an embodiment of the present invention;
[26] FIG. 8 is a cross-sectional view showing a RTP for a solar cell according to another embodiment of the present invention; [27] FIG. 9 is a plan views showing a cluster type apparatus for a solar cell according to an embodiment of the present invention; and
[28] FIG. 10 is a plan views showing an in-line type apparatus for a solar cell according to an embodiment of the present invention. Mode for the Invention
[29] Reference will now be made in detail to embodiments which are illustrated in the accompanying drawings. Wherever possible, similar reference numbers will be used to refer to the same or similar parts.
[30] FIG. 2 is a flow chart showing a fabrication process of a solar cell according to an embodiment of the present invention, and FIGs. 3 to 7 are cross-sectional views showing a fabrication process of a solar cell according to an embodiment of the present invention.
[31] At steps of STl 1 and ST 12 and in FIG. 3, a transparent substrate 110 is provided, and a front electrode 120 (i.e., a first electrode) and a p-type semiconductor layer (i.e., a first impurity-doped semiconductor layer) of amorphous silicon 130 are sequentially formed on the transparent substrate 1 IQ The front electrode 120 includes a transparent conductive oxide (TCO) material for transmission of incident light from the transparent substrate 1 IQ For example, the front electrode 120 may have a thickness of about 700 nm to about 2000 nm. The p-type semiconductor layer 130 of amorphous silicon may have a thickness of about 30 nm. For example, the p-type semiconductor layer 130 of amorphous silicon may be formed by a plasma enhanced chemical vapor deposition (PECVD) method using SiH4, H2, B2H6 and CH4.
[32] At step of ST 13 and in FIG. 4, a first intrinsic semiconductor layer 140 of amorphous silicon is formed on the p-type semiconductor layer 130 of amorphous silicon. The first intrinsic semiconductor layer 140 of amorphous silicon functions as a light absorbing layer and may have a thickness of about 1/M to about 3 /M. For example, the first intrinsic semiconductor layer 140 of amorphous silicon may be formed by a PECVD method using SiH4 and H2.
[33] Although not shown at step of ST 13 and in FIG. 4, a buffer layer may be formed between the p-type semiconductor layer 130 and the first intrinsic semiconductor layer 140 in order to eliminate interface defects and adjust band gap levels. For example, the buffer layer may include a thin layer of microcrystalline silicon or amorphous silicon.
[34] At step of ST 14 and in FIG. 5, a rapid thermal process (RTP) is performed for the first intrinsic semiconductor layer 140 of amorphous silicon. For example, after the transparent substrate 110 including the first intrinsic semiconductor layer 140 of amorphous silicon is transferred into a heating chamber, the first intrinsic semiconductor layer 140 of amorphous silicon is heated up to about 500 0C to about 6D0 0C for a predetermined time period under a hydrogen (H2) ambient using a heating means such as a xenon (Xe) lamp or a halogen lamp applying heat optically. The predetermined time period for heating may be within a range of several minutes to several tens minutes. The first intrinsic semiconductor layer of amorphous silicon is not completely crystallized by the RTP. Instead, the first intrinsic semiconductor layer 140 of amorphous silicon is heated such that about 30 % to about 40 % of the whole amorphous silicon of the first intrinsic semiconductor layer 140 is crystallized by the RTP.
[35] At step of ST 15 and in FIG. 6, the first intrinsic semiconductor layer 140 of amorphous silicon is crystallized by the RTP to form a second intrinsic semiconductor layer 150 of linearly crystallized silicon. The second intrinsic semiconductor layer 150 has a gradually varying crystallinity along a vertical direction perpendicular to the transparent substrate 1 IQ Accordingly, a portion of the second intrinsic semiconductor layer 150 closer to the heating means has higher crystallinity than a portion of the second intrinsic semiconductor layer 150 farther from the heating means. As a result, the crystallinity of the second intrinsic semiconductor layer 150 is proportional to a distance from a bottom surface of the second intrinsic semiconductor layer 15Q For example, the crystallinity of the second intrinsic semiconductor layer 150 may linearly increase along a direction from a bottom surface adjacent to the transparent substrate 110 to a top surface adjacent to the heating means. As a result, the second intrinsic semiconductor layer 150 of linearly crystallized silicon has a linearly increasing crystallinity from the bottom surface contacting the p-type semiconductor layer 130 to the top surface adjacent to the heating means. For example, a portion near the bottom surface contacting the p-type semiconductor layer 130 may have amorphous silicon and a portion near the top surface adjacent to the heating means may have micro- crystalline silicon.
[36] For illustration, the second intrinsic semiconductor layer 150 may be classified into first to n"1 very thin layers Ll to Ln having first to n"1 crystallinities Xc(I) to Xc(n), respectively. The first to nth crystallinities Xc(I) to Xc(n) satisfy a following equation 1.
[37] Xc(n) > Xc(n-l) > ... > Xc(2) > Xc(I) equation 1
[38] Accordingly, when the first to nth crystallinities Xc(I) to Xc(n) have first to n "■ band gaps Bg(I) to Bg(n), respectively, the first to nth band gaps Bg(I) to Bg(n) satisfy a following equation 2. [39] Bg(n) < Bg(n-l) < ... < Bg(2) < Bg(I) equation 2
[40] , where the n"1 band gap Bg(n) is a band gap of macrocrystalline silicon having about
1.1 eV and the first band gap Bg(I) is a band gap of amorphous silicon within a range of about 1.7 eV to about 1.8eV.
[41] Although the solar cell aαjording to an embodiment of the present invention does not include PIN junction layers of amorphous silicon and PIN junction layers of micro- crystalline silicon of a tandem structure or a triple structure as an absorption layer, the light absorption band of the solar cell is broadened to cover a range from a shorter wavelength band to a longer wavelength band because the second intrinsic semiconductor layer has a continuous distribution of crystallinity, e.g., from amorphous silicon to microcrystalline silicon.
[42] FIG. 8 is a cross-sectional view showing a RTP for a solar cell aαjording to another embodiment of the present invention.
[43] In FIG. 8, a metal layer 190 is formed on the first intrinsic semiconductor layer 140 of amorphous silicon for reducing a temperature of an RTP and increasing a speed of crystallization. The metal layer 190 may include at least one of nickel (Ni), aluminum (Al) and palladium (Pd). Next, the RTP is performed for the metal layer 190 and the first intrinsic semiconductor layer 140 of amorphous silicon using a heating means such as a xenon (Xe) lamp or a halogen lamp applying heat optically. While the RTP is performed, metallic materials of the metal layer 190 are diffused into the first intrinsic semiconductor layer 140 to form a metal silidde. Since the metal silidde functions as a crystalline nucleus in crystallization by the RTP, the first intrinsic semiconductor layer 140 is crystallized under a relatively low temperature of about 350 0C to about 450 0C to form a second intrinsic semiconductor layer of linearly crystallized silicon. In addition, since the first intrinsic semiconductor layer 140 is crystallized by the RTP for a relatively shorter predetermined time period due to function of the metal silidde, the speed of crystallization increases. Spedfically, the RTP with a metal layer may be advantageously applied to a fabrication method for a solar cell including a transparent substrate of plastic having a relatively low heat resistance. After the RTP, the metal layer may remain and be used as a portion of electrode, or may be removed from the second intrinsic semiconductor layer.
[44] At step of ST16 and FIG. 7, an n-type semiconductor layer (i.e., second impurity- doped semiconductor layer) of amorphous silicon and a rear electrode 170 (i.e., second electrode) are sequentially formed on the second intrinsic semiconductor layer 150 of linearly crystallized silicon. The n-type semiconductor layer 160 of amorphous silicon may have a thickness of about 50 nm. For example, the n-type semiconductor layer 160 of amorphous silicon may be formed by a PECVD method using SiH 4, H2 and PH3 . The rear electrode 170 may include a TCO material or one of aluminum (Al), copper (Cu) and silver (Ag).
[45] When sunlight corresponding to a broad wavelength band is irradiated onto the transparent substrate 110 of the solar cell, the second intrinsic semiconductor layer 150 of linearly crystallized silicon absorbs the sunlight through the p-type semiconductor layer 13Q Since a portion of the second intrinsic semiconductor layer 150 adjacent to an interface with the p-type semiconductor layer 130 has a lower crystallinity, i.e., a higher ratio of amorphous silicon, the portion of the second intrinsic semiconductor layer 150 adjacent to the interface with the p-type semiconductor layer 133 absorbs the sunlight mostly corresponding to a shorter wavelength band. In addition, since a portion of the second intrinsic semiconductor layer 150 adjacent to an interface with the n-type semiconductor layer 163 has a higher crystallinity, i.e., a higher ratio of mi- crocrystalline silicon, the portion of the second intrinsic semiconductor layer 150 adjacent to the interface with the n-type semiconductor layer 163 absorbs the sunlight mostly corresponding to a longer wavelength band. Accordingly, light absorption and energy -converting efficiency of the solar cell according to an embodiment of the present invention are improved.
[46] FIGs. 5 and 6 are plan views showing a cluster type apparatus and an in-line type apparatus, respectively, for a solar cell according to an embodiment of the present invention.
[47] In FIG. 9, a cluster type apparatus 200 for a solar cell includes a transfer chamber
210, a load lock chamber 220 and a plurality of process chambers, e.g., first to fourth process chambers 230 to 263 The load lock chamber 220 and the first to fourth process chambers 230 to 263 surround and are coupled with the transfer chamber 2 IQ The transfer chamber 210 may include a transfer means such as a robot (not shown) therein to transfer a substrate between chambers. The transfer chamber 210 maintains a vacuum state during the fabrication process of the solar cell. The load lock chamber 220 is used as a buffer space for transferring a substrate between the transfer chamber 210 under a vacuum state and an exterior under an atmospheric pressure state. Accordingly, the load lock chamber 220 alternately has a vacuum state and an atmospheric pressure state.
[48] For example, the first to fourth process chambers 230 to 263 are coupled with side portions of the transfer chamber 21Q The p-type semiconductor layer 130 (of FIG. 3) is formed on the transparent substrate 110 (of FIG. 3) in the first process chamber 230, and the first intrinsic semiconductor layer 140 (of FIG. 4) of amorphous silicon is formed on the p-type semiconductor layer 130 in the second process chamber 24Q In addition, the first intrinsic semiconductor layer 140 is crystallized by the RTP to become the second intrinsic semiconductor layer 150 (of FIG. 6) of linearly crystallized silicon in the third process chamber 250, and the n-type semiconductor layer 160 (of FIG. 7) is formed on the second intrinsic semiconductor layer 150 in the fourth process chamber 263 A slot valve 270 selectively opening and closing a substrate path is disposed between the transfer chamber 210 and each of the load lock chamber 220 and the first to fourth process chambers 230 to 263
[49] After the transparent substrate 110 having the front electrode 120 thereon is inputted into the load lock chamber 220, the load lock chamber 220 is evacuated to have a vacuum state predetermined pressure. Next, the slot valve 270 between the load lock chamber 220 and the transfer chamber 210 is opened and the transparent substrate 110 is transferred from the load lock chamber 220 to the first process chamber 230 through the transfer chamber 210 by the transfer robot. In the first process chamber 230, the p- type semiconductor layer 130 is formed on the front electrode 12Q The first intrinsic semiconductor layer 140 is formed on the p-type semiconductor layer 130 after the transparent substrate 110 is transferred to the second process chamber 240, and the first intrinsic semiconductor layer 140 is crystallized to become the second intrinsic semiconductor layer 150 after the transparent substrate 110 is transferred to the third process chamber 250 Similarly, the n-type semiconductor layer 163 is formed on the second intrinsic semiconductor layer 150 after the transparent substrate 110 is transferred to the fourth process chamber 263 Next, the transparent substrate 110 is transferred from the fourth process chamber 263 to the load lock chamber 220 through the transfer chamber 210, and the transparent substrate 110 having the front electrode 120, the p-type semiconductor layer 133, the second intrinsic semiconductor layer 150 and the n-type semiconductor layer 163 thereon is outputted from the load lock chamber 22Q
[50] In FIG. 10, an in-line type apparatus 300 for a solar cell includes a loading chamber
310, first to fourth process chambers 320 to 350 and an unloading chamber 360 The loading chamber 310, the first to fourth process chambers 320 to 350 and the unloading chamber 363 are serially coupled with each other. A substrate is inputted into the loading chamber 310 and outputted from the unloading chamber 363 Each of the loading chamber 310, the first to fourth process chambers 320 to 350 and the unloading chamber 360 includes an in-line type transferring means such as a roller or a linear motor to transfer a substrate. The first to fourth process chambers 320 to 350 maintains a vacuum state during the fabrication process of the solar cell. Since a substrate is transferred between an exterior under an atmospheric pressure state and each of the first and fourth process chambers 320 and 350, each of the loading chamber 310 and the unloading chamber 363 alternately has a vacuum state and an atmospheric pressure state.
[51] After the transparent substrate 110 (of FIG. 3) having the front electrode 120 (of
FIG. 3) thereon is transferred to the first process chamber 320, the p-type semiconductor layer 130 (of FIG. 3) is formed on the front electrode 12Q The first intrinsic semiconductor layer 140 (of FIG. 4) is formed on the p-type semiconductor layer 130 after the transparent substrate 110 is transferred to the second process chamber 330, and the first intrinsic semiconductor layer 140 is crystallized to become the second intrinsic semiconductor layer 150 (of FIG. 6) after the transparent substrate 110 is transferred to the third process chamber 34Q Similarly, the n-type semiconductor layer 160 (of FIG. 7) is formed on the second intrinsic semiconductor layer 150 after the transparent substrate 110 is transferred to the fourth process chamber 35Q After the transparent substrate 110 having the front electrode 120, the p-type semiconductor layer 130, the second intrinsic semiconductor layer 150 and the n-type semiconductor layer 160 thereon is outputted from the in-line type apparatus for a solar cell, the rear electrode 170 (of FIG. 7) may be formed on the n-type semiconductor layer 160 in another apparatus such as a sputter.
[52] It will be apparent to those skilled in the art that various modifications and variations can be made in a solar cell, a method of fabricating the solar cell and an apparatus for fabricating the solar cell of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

Claims
[1] A method of fabricating a solar cell, comprising: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
[2] The method according to claim 1, wherein the second intrinsic semiconductor layer includes a linearly crystallized silicon such that a crystallinity of the second intrinsic semiconductor layer linearly varies along a direction from a bottom surface to a top surface of the second intrinsic semiconductor layer.
[3] The method according to claim 1, wherein the first intrinsic semiconductor layer has a thickness of about 1 μm to about 3 μm.
[4] The method according to claim 1, wherein a first portion of the second intrinsic semiconductor layer closer to the first impurity-doped semiconductor layer has a higher crystallinity and a second portion of the second intrinsic semiconductor layer closer to the second impurity-doped semiconductor layer has a lower crystallinity.
[5] The method according to claim 1, wherein a first portion of the second intrinsic semiconductor layer closer to the first impurity-doped semiconductor layer has a higher band gap and a second portion of the second intrinsic semiconductor layer closer to the second impurity-doped semiconductor layer has a lower band gap.
[6] The method according to claim 1, wherein heating the first intrinsic semiconductor layer comprises: disposing an optical heating means over the first intrinsic semiconductor layer; irradiating light onto the first intrinsic semiconductor layer; and heating the first intrinsic semiconductor layer up to about 500 0C to about 600 0C.
[7] The method according to claim 1, wherein heating the first intrinsic semiconductor layer comprises: forming a metal layer on the first intrinsic semiconductor layer; disposing an optical heating means over the metal layer; irradiating light onto the metal layer; and heating the first intrinsic semiconductor layer up to about 350 0C to about 450
0C.
[8] The method according to claim 7, wherein the metal layer includes at least one of nickel (Ni), aluminum (Al) and palladium (Pd).
[9] The method according to claim 1, wherein the first impurity-doped semiconductor layer includes a p-type amorphous silicon, the first intrinsic semiconductor layer includes an intrinsic amorphous silicon, and the second impurity-doped semiconductor layer includes an n-type amorphous silicon.
[10] A high efficiency solar cell, comprising: a transparent substrate; a first electrode on the transparent substrate; a first impurity-doped semiconductor layer on the first electrode; an intrinsic semiconductor layer on the first impurity-doped semiconductor layer, the intrinsic semiconductor layer having a gradually varying crystallinity; a second impurity-doped semiconductor layer on the intrinsic semiconductor layer; and a second electrode on the second impurity-doped semiconductor layer.
[11] The solar cell according to claim 10, wherein the intrinsic semiconductor layer includes a linearly crystallized silicon such that a crystallinity of the intrinsic semiconductor layer linearly varies along a direction from a bottom surface to a top surface of the intrinsic semiconductor layer.
[12] The solar cell according to claim 10, further comprising a metal layer between the intrinsic semiconductor layer and the second impurity-doped semiconductor layer.
[13] An apparatus for fabricating a solar, comprising: a transfer chamber including a transfer means for transferring a substrate; a load lock chamber coupled with a first side portion of the transfer chamber, the load lock chamber alternately having a vacuum state and an atmospheric pressure state for inputting and outputting the substrate; a first process chamber coupled with a second side portion of the transfer chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a third side portion of the transfer chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a fourth side portion of the transfer chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and a fourth process chamber coupled with a fifth side portion of the transfer chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer.
[14] An apparatus for fabricating a solar, comprising: a loading chamber alternately having a vacuum state and an atmospheric pressure state for inputting a substrate; a first process chamber coupled with a side portion of the loading chamber, the first process chamber forming a first impurity-doped semiconductor layer on a first electrode on the substrate; a second process chamber coupled with a side portion of the first process chamber, the second process chamber forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; a third process chamber coupled with a side portion of the second process chamber, the third process chamber heating the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; a fourth process chamber coupled with a side portion of the third process chamber, the fourth process chamber forming a second impurity-doped semiconductor layer on the second intrinsic semiconductor layer; and an unloading chamber coupled with a side portion of the fourth process chamber, the unloading chamber alternately having a vacuum state and an atmospheric pressure state for outputting the substrate.
[15] A method of fabricating a solar cell, comprising: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a light absorbing layer on the first impurity-doped semiconductor layer; heating the light absorbing layer; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the light absorbing layer. [16] A method of fabricating a solar cell, comprising: sequentially forming a first electrode and a first impurity-doped semiconductor layer on a transparent substrate; forming a first intrinsic semiconductor layer on the first impurity-doped semiconductor layer; crystallizing the first intrinsic semiconductor layer to form a second intrinsic semiconductor layer having a gradually varying crystallinity; and sequentially forming a second impurity-doped semiconductor layer and a second electrode on the second intrinsic semiconductor layer.
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KR20080104696A (en) 2008-12-03
US20100132791A1 (en) 2010-06-03

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