WO2008145186A1 - Floating-body dram cell capacitively coupled to an electrode in an sti region and fabrication method thereof - Google Patents

Floating-body dram cell capacitively coupled to an electrode in an sti region and fabrication method thereof Download PDF

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Publication number
WO2008145186A1
WO2008145186A1 PCT/EP2007/055310 EP2007055310W WO2008145186A1 WO 2008145186 A1 WO2008145186 A1 WO 2008145186A1 EP 2007055310 W EP2007055310 W EP 2007055310W WO 2008145186 A1 WO2008145186 A1 WO 2008145186A1
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WO
WIPO (PCT)
Prior art keywords
insulating
electrically conductive
memory device
semiconductor memory
trench
Prior art date
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PCT/EP2007/055310
Other languages
French (fr)
Inventor
Franck Genevaux
Richard Ferrant
Pierre Malinge
Andreas Wild
Marius Orlowski
Original Assignee
Stmicroelectronics (Crolles 2) Sas
Freescale Semiconductor, Inc.
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Publication date
Application filed by Stmicroelectronics (Crolles 2) Sas, Freescale Semiconductor, Inc. filed Critical Stmicroelectronics (Crolles 2) Sas
Priority to PCT/EP2007/055310 priority Critical patent/WO2008145186A1/en
Publication of WO2008145186A1 publication Critical patent/WO2008145186A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Definitions

  • a DRAM cell according to a possible architecture comprises one transistor and one capacitor used in particular for storing information.
  • An alternate architecture is a so-called floating body capacitor- less DRAM cell.
  • no capacitor is provided for storing information.
  • the floating body charging is used for storing the information while the memory cell transistor is used to read stored information.
  • figure 1 is a diagrammatic top view of an embodiment of a semiconductor memory device
  • figure 2 and figure 3 are respectively partial cross- sections according to lines H-II and III-III of figure 1
  • figure 4 is another representation of an embodiment of a floating body capacitor-less DRAM cell
  • figure 5 illustrates curves corresponding to erase and write operations
  • - figure 6 illustrates diagrammatically a top view of an embodiment of a semiconductor chip
  • figure 7 is a diagrammatic cross-section view of a semiconductor chip
  • figures 8- 15 illustrate diagrammatically steps of an embodiment of a fabricating method.
  • figure 16 is a diagrammatic top view of an other embodiment of a semiconductor memory device
  • figures 17, 18 and 19 are respectively partial cross- sections according to lines XVII-XVII, XVIII-XVIII and XIX-XIX of figure 16
  • figure 20 illustrates diagrammatically a top view o f another embodiment of a semi-conductor chip
  • figure 21 is another diagrammatically cross-section view of a semi-conductor chip
  • - figures 22-27 illustrate diagrammatically steps o f another embodiment of a fabricating method.
  • said insulating regions are insulating trenches, each trench comprising an inner electrically conductive region surrounded by an insulating layer contacting the floating body of at least one cell ; said capacitor means comprise cell capacitor means respectively associated with the cells, each cell capacitor means comprising at least a part of the inner electrically conductive region, a part of the floating body of the cell and a part of the insulating layer contacting said floating body.
  • All the cell capacitor means may be mutually connected, providing thus a huge capacitance.
  • All the coupling electrodes may be mutually connected.
  • the coupling electrodes may have a floating potential.
  • the coupling electrodes may be connected to a reference voltage, for example a negative or low voltage, in order to have an accumulation mode on the capacitance with floating body.
  • the semiconductor chip may further comprise an annular semiconductor region surrounding said semiconductor memory device and separating the insulating trenches of said semiconductor memory device from said standard shallow insulating trenches.
  • a method for fabricating a semiconductor memory device comprising forming insulating regions in a substrate and forming floating body capacitor- less DRAM cells between said insulating regions.
  • each insulating region comprises forming an electrically conductive region and an insulating zone sandwiched between the floating body of one cell and the electrically conductive region.
  • forming said electrically conductive region and said insulating zone sandwiched between the floating body of one cell and the electrically conductive region comprises forming a trench in a semiconductor substrate, forming an insulating layer on the walls of said trench and filling the trench with an electrically conductive material.
  • a method for fabricating a semiconductor component comprising embedding on a monolithic substrate standard shallow insulating trenches and a semiconductor device fabricated according to the method defined above.
  • the memory cell CL comprises a floating body FB which is here of the P type conductivity.
  • the floating body FB is also bordered laterally by a trench capacitor STC which separates the memory cell CL from an adjacent memory cell of said array or matrix.
  • the trench capacitor comprises an inner electrically conductive region ECR formed with an electrically conductive material, for example polysilicone or other types of electrically conductive material, surrounded by the insulating layer INSL contacting the floating body of the cell.
  • ECR electrically conductive region
  • an electrically conductive material for example polysilicone or other types of electrically conductive material
  • a cell capacitor means CCM associated with a cell CL comprises a part of the inner electrically conductive region ECR, a part of floating body of the cell and a part of the insulating layer contacting said floating body.
  • the two electrodes of the cell capacitor means
  • CCM are respectively formed by at least a part of the floating body FB and the conductive region ECR while the part of the insulating layer sandwiched there between forms the dielectric region of the cell capacitor means CCM.
  • the memory transistor MCT of the memory cell CL is a MOS transistor formed on and within the floating body FB and comprises source/drain regions S/D, having here the N type conductivity, and a gate G isolated from the floating body by a gate oxide GO.
  • This coupling electrode CE can be floating because the capacitor means of the memory array have a huge capacitance as all the cell capacitor means (trench capacitors) of all the memory cells o f the matrix are mutually connected.
  • this coupling electrode CE can be polarized with a negative (or low) voltage VN (figure 4) in order to have an accumulation mode on the capacitance with the floating body FB.
  • the top part of figure 5 illustrates the time evolution of the voltages SL, WL and BL applied to the memory cell during erase and write operations.
  • the bottom part of figure 5 illustrates the corresponding evolution of the floating body voltage VB .
  • Curve C l (dotted line) corresponds to a memory cell of the prior art, i.e. without STI capacitance, whereas curves C2 corresponds to a memory cell with STI capacitance, i.e. with trench capacitor STC .
  • the number of charges stored in the floating body is increased with the presence of the capacitor means CCM and thus the retention time is improved.
  • the memory point' s write and erase operations are improved because of the large capacitance added which stabilizes the potential of the storage node (floating body).
  • the capacitance on STI node can be used for another need like output capacitance of a charge pump.
  • STI shallow trench capacitors
  • STC shallow trench capacitors
  • an active ring ANR i.e. a semiconductor area without shallow trench isolation or shallow trench capacitor, can help to process both shallow trench insulation and shallow trench capacitor on the same die.
  • this ring ANR enables to separate the two types of trenches.
  • a semiconductor chip can co-integrate a semiconductor memory device MA as well as other types of components including standard MOS transistors SDT (PMOS or NMOS).
  • standard MOS transistors SDT PMOS or NMOS
  • the shallow trench insulation STI delimitating the standard transistor SDT is separated from the memory array MA by the ring ANR.
  • a well NW here an N well
  • the dotted line inside the N strap ANR represents an example of mask pattern MSK2 used to make the specific trench insulation STI.
  • the mask MSKl used to make trench can be the same for all trenches.
  • This second insulator can be also SIO 2 .
  • Figures 16, 17 and 18 are analogous to figures 1 , 2 and 3.
  • Figures 20 and 21 are analogous to figures 6 and 7.
  • a first layer L l typically a so-called “Pad oxide” is formed, which is covered by a second layer L2 for example a nitride layer (figure 22).
  • the exccedent of conductive material is then removed (figure 25) for example by using a conventional planarization step.
  • a further planarization step for example an oxide CMP (Chemical Mechanical
  • Planarization is applied to the oxide-filled trenches STI and to the poly-filled trenches STC covered by the oxide caps CP l protruding out of the main surface of the wafer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor memory device comprises an array of floating body capacitor-less DRAM cells (CL) mutually spaced by insulating regions (INSL). It further comprises capacitor means (CCM) contacting the floating bodies (FB) of the cells and partially formed in said insulating regions (INSL). A method of manufacturing the device is also disclosed.

Description

FLOATING-BODY DRAM CELL CAPACITIVELY COUPLED TO AN ELECTRODE IN AN STI REGION
AND FABRICATION METHOD THEREOF
The invention relates to semiconductor memory devices, more particularly to floating body capacitor-less DRAM (Dynamic Random Access Memory) cells.
A DRAM cell according to a possible architecture comprises one transistor and one capacitor used in particular for storing information.
An alternate architecture is a so-called floating body capacitor- less DRAM cell. In such an architecture, no capacitor is provided for storing information. The floating body charging is used for storing the information while the memory cell transistor is used to read stored information.
More precisely, a conventional floating body capacitor-less DRAM cell comprises a floating body laterally bordered by a conventional insulating region, typically a conventional Shallow Trench Isolation (STI). The floating body is further isolated from the substrate by a buried insulating layer, for example an N layer if the substrate is of the P type. The transistor of the memory cell is a MOS transistor located within and on the floating body.
According to an embodiment, it is proposed a floating body capacitor-less DRAM cell which improves memory point's write and erase operations. According to another embodiment, it is proposed a floating body capacitor-less DRAM cell which increases the number of charge stored in the floating body and thus improves the retention time.
Several aspects and embodiments of the invention are claimed in the accompanying claims. Other advantages and features of the invention will appear on examining the detailed description of embodiments, these being in no way limiting, and of the appended drawings in which: figure 1 is a diagrammatic top view of an embodiment of a semiconductor memory device, figure 2 and figure 3 are respectively partial cross- sections according to lines H-II and III-III of figure 1 , figure 4 is another representation of an embodiment of a floating body capacitor-less DRAM cell, figure 5 illustrates curves corresponding to erase and write operations, - figure 6 illustrates diagrammatically a top view of an embodiment of a semiconductor chip, figure 7 is a diagrammatic cross-section view of a semiconductor chip, and, figures 8- 15 illustrate diagrammatically steps of an embodiment of a fabricating method. figure 16 is a diagrammatic top view of an other embodiment of a semiconductor memory device, figures 17, 18 and 19 are respectively partial cross- sections according to lines XVII-XVII, XVIII-XVIII and XIX-XIX of figure 16, figure 20 illustrates diagrammatically a top view o f another embodiment of a semi-conductor chip, figure 21 is another diagrammatically cross-section view of a semi-conductor chip, and, - figures 22-27 illustrate diagrammatically steps o f another embodiment of a fabricating method.
According to an aspect, a semiconductor memory device is proposed, comprising an array of floating body capacitor-less DRAM cells mutually spaced by insulating regions. According to a general feature of this aspect, the semiconductor memory device further comprises capacitor means contacting the floating bodies of the cells and partially formed in said insulating regions.
According to an embodiment, said insulating regions are insulating trenches, each trench comprising an inner electrically conductive region surrounded by an insulating layer contacting the floating body of at least one cell ; said capacitor means comprise cell capacitor means respectively associated with the cells, each cell capacitor means comprising at least a part of the inner electrically conductive region, a part of the floating body of the cell and a part of the insulating layer contacting said floating body.
According to another embodiment, each insulating trench further comprises an insulating cap covered said inner electrically conductive region. This insulating cap improves the electrical isolation between the inner electrically conductive region and active areas o f the device (gate, drain, source).
All the cell capacitor means may be mutually connected, providing thus a huge capacitance.
According to another aspect, a semiconductor memory device is proposed, comprising an array of floating body capacitor-less DRAM cells. According to a general feature of this aspect, the cells are mutually spaced by trench capacitors, each trench capacitor including a dielectric layer sandwiched between the floating body of one cell and an inner electrically conductive region of said trench. The inner electrically conductive region of each trench capacitor may be totally wrapped by an insulating covering including said dielectric layer.
The trench capacitors may be mutually connected.
According to another aspect, a semiconductor memory device is proposed, comprising an array of floating body capacitor-less DRAM cells mutually spaced by insulating regions. According to a general feature of this aspect, each cell further comprises a coupling electrode in the insulating region bordering the floating body of said cell.
According to an embodiment, the insulating region comprises a trench including an insulating layer on the wall of said trench and an electrically conductive region covering said insulating layer, said coupling electrode comprising said electrically conductive region. The electrically conductive region of each trench may be totally wrapped by an insulating covering including said insulating layer.
All the coupling electrodes may be mutually connected. The coupling electrodes may have a floating potential.
Alternatively, the coupling electrodes may be connected to a reference voltage, for example a negative or low voltage, in order to have an accumulation mode on the capacitance with floating body.
According to another aspect, it is proposed a semiconductor chip, comprising a monolithic substrate and standard shallow insulating trenches (STI) embedded on said substrate with a semiconductor memory device as defined above.
According to an embodiment, the semiconductor chip may further comprise an annular semiconductor region surrounding said semiconductor memory device and separating the insulating trenches of said semiconductor memory device from said standard shallow insulating trenches.
According to another aspect, it is proposed a method for fabricating a semiconductor memory device, comprising forming insulating regions in a substrate and forming floating body capacitor- less DRAM cells between said insulating regions.
According to a general feature of this aspect, forming each insulating region comprises forming an electrically conductive region and an insulating zone sandwiched between the floating body of one cell and the electrically conductive region.
According to an embodiment, forming said electrically conductive region and said insulating zone sandwiched between the floating body of one cell and the electrically conductive region comprises forming a trench in a semiconductor substrate, forming an insulating layer on the walls of said trench and filling the trench with an electrically conductive material.
According to another embodiment forming said electrically conductive region and said insulating zone sandwiched between the floating body of one cell and the electrically conductive region further comprise forming an insulating cap on said electrically conductive material, for example by reoxidizing the top of the electrically conductive material.
According to another aspect, it is proposed a method for fabricating a semiconductor component comprising embedding on a monolithic substrate standard shallow insulating trenches and a semiconductor device fabricated according to the method defined above.
According to an embodiment, said embedding step comprises forming trenches in said substrate, forming an insulating layer on the walls of each trench, filling each trench with an electrically conductive material, removing the electrically conductive material from some of the trenches and filling said some of the trenches with an insulating material. According to an embodiment, said embedding step further comprises forming in said substrate an annular semiconductor region surrounding said semiconductor memory device and separating the insulating trenches of said semiconductor memory device from said standard shallow insulating trenches. Turning now to figures 1 -3 , the reference sign MA designates a semiconductor memory device comprising an array of floating body capacitor-less DRAM cells CL mutually spaced by insulating regions which are here insulating layer INSL.
The memory cell CL comprises a floating body FB which is here of the P type conductivity.
The floating body is separated from the substrate SB, here a P substrate, by a buried isolation layer BL which is here a semiconductor layer of the N type conductivity.
The floating body FB is also bordered laterally by a trench capacitor STC which separates the memory cell CL from an adjacent memory cell of said array or matrix.
The trench capacitor comprises an inner electrically conductive region ECR formed with an electrically conductive material, for example polysilicone or other types of electrically conductive material, surrounded by the insulating layer INSL contacting the floating body of the cell.
Thus, a cell capacitor means CCM associated with a cell CL comprises a part of the inner electrically conductive region ECR, a part of floating body of the cell and a part of the insulating layer contacting said floating body.
In other words, the two electrodes of the cell capacitor means
CCM are respectively formed by at least a part of the floating body FB and the conductive region ECR while the part of the insulating layer sandwiched there between forms the dielectric region of the cell capacitor means CCM.
The memory transistor MCT of the memory cell CL is a MOS transistor formed on and within the floating body FB and comprises source/drain regions S/D, having here the N type conductivity, and a gate G isolated from the floating body by a gate oxide GO.
As illustrated in figure 3 , which is a cut-view along the transistor's width (whereas figure 2 is a cut-view along transistor' s length) but also in figure 1 , all the cell capacitor means CCM are mutually connected through the gate oxide and the electrically conductive regions providing thus a huge capacitance.
Adding a coupling electrode in the shallow trench isolation permits to improve write and read operations as it is illustrated in figure 5.
This coupling electrode CE can be floating because the capacitor means of the memory array have a huge capacitance as all the cell capacitor means (trench capacitors) of all the memory cells o f the matrix are mutually connected.
However, this coupling electrode CE can be polarized with a negative (or low) voltage VN (figure 4) in order to have an accumulation mode on the capacitance with the floating body FB.
The top part of figure 5 illustrates the time evolution of the voltages SL, WL and BL applied to the memory cell during erase and write operations. The bottom part of figure 5 illustrates the corresponding evolution of the floating body voltage VB .
Curve C l (dotted line) corresponds to a memory cell of the prior art, i.e. without STI capacitance, whereas curves C2 corresponds to a memory cell with STI capacitance, i.e. with trench capacitor STC .
It can be seen in figure 5 a reduction of the coupling effect o f source/drain for a memory cell with STI capacitance with respect to a memory cell without STI capacitance.
Further, the voltage difference between a state "1 " and a state "0" increases for a memory cell with trench capacitor STC.
Further, the number of charges stored in the floating body is increased with the presence of the capacitor means CCM and thus the retention time is improved.
The memory point' s write and erase operations are improved because of the large capacitance added which stabilizes the potential of the storage node (floating body).
The capacitance on STI node can be used for another need like output capacitance of a charge pump.
As illustrated in figures 6 and 7, it is possible to embed (i.e. to realize with the same process) both standard shallow trench insulation
(STI) and shallow trench capacitors (STC) on the same die.
In this respect, an active ring ANR, i.e. a semiconductor area without shallow trench isolation or shallow trench capacitor, can help to process both shallow trench insulation and shallow trench capacitor on the same die. As a matter of fact, this ring ANR enables to separate the two types of trenches.
Thus, a semiconductor chip can co-integrate a semiconductor memory device MA as well as other types of components including standard MOS transistors SDT (PMOS or NMOS). The shallow trench insulation STI delimitating the standard transistor SDT is separated from the memory array MA by the ring ANR.
Of course, as illustrated more particularly in figure 7, a well NW, here an N well, permits also to deeply separate the memory transistor MCT from the standard transistor SDT. In figure 6, the dotted line inside the N strap ANR represents an example of mask pattern MSK2 used to make the specific trench insulation STI.
As it will be now described more in details with reference to figures 8 and 15 , only a new mask MSK2 can be necessary to implement both STI and STC on one monolithic substrate SB.
The mask MSKl used to make trench can be the same for all trenches.
More precisely, departing from an initial wafer or substrate SB without trenches (figure 8), shallow trenches TRC are conventionally formed by using a mask pattern MSKl (figure 9).
Then, a first insulator deposition is made in all shallow trenches. This insulating layer INSL is for example a SIO2 layer. This deposition can be made with or without the mask pattern MSKl . Then, a conductive material, for example polysilicone, is used to fill the shallow trenches (figure 1 1 ).
If necessary, a planarization step can be done to remove the exceedent of conductive material (figure 12).
Then, the second mask MSK2 enables to remove selectively the conductive material from some trenches, i.e. from the trenches which will not be the trench capacitors (figure 13).
Then, the empty trenches are filled by a second insulator (figure 14). This second insulator can be also SIO2.
If necessary, as illustrated in figure 15 , a final planarization is done which permits to obtain both shallow trench capacitors STC and standard shallow trench insulation STI on the same monolithic substrate SB .
The other steps permitting to fabricate either the floating body capacitor-less DRAM array or the standard transistors are conventional steps. The ring ANR may be realized by implantation inside the substrate.
We refer now to figures 16 and following which relate to another embodiment.
Figures 16, 17 and 18 are analogous to figures 1 , 2 and 3. Figures 20 and 21 are analogous to figures 6 and 7.
For simplification reasons, only the differences between these figures will be now described.
As it can be seen in particular on figures 16- 19, the inner electrically conductive region ECR of a trench capacitor STC is here totally wrapped by an insulating cover INSCV.
This insulating cover INSCV includes the insulating layer INSL contacting the floating body of the cell and an insulating cap INSCP covering said inner electrically conductive region ECR. Such an embodiment permits to improve the electrical isolation between the electrically conductive material ECR and the source/drain regions as well as the gate region of the memory transistor MCT.
Further, as it can be seen more particularly on figures 16 and
19, whereas reference GTC designates a gate contact, a further contact TTC is provided in order to ensure an electrical contact with the polysilicon ECR, in order for example to permit a mutual connexion o f all the cell capacitor means.
Turning now to figures 20 and 21 , as for figures 6 and 7, it is possible to embed, (i.e. to realize with the same process) both standard shallow trench insulation (STI) and shallow trench capacitor (STC) on the same die.
Another example of steps of a fabrication method permitting to embed both STI and STC on the same die will be now described with reference to figures 22-27. On the silicone substrate SB, a first layer L l , typically a so- called "Pad oxide" is formed, which is covered by a second layer L2 for example a nitride layer (figure 22).
Then, as illustrated in figure 23 , shallow trenches TR are conventionally formed by using a first mask pattern as for figure 9 for example.
A first insulator deposition is made in all shallow trenches. This insulating layer INSL which is also called a liner oxide, is for example a SiO2 layer. As for figure 9, the thickness of such liner oxide INSL may be typically less than 100A. A third electrically conductive layer L3 , for example a polysilicon layer is then conventionally formed on the portions of the second layer L2 as well as in the trench TR and on the insulating layer INSL (figure 24).
The exccedent of conductive material is then removed (figure 25) for example by using a conventional planarization step.
Then, the top part of the conductive material L3 located within the trenches TR is oxidized leading to the formation of insulating caps CP l .
The nitride layer L2 is then removed (figure 26). After having used the non critical mask MSK2, the formation of the conventional shallow trench insulation STI is performed.
Then, after having removed the mask MSK2, a further planarization step, for example an oxide CMP (Chemical Mechanical
Planarization) is applied to the oxide-filled trenches STI and to the poly-filled trenches STC covered by the oxide caps CP l protruding out of the main surface of the wafer.
The insulating cap INSCP is thus obtained, forming with the insulating layer INSL (liner oxide) the insulating covering INSCV.
Whereas the above embodiments have been realized with SOI (Silicon On Insulator) technology, it is also possible to use a bulk technology.
Further, P and N layers can be inverted in a memory cell to work with a PMOS instead of a NMOS.

Claims

1. Semiconductor memory device, comprising an array (MA) of floating body capacitor-less DRAM cells (CL) mutually spaced by insulating regions (INSL), characterized by the fact that it further comprises capacitor means (CCM) contacting the floating bodies (FB) o f the cells and partially formed in said insulating regions (INSL).
2. Semiconductor memory device according to claim 1 , wherein said insulating regions are insulating trenches, each trench comprising an inner electrically conductive region (ECR) surrounded by an insulating layer (INSL) contacting the floating body (FB) of at least one cell, said capacitor means comprise cell capacitor means (CCM) respectively associated with the cells, each cell capacitor means (CCM) comprising at least a part of the inner electrically conductive region (ECR), a part of the floating body (FB) of the cell and a part of the insulating layer (INSL) contacting said floating body.
3. Semiconductor memory device according to claim 2, wherein each insulating trench further comprises an insulating cap covering said inner electrically conductive region.
4. Semiconductor memory device according to any one of the preceding claims, wherein all the cell capacitor means (CCM) are mutually connected.
5. Semiconductor memory device, comprising an array of floating body capacitor-less DRAM cells, characterized by the fact that the cells (CL) are mutually spaced by trench capacitors (STC), each trench capacitor (STC) including a dielectric layer sandwiched between the floating body of one cell and an inner electrically conductive region o f said trench.
6. Semiconductor memory device according to claim 5 , wherein the inner electrically conductive region of each trench capacitor is totally wrapped by an insulating covering including said dielectric layer.
7. Semiconductor memory device, according to claim 5 or 6 wherein all the trench capacitors (STC) are mutually connected.
8. Semiconductor memory device, comprising an array of floating body capacitor-less DRAM cells mutually spaced by insulating regions, characterized by the fact that each cell (CL) further comprises a coupling electrode (CE) in the insulating region bordering the floating body of said cell.
9. Semiconductor memory device according to claim 8, wherein the insulating region comprises a trench (TRC) including an insulating layer (INSL) on the wall of said trench and an electrically conductive region (ECR) covering said insulating layer, said coupling electrode (CE) comprising said electrically conductive region.
10. Semiconductor memory device according to claim 9, wherein the electrically conductive region of each trench is totally wrapped by an insulating covering including said insulating layer.
1 1. Semiconductor memory device according to any one o f claims 8 to 10, wherein all the coupling electrodes are mutually connected.
12. Semiconductor memory device according to claim 1 1 , wherein the coupling electrodes have a floating potential.
13. Semiconductor memory device according to claim 1 1 , wherein the coupling electrodes are connected to a reference voltage
(VN).
14. Semiconductor chip, comprising a monolithic substrate and standard shallow insulating trenches (STI) embedded on said substrate with a semiconductor memory device according to any one of the preceding claims.
15. Semiconductor chip according to claim 14, further comprising an annular semiconductor region (ANR) surrounding said semiconductor memory device and separating the insulating trenches of said semiconductor memory device from said standard shallow insulating trenches.
16. Method for fabricating a semiconductor memory device, comprising forming insulating regions in a substrate, and forming floating body capacitor-less DRAM cells between said insulating regions, characterized by the fact that forming each insulating region comprises forming an electrically conductive region (ECR) and an insulating zone (INSL) sandwiched between the floating body of one cell and the electrically conductive region.
17. Method according to claim 16, wherein forming said electrically conductive region and said insulating zone sandwiched between the floating body of one cell and the electrically conductive region comprises forming a trench (TRC) in a semiconductor substrate (SB), forming an insulating layer (INSL) on the walls of said trench and filling the trench with an electrically conductive material (ECR).
18. Method according to claim 16, wherein forming said electrically conductive region and said insulating zone sandwiched between the floating body of one cell and the electrically conductive region further comprise forming an insulating cap on said electrically conductive material (ECR)
19. Method for fabricating a semiconductor component, comprising embedding on a monolithic substrate standard shallow insulating trenches and a semiconductor device fabricated according to the method claimed in any one of claims 16 to 18.
20. Method according to claim 19, wherein said embedding step comprises forming trenches in said substrate, forming an insulating layer on the walls of each trench, filling each trench with an electrically conductive material, removing the electrically conductive material from some of the trenches and filling said some of the trenches with an insulating material.
21. Method according to claim 19 or 20, wherein said embedding step further comprises forming in said substrate an annular semiconductor region (ANR) surrounding said semiconductor memory device and separating the insulating trenches of said semiconductor memory device from said standard shallow insulating trenches.
PCT/EP2007/055310 2007-05-31 2007-05-31 Floating-body dram cell capacitively coupled to an electrode in an sti region and fabrication method thereof WO2008145186A1 (en)

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Publication number Priority date Publication date Assignee Title
US20060194410A1 (en) * 2005-02-28 2006-08-31 Hiroyuki Sugaya Semiconductor device with cavity and method of manufacture thereof
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Publication number Priority date Publication date Assignee Title
US20060194410A1 (en) * 2005-02-28 2006-08-31 Hiroyuki Sugaya Semiconductor device with cavity and method of manufacture thereof
US20060267082A1 (en) * 2005-05-31 2006-11-30 Franz Hofmann Semiconductor memory component
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