WO2008133620A1 - Commutateur t/r à haute puissance utilisant des transistors empilés - Google Patents

Commutateur t/r à haute puissance utilisant des transistors empilés Download PDF

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Publication number
WO2008133620A1
WO2008133620A1 PCT/US2007/010295 US2007010295W WO2008133620A1 WO 2008133620 A1 WO2008133620 A1 WO 2008133620A1 US 2007010295 W US2007010295 W US 2007010295W WO 2008133620 A1 WO2008133620 A1 WO 2008133620A1
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WO
WIPO (PCT)
Prior art keywords
transistor
stacked
transistors
transistor configuration
shunt
Prior art date
Application number
PCT/US2007/010295
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English (en)
Inventor
Haifeng Xu
Kenneth K. O
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University Of Florida
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by University Of Florida filed Critical University Of Florida
Priority to PCT/US2007/010295 priority Critical patent/WO2008133620A1/fr
Publication of WO2008133620A1 publication Critical patent/WO2008133620A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Definitions

  • the Transmit/Receive (T/R) switch is a key building block of a Radio Frequency (RF) front end of most time-division duplexing (TDD) communication systems.
  • a typical TDD communication system includes a transmitter, receiver, T/R switch, and antenna.
  • Figure 1 shows a block diagram of an example of a TDD communication system.
  • a T/R switch follows the Power Amplifier (PA), and usually needs to sustain the highest voltage swing.
  • PA Power Amplifier
  • the performance of the T/R switch depends on certain operating performance parameters that are taken into consideration in its design.
  • the key parameters tend to be the 1-dB compression point at input (IPia ⁇ ), insertion loss (IL) and isolation.
  • the 1-dB compression point, or IP)dB > describes the switch's ability to handle large input power when the switch is turned on.
  • the IPidB is defined as the input power at which the insertion loss has increased by 1 dB from its low-power value.
  • Power handling capabilities of certain stacked transistors are described by T. Ohnakado, et al., "21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs)," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 577-584, April 2004.
  • the IL of the switch can be determined from the difference between the available power at an input node and the power that is delivered to a load at an output node. IL tends to depend on resistances of the switch transistors.
  • silicon-on-insulator (SOI) technology is utilized.
  • SOI silicon-on-insulator
  • CMOS T/R switches In bulk CMOS technologies, low breakdown voltage of transistors and parasitic diodes at drain and source junctions limit the power handling capability of bulk CMOS T/R switches. Techniques, such as floating body, stacked transistors and DC bias of drain/source, have been used to improve this performance. However, it is still difficult to implement CMOS T/R switches with Pi d B higher than 3OdBm and IL lower than IdB. This impedes the realization of low cost RF systems using foundry CMOS processes.
  • IPid ⁇ 1-dB compression point
  • Embodiments of the present invention pertain to improved T/R switch circuit designs.
  • Embodiments of the subject invention can be used in time-division duplexing (TDD) CMOS transceivers with high transmitting power.
  • TDD time-division duplexing
  • the power handling capability of T/R switches using foundry CMOS processes can be increased, while keeping the insertion loss low.
  • a high level of integration can be possible such that low cost solutions of wireless communication systems can be provided on a single chip.
  • the subject TVR switch can provide an improved power handling capability and can be implemented using foundry CMOS processes.
  • the T/R switch can be implemented in bulk CMOS.
  • the T/R switch circuit incorporates a series transistor on the TX leg, 3-stack transistors on the RX leg, shunt 3-stack transistors on the TX node, and a shunt transistor on the RX node.
  • the transistors can be formed using sub-design-rule (SDR) channel length to reduce insertion loss (IL).
  • SDR sub-design-rule
  • IL insertion loss
  • the transistors can be located in isolated p- wells to provide an improved floating body.
  • feed-forward capacitors can be included to balance the voltage swing among the stack transistors.
  • the feedforward capacitors can be metal capacitors.
  • the feed-forward capacitors can be MIM capacitors.
  • transistors can be formed in separate p-wells placed within n-wells in a stacked formation. This method significantly increases the power handling capability.
  • SDR channel length MOS transistors can be utilized. Feedforward capacitance is another method that can be incorporated to distribute the voltage swing evenly among the stack transistors, and therefore improve power capability.
  • FIG. 1 is a block schematic showing a T/R switch in a typical TDD communication system.
  • Figure 2 shows a simplified schematic of T/R switch with 3-stack sub-design-rule
  • Figure 3 shows a cross-section of 3-stack MOS transistors in a SDR T/R switch according to an embodiment of the subject invention.
  • Figure 4 shows a die photo of a 3-stack SDR T/R switch according to an embodiment of the subject invention.
  • Figure 5 is a plot of measured insertion loss of a SDR CMOS T/R switch using 3- stack transistors according to an embodiment of the subject invention, compared to that of a switch using 2-stack 0.34- ⁇ m length 3.3-V transistors.
  • Figure 6 is a plot of measured isolation and return loss for the SDR CMOS T/R switch using 3-stack SDR channel length transistors.
  • Figure 7 is a plot of IP ⁇ 8 and IIP 3 measurement results of the 3-stack SDR T/R switches with source/drain biased at 3V and OV, and with and without the feed-forward capacitors.
  • Figure 8 is a table providing a performance summary of stacked T/R switches.
  • T/R switch circuit designs for improved characteristics for T/R switches.
  • T/R switch circuit designs are provided that can increase IPidB above 30 dBm for T/R switches while maintaining IL less than —1 dB.
  • An exemplary embodiment involves a 900 MHz single- pole-double-throw (SPDT) switch with IP M B of 31.3 dBm, and IL' s of 0.5 dB and 1 dB in transmit (TX) and receive (RX) modes at 900 MHz.
  • TX transmit
  • RX receive
  • isolation is better than 29 dB up to 1 GHz.
  • Another exemplary embodiment involves a 2.4 GHz SPDT switch with IP KJB of 28 dBm, and IL' s of 0.8 dB and 1.2 dB in TX and RX modes.
  • isolation is better than 24 dB up to 2.4 GHz.
  • switches can be fabricated using 3.3-V transistors of UMC (United Microelectronics Corporation) 130-nm mixed mode CMOS process with a thicker gate oxide layer. In this way the switches can support the required voltage swing.
  • FIG. 2 An embodiment of the subject T/R switch circuit is illustrated in Figure 2.
  • Stacked transistors can be used on the RX leg and can be used as shunt transistors for the TX node.
  • Figure 2 indicates three stacked transistors. However, the number of stacked series and shunt transistors can be modified. The number of transistors for the stacked transistors in the stacked series and stacked shunt can be the same number.
  • the transistors may be N- type or P-type. However, N-type transistors are preferred. In a specific embodiment where P-type transistors are used, isolated n-wells can be formed in a simpler way, e.g. a twin- well process.
  • An embodiment of the T/R switch can be implemented in a 130-nm mixed mode triple-well CMOS process.
  • the T/R switch circuit can be formed with a series transistor M4 on the TX leg, 3-stack transistors M6-M8 on the RX leg, shunt 3-stack transistors M1-M3 on the TX node, and a shunt transistor M5 on the RX node.
  • all the transistors use 3.3-V thick-gate-oxide MOSFETs.
  • the stacked shunt transistors M1-M3 and series transistors M6-M8 are used to improve the power handling.
  • all of the transistors can be implemented using sub-design-rule (SDR) channel length.
  • the transistors can be implemented using SDR channel length with lower on-resistance. Referring to the embodiment shown in Figure 2, the drawn length of transistors can be 0.26 ⁇ m instead of 0.34 ⁇ m currently required for 3.3-V transistors. Since the thin-gate- oxide and thick-gate-oxide layers for the 3.3-V and 1.2-V transistors in the process can be simultaneously formed, the SDR channel length transistors can be formed without any process modifications.
  • SDR switches can be fabricated in foundry CMOS technologies with no extra cost. Specific embodiments of the switch do not utilize impedance transformation to increase IPidB and demonstrate the broadband characteristics. In addition, the peak-to-peak voltage the switch needs to handle is ⁇ 20 V at 30 dBm input power. In one embodiment, isolation of the transistors can be accomplished by locating the transistors in isolated p-wells to allow the body node to float and to follow the RF input. This increases IPi dB similarly to that which happens in switches fabricated in silicon on sapphire (SOS) and silicon on insulator (SOI) processes.
  • SOS silicon on sapphire
  • SOI silicon on insulator
  • the substrate resistance can be increased by using a p-well implantation block (for example, having a width of ⁇ 20 ⁇ m), using a small number (for example, 4 per transistor) of substrate contacts, and adding a 1 k ⁇ resistor in series with the substrate contacts as shown in Figure 3.
  • a p-well implantation block for example, having a width of ⁇ 20 ⁇ m
  • a small number for example, 4 per transistor
  • Embodiments of the subject switch can incorporate feed-forward techniques, as those taught in K. Miyatsuji, and D. Ueda, "A GaAs High Power RF Single Pole Dual Throw Switch IC for Digital Mobile Communication System," IEEE J. of Solid-State Circuits, vol. 30, no. 9, pp. 979-983, which is hereby incorporated by reference in its entirety, such as capacitors (shown as C3, C4, C5 and C6) between the drain and body nodes of M3 and M8 and between the drain and gate nodes of M3 and M8 as shown in Figure 2.
  • the feed-forward capacitors C3, C4, C5 and C6 can be metal capacitors. In one embodiment, the capacitors C3, C4, C5 and C6 can be MIM capacitors.
  • the body-to- substrate parasitic junction capacitances make the voltage swing unevenly distributed among the gates and bodies of 3-stack transistors.
  • M3 and M8 sustain higher gate-to-body and drain-to-gate voltages than Ml and M6.
  • the extra capacitances can help the body/gate nodes of M3 and M8 better follow the high swing nodes, and can make the voltage swing at TX and ANT nodes more evenly distributed among the gates and bodies of the stacked transistors. This enables the stack as a whole to withstand a larger voltage swing before any one transistor is turned on or damaged.
  • the metal capacitors can be formed using metal layers 1 through 3 and can be incorporated as part of the transistor layout.
  • TX and RX nodes as well as the sources of Ml and M5 can be biased at 3 V, and the switches can be turned on and off by varying the control voltage (G_TX, G_RX) from 2 to 6 V.
  • G_TX, G_RX control voltage
  • metal capacitors Cl and C2 which can be formed using metal layers 1 through 8, can be connected to the sources of Ml and M5 to block the DC current and provide AC ground.
  • the switches can be controlled using a circuit similar to that taught by R. Point et al., An RF CMOS Transmitter Integrating a Power Amplifier and a Transmit/Receive Switch for 802.11b Wireless Local Area Network Applications," Proc. of 2003 RFIC Symposium, pp. 431-434, Philadelphia, PA, which is hereby incorporated by reference in its entirety, and the control voltages can be generated using a voltage doubler.
  • a die photograph of the circuit is shown in Figure 4.
  • the active area is about 300 ⁇ m by 380 ⁇ m or ⁇ 0.1 mm 2 . This is ⁇ 6X smaller than the —0.6 mm 2 of the switch using an LC-tank connection to the body node as taught by N. A. Talwalkar et al. (2004).
  • IL of the 3- stack SDR switch is 0.5 and 1.0 dB for TX and RX mode, respectively.
  • a T/R switch, using only 2-stack 0.34- ⁇ m length transistors instead of 3-stack 0.26- ⁇ m length transistors is also measured for comparison.
  • the non-SDR CMOS T/R switch's IL of RX leg is ⁇ 0.2 dB higher than that for the switch using 3-stack SDR channel length transistors.
  • the isolation of the SDR CMOS T/R switch is better than 29 dB for both TX and RX modes.
  • Figure 7 shows the linearity of the SDR CMOS T/R switch at 900 MHz.
  • the measured IP WB at the TX node is above 31.3 dBm, which is the highest IPi dB currently reported for bulk CMOS T/R switches. It is also ⁇ 5 dB higher than that for the switch with 2-stack 0.34- ⁇ m length transistors.
  • the UP 3 of the SDR CMOS switch is 42 dBm. When the source and drain nodes are biased at 0 V, IPm ⁇ drops to 26 dBm.
  • the linearity measurements of the SDR CMOS T/R switches with and without the additional feedforward capacitors are also compared in Figure 7.
  • the IPidB for the switch with the additional capacitors (extra capacitance) is ⁇ 1 dB higher.
  • the output power abruptly drops with input power and limits the power handling. This effect may be reversible in that when the input power is lowered, the output power is increased back.
  • the 3-transistor stack M1-M3 is breaking down. A positive consequence of this may be that when the switch is severely mismatched, the resulting high voltage will be clamped, thus protecting the switch from permanent damages.
  • the performances of the 3-stack SDR switch with capacitors and the 3-stack SDR switch without capacitors are summarized in the table shown in Figure 8.
  • IPid B is greater than 28 dBm, while IL is 0.8 and 1.2 dB for TX and RX legs at 2.4 GHz.
  • the reliability characteristics of the exemplary SDR CMOS T/R switch was examined by stressing the switch at IPidB for 10 hours. The stress was done for both when ANT pad is connected to 50- ⁇ load, and when it is left open to examine the effects of mismatch. The measured S-parameters showed no difference before and after the stresses.
  • embodiments of the present invention can be implemented for all FET processes such as MOSFET and MESFET.
  • the processes can include other processes such as SOI processes and GaAs based processes.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit de commutateur émission/réception (T/R). Dans un mode de réalisation préféré, des conceptions de circuit de commutateur T/R sont proposées qui augmentent IP1dB pour des commutateurs T/R tandis que IL est maintenue à moins de ~1 dB. Dans un mode de réalisation, le circuit de commutateur T/R peut incorporer un transistor en série sur la branche d'émission (TX), 3 transistors empilés sur la branche de réception (RX), 3 transistors empilés de dérivation sur le nœud TX, et un transistor de dérivation sur le nœud RX. Les transistors peuvent être formés à l'aide d'une longueur de canal en dessous d'une règle de conception (SDR) pour réduire une perte d'insertion (IL) et peuvent être situés dans des puits p isolés pour fournir un corps flottant amélioré. En outre, des condensateurs métalliques d'alimentation peuvent être inclus pour améliorer l'excursion de tension totale des transistors empilés. Ce circuit peut être mis en œuvre dans le procédé CMOS à triple puits en mode mixte à 130 nm UMC.
PCT/US2007/010295 2007-04-26 2007-04-26 Commutateur t/r à haute puissance utilisant des transistors empilés WO2008133620A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134665A (ja) * 2010-12-20 2012-07-12 Samsung Electro-Mechanics Co Ltd 高周波スイッチ
US10699961B2 (en) 2018-07-09 2020-06-30 Globalfoundries Inc. Isolation techniques for high-voltage device structures

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134665A (ja) * 2010-12-20 2012-07-12 Samsung Electro-Mechanics Co Ltd 高周波スイッチ
US8779840B2 (en) 2010-12-20 2014-07-15 Samsung Electro-Mechanics Co., Ltd. High frequency switch
US10699961B2 (en) 2018-07-09 2020-06-30 Globalfoundries Inc. Isolation techniques for high-voltage device structures

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