WO2008129786A1 - マルチプロセッサ制御装置、その制御方法および集積回路 - Google Patents

マルチプロセッサ制御装置、その制御方法および集積回路 Download PDF

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Publication number
WO2008129786A1
WO2008129786A1 PCT/JP2008/000579 JP2008000579W WO2008129786A1 WO 2008129786 A1 WO2008129786 A1 WO 2008129786A1 JP 2008000579 W JP2008000579 W JP 2008000579W WO 2008129786 A1 WO2008129786 A1 WO 2008129786A1
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WIPO (PCT)
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executable time
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PCT/JP2008/000579
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English (en)
French (fr)
Inventor
Shinichiro Nishioka
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Panasonic Corporation
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Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to JP2009510759A priority Critical patent/JP5235870B2/ja
Priority to EP08720465A priority patent/EP2073119A1/en
Priority to US12/377,938 priority patent/US8214662B2/en
Priority to CN2008800005135A priority patent/CN101542442B/zh
Publication of WO2008129786A1 publication Critical patent/WO2008129786A1/ja

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G06F11/3423—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time where the assessed time is active or idle time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)

Abstract

　本発明に係るマルチプロセッサ制御装置は、第１プログラムブロックのバリア同期開始からバリア同期成立までの第１バリア成立時間のうち第１ブロックが実行されない時間を表す第１非実行時間であってプロセッサ毎に表された第１非実行時間に関する第１非実行時間情報と、第２プログラムブロックのバリア同期開始からバリア同期成立までの第２バリア成立時間のうち第２ブロックが実行されない時間を表す第２非実行時間であってプロセッサ毎に表された第２非実行時間に関する第２非実行時間情報とを取得する取得手段と、取得手段において取得された第１及び第２非実行時間情報を用いて、第１及び第２プログラムブロックが連続して並列実行される間の各プロセッサへの電力供給を制御する電力制御手段とを備える。
PCT/JP2008/000579 2007-04-09 2008-03-13 マルチプロセッサ制御装置、その制御方法および集積回路 WO2008129786A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009510759A JP5235870B2 (ja) 2007-04-09 2008-03-13 マルチプロセッサ制御装置、その制御方法および集積回路
EP08720465A EP2073119A1 (en) 2007-04-09 2008-03-13 Multiprocessor control unit, its control method, and integrated circuit
US12/377,938 US8214662B2 (en) 2007-04-09 2008-03-13 Multiprocessor control unit, control method performed by the same, and integrated circuit
CN2008800005135A CN101542442B (zh) 2007-04-09 2008-03-13 多处理器控制装置、其控制方法及集成电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-101507 2007-04-09
JP2007101507 2007-04-09

Publications (1)

Publication Number Publication Date
WO2008129786A1 true WO2008129786A1 (ja) 2008-10-30

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PCT/JP2008/000579 WO2008129786A1 (ja) 2007-04-09 2008-03-13 マルチプロセッサ制御装置、その制御方法および集積回路

Country Status (5)

Country Link
US (1) US8214662B2 (ja)
EP (1) EP2073119A1 (ja)
JP (1) JP5235870B2 (ja)
CN (1) CN101542442B (ja)
WO (1) WO2008129786A1 (ja)

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JP2011022627A (ja) * 2009-07-13 2011-02-03 Hitachi Ltd 計算機システム、仮想計算機モニタ及び仮想計算機モニタのスケジューリング方法
JP2013502642A (ja) * 2009-08-18 2013-01-24 インターナショナル・ビジネス・マシーンズ・コーポレーション イベント・ドリブン・システムにおける非集中負荷分散の方法およびコンピュータ・プログラム
JP2013125549A (ja) * 2011-12-13 2013-06-24 Samsung Electronics Co Ltd ソフトリアルタイムオペレーティングシステムの実時間性を確保する方法及び装置
WO2014033941A1 (ja) * 2012-09-03 2014-03-06 株式会社日立製作所 計算機システムおよび計算機システムの制御方法
JP2015206931A (ja) * 2014-04-22 2015-11-19 富士通株式会社 データ処理方法、データ処理装置及びプログラム
JP2015210813A (ja) * 2014-04-24 2015-11-24 富士通株式会社 同期方法
JP2016012347A (ja) * 2014-06-27 2016-01-21 富士通株式会社 分散型コンピュータシステムでアプリケーションを実行する方法、リソースマネジャ、及び分散型コンピュータシステム
JP2016042232A (ja) * 2014-08-14 2016-03-31 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP6151465B1 (ja) * 2014-04-22 2017-06-21 クアルコム，インコーポレイテッド プロセッサコアの電力モードを制御するためのレイテンシベースの電力モードユニット、ならびに関連する方法およびシステム

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JP5206858B2 (ja) * 2011-11-24 2013-06-12 パナソニック株式会社 無線通信装置
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CN102521039B (zh) * 2011-12-08 2014-08-13 汉柏科技有限公司 网络通信产品的时间组实现方法及系统
US9563254B2 (en) 2011-12-22 2017-02-07 Intel Corporation System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time
US9594412B2 (en) 2012-03-30 2017-03-14 Intel Corporation Controlling power gate circuitry based on dynamic capacitance of a circuit
US9360909B2 (en) 2012-04-19 2016-06-07 Intel Corporation System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time
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JP5994601B2 (ja) * 2012-11-27 2016-09-21 富士通株式会社 並列計算機、並列計算機の制御プログラム及び並列計算機の制御方法
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011022627A (ja) * 2009-07-13 2011-02-03 Hitachi Ltd 計算機システム、仮想計算機モニタ及び仮想計算機モニタのスケジューリング方法
JP2013502642A (ja) * 2009-08-18 2013-01-24 インターナショナル・ビジネス・マシーンズ・コーポレーション イベント・ドリブン・システムにおける非集中負荷分散の方法およびコンピュータ・プログラム
JP2013125549A (ja) * 2011-12-13 2013-06-24 Samsung Electronics Co Ltd ソフトリアルタイムオペレーティングシステムの実時間性を確保する方法及び装置
WO2014033941A1 (ja) * 2012-09-03 2014-03-06 株式会社日立製作所 計算機システムおよび計算機システムの制御方法
JP2015206931A (ja) * 2014-04-22 2015-11-19 富士通株式会社 データ処理方法、データ処理装置及びプログラム
JP6151465B1 (ja) * 2014-04-22 2017-06-21 クアルコム，インコーポレイテッド プロセッサコアの電力モードを制御するためのレイテンシベースの電力モードユニット、ならびに関連する方法およびシステム
JP2017519274A (ja) * 2014-04-22 2017-07-13 クアルコム，インコーポレイテッド プロセッサコアの電力モードを制御するためのレイテンシベースの電力モードユニット、ならびに関連する方法およびシステム
JP2015210813A (ja) * 2014-04-24 2015-11-24 富士通株式会社 同期方法
JP2016012347A (ja) * 2014-06-27 2016-01-21 富士通株式会社 分散型コンピュータシステムでアプリケーションを実行する方法、リソースマネジャ、及び分散型コンピュータシステム
US10168751B2 (en) 2014-06-27 2019-01-01 Fujitsu Limited Method of executing an application on a distributed computer system, a resource manager and a distributed computer system
JP2016042232A (ja) * 2014-08-14 2016-03-31 富士通株式会社 演算処理装置および演算処理装置の制御方法

Also Published As

Publication number Publication date
US20100153761A1 (en) 2010-06-17
US8214662B2 (en) 2012-07-03
JP5235870B2 (ja) 2013-07-10
EP2073119A1 (en) 2009-06-24
JPWO2008129786A1 (ja) 2010-07-22
CN101542442B (zh) 2012-12-19
CN101542442A (zh) 2009-09-23

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