WO2008125708A1

WO2008125708A1 - Storage-free method and architecture for computing fft rotations

Info

Publication number: WO2008125708A1
Application number: PCT/ES2008/000220
Authority: WO
Inventors: Mario GARRIDO GÁLVEZ; Jesús GRAJAL DE LA FUENTE
Original assignee: Universidad Politécnica de Madrid
Priority date: 2007-04-12
Filing date: 2008-04-10
Publication date: 2008-10-23
Also published as: ES2283236B2; ES2283236A1; WO2008125708A8

Abstract

A storage-free method and architecture for computing FFT rotations makes it possible to compute the FFT decomposed according to the Cooley-Tukey algorithm without using stored data. The rotation angles of the FFT steps are generated by a single counter (1) and a circuit comprising adders and logic gates, eliminating the need to store data related to rotation angles. Rotations are computed using a modified CORDIC algorithm which makes it possible to simplify the micro-rotation computing blocks. Moreover, a system is disclosed which uses only two subtracters to compensate for the typical scaling of the CORDIC algorithm.

Description

Procedure and architecture without memory for the calculation of the rotations of Ia

FFT

Technical Sector

The invention described is framed within the field of signal processing, more specifically in relation to the elaboration of algorithms and the development of efficient circuit architectures for carrying out said algorithms. >

State of the art.

The Fourier transform is one of the fundamental operations in the field of signal processing, especially in spectral analysis. For its application in digital systems, the DFT (Discrete Fourier Transform) is used, which allows

The Fourier transform on data stored in a computer or sampled through an analog-digital converter, and whose formula is:

In the equation, the value N indicates the number of points on which the DFT is calculated, x [n] are the samples in the time domain, k is a discrete variable that represents the frequency, and X [k] is the signal in the frequency domain, which is defined for the values of .fe from 0 to N - 1. '

In order to calculate the DFT efficiently, the name FFT (Fast Fourier Transform) encompasses a set of algorithms that reduce the number of operations required by the DFT. Of all of them, the Cooley-Tukey algorithm [CT65] is the most used. This is based on decomposing the DFT into n = log _r N stages of cascading calculation, where r is the radix used in the decomposition. On the other hand, the decomposition can be performed following different methods. The most common are time decimated (DIT) and frequency decimated (DIF). In this way a reduction in the number of operations is achieved, which goes from an order 0 (N ² ) in the DFT, to an order O (Ñ \ og _r N) in the FFT.

Each of the n stages of the FFT is characterized by having to calculate a set of additions, subtractions and rotations in the complex plane. Addition and subtraction are carried out through elements called butterflies, and complex rotations through rotators.

Each butterfly receives r input data and offers r outputs that represent the FFT of r points of the inputs. As the 2-point FFT and the 4-point FFT can be performed by trivial rotations (0 ^or , 90 °, 180 ° and 270 °), the most common is to use radix 2 or 4 FFTs, since in other cases it is necessary include rotators inside the butterflies to carry out the non-trivial rotations that appear.

At each stage s of the FFT ₁ se {1. . . n}, N / r butterflies and N rotations are calculated. However, in the architectures of the FFT calculation circuits, all butterflies are usually calculated with a single circuit, taking advantage of the fact that the data arrives sequentially. The same goes for rotations: a single rotator is enough to carry out all the rotations of a stage. In this way, significant component savings are achieved. However, in the case of rotations it is necessary to know the angle of rotation (or any data related to it) that each of the samples that reach the rotator must be rotated.

There are two main methods for performing FFT rotations. The first is to rotate the input data by directly applying the formula of a rotation, using real multipliers and adders. The other option, more commonly used to require less resources in general, is to use the CORDIC algorithm, proposed by J.E. Volder [Vol59], and described briefly below.

The CORDIC algorithm is used to efficiently calculate complicated mathematical operations in digital systems. This algorithm is based on transforming these operations into a set of sums and displacements, which are easy to carry out in digital circuits.

If used to perform rotations in the complex plane, the CORDlC algorithm breaks down the angle of rotation, θ, into a sum of angles, α _τ :

M

where m and M are respectively the indices of the first and last angle considered, and is the error of the approximation and

Usually m = 0 and, therefore, the first angle is «o = tg ^{~ 1} (l) = 45 °, which makes the algorithm valid for any value of θ in the interval [—90 °, 90 ° ]. s When θ is outside this range, trivial rotations of 180 ° and 90 ° are used to place it. In fact, by these rotations it is possible to leave the remaining angle of rotation, z, in the range [-45 °, 45 °]. In accordance with this idea, it is possible to dispense with the 45 ° rotation and consider that the first rotation of the CORDIC algorithm is for the case m = l, where ai = tg ^{~ 1} (2 ^{~ 1} ) «26.5 °.

io The rotation of the input data to the rotator is carried out through a series of stages called micro rotations, in each of which an angle to _τ is rotated according to the equations:

X _{1 + 1} = x _τ - y _τ δ _ι 2 ^{~ τ}

Vτ + l = Vτ + Xιδ _τ 2 ^{~ l}

i5 where S ₁ indicates the direction of the micro rotation and is calculated according to:

S ₁ - SIgTi (Z ₁ ) Zι + i - Zi - S ₁ ^• a _τ

where sιgn (η) = 1 if η> 0, and sιgn (η) = - 1 if η <0. As S ₁ E {- 1, 1}, a rotation is made in each of the stages, either in the direction positive or in a negative sense. 20 This results in a constant gain in the rotator, which can be compensated, if necessary, simply by multiplying the output samples by:

MM

ι = mi = m

In order to properly rotate each of the rotator input data, the corresponding rotation vector values are stored in a memory, <5,

25 to each of the rotations that the rotator must perform. These data are read from the memory sequentially in such a way that each input data to the rotator is rotated by the corresponding rotation angle. When the number of rotations performed by the rotator of a certain stage of the FFT is high, the rotation memory must store a large amount of data, which negatively affects the area and the speed of the FFT. This problem is similar in the case of using multipliers to calculate the rotations, since

5 The sine and cosine values of the rotation angles must be stored.

Certain investigations have managed to reduce the memory of rotations to log ^ N [YCC06], or 0.5N [CP03]. In addition, other methods of decomposition of the FFT (other than the Cooley-Tukey algorithm) have been used to reduce the number of rotations to be calculated, as in [ZH05], where the decomposition method0 in prime factors is used, which is only applicable when the number of points of the FFT can be represented as a product of prime factors to each other.

On the contrary, with the proposed procedure and architecture, it is possible to replace the rotation memories of all stages of the FFT with a simple circuit consisting of a counter (unique for the entire FFT), and a few adders and logic gates. Thus, from the counter value, the rotations of all stages of the FFT are calculated taking advantage of common characteristics between them. In this way, it is possible to significantly improve the performance of the FFT, mainly in terms of area. In addition, the improvement is more significant the greater the number of points of the FFT that it is desired to calculate, which makes this procedure very suitable for the calculation of FFTs of a high number of points.

On the other hand, the rotations are calculated using a modification of the CORDIC algorithm that allows simplifying the blocks of calculation of the micro-rotations with respect to other existing options [MGBS02, Hu92].

DETAILED DESCRIPTION OF THE INVENTION s This invention presents a method for calculating the rotations of any decomposed FFT according to the Cooley-Tukey algorithm, and whose number of points, N, and radix, r, are both power of 2, with the following Steps:

«Obtain the sequences of rotation angles of all stages of the FFT,

• calculate the rotations corresponding to each of the stages of the FFT from of the generated rotation angles, where from a single counter the sequences of rotation angles are obtained, from all stages of the FFT. This procedure has the advantage that it is not necessary to resort to any previously stored data.

To implement the procedure, a circuit architecture is used that includes:

• An angle generation module that includes a single counter (1) for the entire FFT, from which the rotation angles of all stages of the FFT are obtained without resorting to any previously stored data, • a module of calculation of the rotations for each of the stages of the FFT. As will be seen later, the rotations of some of the FFT stages can be trivial, in which case the rotational calculation module of said stage can be dispensed with.

As explained above, an FFT of N points can be divided into n = log _r N stages, where r is the radix of the FFT. Assuming that both N and r are power of 2, the sequence of angles, (of length N) of any stage s of the FFT, is {1. . . n}, is, formed by N / r ^s equal sequences of length L = r ^s .

The sequence of angles depends on the radix chosen in the decomposition of the FFT. Thus, for radix 2, the length sequence L will be:

α _s = 0, 0, 0, 0,. . ., 0, 1, 2, 3,. . . ,

and for radix 4,

α _s =

By generalizing these expressions for any radix value, the sequence of angles can be generated by concatenating r sub-sequences:

; 0, ^,. . . , (T - "- ¹ - i) _P

where p = 0, 1, 2,. . . ? ^* - 1. To normalize the sequence of all stages of the FFT to the minimum angle of rotation, Θ _mιn {rad) = 2π / N, the values of the sequences must be multiplied by q = N / r ^a o, which is the same, shifted Iog ₂ (q) bits:

θ _s = q • a _s = 0, 0, 0, 0,. . ., 0, q, 2g, 3g,. . .

₂ 9-i 2 ³ - ¹ The sequence θ _s contains the rotation angles, θ, of the s stage of the FFT, and each rotation angle θ e [0, JV - 1], its equivalence in radians being:

, 0 ( _rα d) = ~ HE

From the digital point of view, this representation of θ as a value between 0 and JV-1 is advantageous for two reasons. First, the represented angle is exact and the number of bits used is minimal; If the angle of rotation is represented in radians, an error would always be made in the approximation because the number of bits is finite. On the other hand, the JV value is equivalent to a full circle turn, so that, since JV is a power of 2, multiplying by 2π radians becomes a bit shift.

Considering now that a counter is available, for any stage, s, of the FFT, the generation of the sequence of rotation angles of said stage, θ _s , is performed following the following steps:

• take the s • Iog ₂ τ least significant bits provided by the counter,

"of the bits taken, multiply the (s - 1) ^• achieve less significant bits by the most significant ones, thus obtaining the values of the sequence to _s . The most significant bits correspond to the value of p while the least significant they will count from 0 to (r ^{s ~ x} - 1).

"multiply the result by N / r ^s , thus obtaining the values of the sequence θ _s .

The explained method serves to generate both the angles of the DIT decomposition (decimated in time) and those of the DIF decomposition (decimated in frequency), considering that s - 1 is the input stage of the FFT in the case of the DIT decomposition , and the exit stage in the DIF case. To implement the generation of angles, the angle generation module represented in Figure 1 is used. The angle generation module comprises, in addition to the counter (1), the following elements:

• combinational logic (3), which operates on the counter value, m an accumulator block (4) for each stage of the FFT, for the calculation of the sequences at _s .

On the other hand, as can be seen in Figure 2, each accumulator block (4) comprises the following elements:

• an adder (43), which allows updating the values of the sequence at _a , m a register (45) that provides the values of the sequence at _s ,

• a logic gate (44) for the control of the accumulator block.

The counter (1) is a binary counter that counts from 0 to N - 1 periodically. This is considered divided into parts (2) of log bits. Each of them contains the p-value of one of the stages, and s ^ corresponds to the input (41) of the accumulator block of said stage. Specifically, the value of p for a stage s includes the bits ranging from the position (s - 1) ^• Iog ₂ (r) + 1 to the s • log% r of the counter, considering that the least significant bit is the bit 1

According to the structure of the accumulator block (4), the register (45) will increase according to the value of p provided that the control signal (42) is not activated.

On the other hand, the less significant (s - 1) • log ₂ r bits of the counter (1) perform a cyclic count from 0 to {r ^ ¹ - 1). When the count of these bits returns to zero, the control signal (42) is activated which causes the register value (45) to be set to zero, which provides the values of the sequence at _s .

Finally, the scaling blocks (5) do not include any logical components. This is because, being N and r powers of 2, the scaling factor q = N / r ^s represents only a fixed bit offset, for which only the interconnection of the bits with the next stage must be adjusted.

Thus, the generation of the rotation angle sequences θ _s of all stages of the FFT is carried out by means of a simple circuit that does not require any type of memory or the realization of multiplications. In addition, it is only necessary to use a single counter for the entire FFT, from which all the rotation angle sequences are generated.

The next step of the procedure described is the calculation of the rotations corresponding to each of the stages of the FFT from the generated rotation angles. The way to proceed is the same for each of the stages of the FFT, and is composed of the following steps:

"determine whether 180 ° and 90 ° rotations should be performed,

"calculate the rotation vector, δ, or obtain the adapted rotation vector δ ',

• rotate the rotator input data.

In the first place, for each rotation angle θ belonging to the sequence θ _{s it} is determined whether the 180 ° and 90 ° rotations must be performed in order to place the remaining rotation angle, z, in the algorithm definition interval CORDIC Note that as θ (rad) = -2πθ / N, the rotations should be done in the negative direction.

The fact of representing θ as an integer value, θ e [0, JV - 1], being JV power of 2, has the advantage that in the circuit architecture it is very easy to determine the 180 ° and 90 ° rotations that allow place the remaining angle of rotation z in the interval [- 45 °, 45 °]. To this must be added only to the set of the two most significant bits more significant than θ _t the next bit. In this way, the two bits resulting from the operation will indicate respectively if the 180 ° and 90 ° rotations must be performed. In addition, z is obtained directly by taking all the bits of θ except the two most significant and considering that z is expressed in complement to 2, and changed sign with respect to the angle in radians.

From z the rotation vector, δ, is determined according to:

δ _t = -sign (z _t ) Z ₁ ^ -I = Z ₁ + δ _t ^• a _%

being sign (η) = 1 if η> 0, and sign (η) = -1 if η <0. This calculation is made from Z ₀ = z in the case of using the micro rotation of αo = 45 ° (m = 0); and from z _\ - z yes the first micro rotation is considered to be that of Ct ₁ = tg ^{~ 1} (2 ^{~ 1} ) ∞ 26.5 °. The change of sign with respect to the usual procedure of the CORDIC is only due to the fact that, as mentioned above, the representation of the angle in the interval [0, N-I] has a sign opposite to the representation of the angle in radians.

The 180 ° rotations are easily calculated by changing the real and imaginary components of the input data, and the 90 ° one with a sign change and exchanging those components.

Usually, from the values of d, and once the 180 ° and 90 ° rotations have been applied to the rotator input data, the micro rotations are carried out according to the equations:

x _{ι +} i - X ₁ - y _ι δ _ι 2 ^{~ ι} Vι + i = Vι + «A2 ^{" 1}

However, it is possible to modify this procedure to reduce the complexity of the rotation calculation module. With this idea, a step is proposed in which the adapted rotation vector, δ ', is obtained from the rotation vector, δ, in the following way:

δ [= -δ _t - δ _t -ι, ι = m + l,. . ^{ . , M δM + l = ^δ M where m is the index corresponding to the first micro rotation and M the one corresponding to the last micro rotation.

Once the vector δ 'is obtained, the calculation of the micro-rotations is carried out in the following way:

+ 6,: -1

{{h + a, Si ^ i = = 1

where O ₁ and b _{z are} the inputs of the ¿th micro-rotation stage. The entries to the first micro-rotation stage, at _m and b _m , will be worth:

Om = XlN b _m = V IN being XIN and VIN respectively the real and imaginary part of the data on which there are 5 micro-rotations. On the other hand, χouτ and youτ, respectively the real and imaginary part of the data resulting from applying the micro-rotations, will be worth:

The rotational calculation module of the FFT is represented in Figure 3 and is composed of the following blocks:

"a generator of the rotation vector (6),

"a rotation vector adapter (7),

"180 ° and 90 ° rotation calculation blocks (8),

"several blocks of calculation of micro rotations (9).

i5 The generator of the rotation vector (6) determines whether the rotator input data has to be rotated 180 ° and / or 90 ° and obtains the rotation vector, δ, all from the rotation angle, θ, that Ie arrives from the angle generation module.

Next, the rotation vector adapter (7) calculates the adapted rotation vector, δ ', from the rotation vector, δ, according to the procedure described 20. From the digital point of view, the values of δ _t and δ _t 'are represented with a bit, which can take the value' 0 'or' 1 ', instead of the values'-1' and T described in the process. Taking this into account, in the implementation of the architecture, the procedure is transformed into: δ _m '= δ _m

2s δ [= S ₁ XOR δ _t -i, i = m + l,. . . , ^' M δ _M ' + i = δ _M. The 180 ° and / or 90 ° rotations calculation blocks (8) rotate the input data those angles (in the negative direction) if necessary, according to the value of θ. The rotation of 180 ° can be done by changing the sign of the real and imaginary components of the data and the one of 90 ° with a change of sign and exchanging said components.

Figure 4 shows the scheme of the microarotation calculation block (9). The inputs (91) and (92) correspond respectively to the values of a _t and b _% described in the procedure, while the switch (93) is controlled by the signal δ [(94). After the switch, the data is shifted and positions (95). Since the value is fixed for each micro rotation stage, the signals are wired, which does not constitute any physical element. Finally, the circuit consists of an adder (96) and a subtractor (97).

Thus, it is possible to simplify the calculation blocks of the micro-rotations (9) being only necessary a switch (93), an adder '(96), and a subtractor (97) in each of them.

As stated earlier, the rotated data leaves the scaled circuit by a constant factor and, therefore, can be compensated. In the case of m = 1 the compensation factor will be:

M

K = J [cos (tg- ¹ (2- ')) «0.8588

considering that cos (tg ^{~ 1} (2 ^{^ 1} )) «1, Vi> M, which is a good approximation for M ≥ 7. Thus, taking into account that:

K = 0.8588 ∞ 0.8594 = 1 - 2 ^{~ 3} - 2 ^{~ 6}

The scaling compensation can be done exclusively using two subtractors.

Therefore, in the case that the first block of calculation of the micro-rotations is the one corresponding to a _\ ~ tg ^'1 (2 ^{~ ι} ), an additional scaling compensation module consisting of two subtractors can be added. Brief description of the drawings

Figure 1: Scheme of the angle generation module, which includes a counter (1), combinational logic (3), accumulator blocks (4) and scaling blocks (5).

Figure 2: Scheme of the accumulator block (4), which is composed of an adder (43), s a register (45) and a logic gate (44).

Figure 3: Scheme of the rotation calculation module, which includes a generator of the rotation vector (6), an adapter of the rotation vector (7), calculation blocks, of the 180 ° and 90 ° rotations (8) and calculation blocks of micro rotations (9).

Figure 4: Scheme of the micro-rotation calculation block (9), which is composed of a switch (93), shifters (95), an adder (96) and a subtractor (97).

Exhibition of an embodiment of the invention

Next, the invention is explained for the case in which the rotations of an FFT of 8 points and radix 2 are calculated. As N = 8, the counter will count cyclically from 0 to 7, and will be increased in each clock cycle. The number of stages of the FFT considered i5 will be n = log _r N = 3 and, therefore, be {1, 2, 3}. . '

The following table shows the way to obtain the rotation sequences θ _s from the values taken by the counter. .

Counter s = 1 s = 2 s = 3

Dec. Bin. Pi ai θl P2 α ₂ - ^" 02 Pz α ₃ θ ₃

0 000 0 0 0 0 0 0 0 0 0

1 001 1 0 0 0 0 0 0 0 0

2 010 0 0 0 1 0 0 0 0 0

3 011 1 0 0 1 1 2 0 0 0

4 100 0 0 0 0 0 0 1 0 I heard.

25, 5 101 1 0 0 0 0 0 1 1 1

6 110 0 0 0 1 0 0 1 2 2

7 111 1 0 0 1 1 2 1 3 3 The first two columns of the table indicate the value of the counter in decimal and in binary respectively. As we are working with radix 2, the value of p \ corresponds to that of the least significant bit of the counter, that of ψi with the next, and that of P ₃ with the most significant.

To get the sequence a _? , the value of the two least significant bits of the counter is taken and multiplied by p ₃ ¡to obtain a-is the least significant bit of the counter multiplied by ^; and «i is always zero, as should happen in all FFTs for s = 1.

On the other hand, θ _s = q _s • a _s , where q _s = N / r \, so that gi = 4, q¿ - 2 and q $ - 1.

From the table you can also understand the operation of the circuit architecture that carries out the procedure. Thus, for example, the sequence at ₃ begins with O 'and increases with the value of p $. When the counter reaches 4, as the two least significant bits are worth zero, the sequence is reset and then increased again with the value of P ₃ until the counter returns to 0, where the sequence is reset again.

To understand the rotation system we will take the case where en = 3 = B '011, which corresponds to an angle in radians:

Adding to the two most significant bits of θ, '01', the next bit, '1', we obtain the valqr '10', so it will be necessary to perform a 180 ° rotation, which will place the remaining angle at z - τr /4.

From z the rotation vector is obtained which, in case m = l and M = 8 will be worth:

δ = 1, 1, 1, -1, 1, -1, -1, 1

The adapted rotation vector is calculated in accordance with the procedure described:

$ M + 1 SM resulting:

δ '= 1, -1, -1, 1, 1, 1, -1, 1, 1

Considering now that the rotator input data is the complex number 10 + 3j, the 180 ° rotation will be applied first, so that the inputs to the first micro-rotation stage (for m = 1) will be:

ai = -10 h = -3

Applying the procedure for calculating micro-rotations:

ι being δ 'the adapted rotation vector that has been calculated, and M = 8, the output values are obtained:

i5. XOUT = —5.80

VOUT = -10.69,. ^,

'' i

You can easily verify that the angle that the input data has been rotated is:

^' ' θ (rad) = -2,3593 PS -—

'. ' 4

20 On the other hand, the output data module is scaled with respect to the input data module, and it is possible to compensate it by multiplying the output by K = 1 - 2 ^{~ 3} - 2 ^{~ 6} . It is also possible to perform scaling compensation at the entrance of the FFT or at any intermediate point of the FFT.

To perform the compensation, the data to be multiplied by K will be taken, the same data shifted by 3 bits and finally the data shifted by 6 bits. They will then be subtracted from the data without shifting the offset values. Thus, since the bit shifts are fixed, only two testers are needed to carry out the scaling compensation.

Industrial application

Because the FFT is an algorithm widely used in information and communications technologies, the presented invention can be applied in numerous communications and signal processing systems. In particular, the proposed architecture is useful when it is intended to build FFTs on hardware platforms, such as FPGAs (Field Programmable Gate Array). On the other hand,

The invention provides a great advantage over other designs in applications where it is necessary to calculate FFTs of a high number of points.

References

[CP03] Yun-Nan Chang and Keshab K. Parhi. An efficient pipelined FFT architecture. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50: 322-325, Jun 2003.

s [CT65] J. W. Cooley and J.W Tukey. An algorithm for machine computation of complex fourier series. Math Computation, 19: 297-301, Apr. 1965.

[Hu92] • Y. H. Hu. CORDIC-based VLSI Architectures for Digital Signal Processing. IEEE Signal Processing Magazine, 9, Ju1 1992.

[MGBS02] K. Maharatna, E. Grass, S. Banerjee, and A. Sundar. CORDIC UNIT. Patent "US 20060059215A1, 20.12. 2002

[Vol59] J. E. Volder. The CORDIC trigonometric computing technique. IRE Trans. Electronic Computers, EC-8: 330-334, Sep. 1959.

[YCC06] Cheng-Ying Yu, Sau-Gee Chen, and Jen-Chuan Chih. Efficient CORDIC Designs for Multi-Mode OFDM FFT. Proc. IEEE International Conference on is Acoustics, Speech and Signal Processing, 3: 1036-1039, May 2006.

[ZH05] Li Zou and Xiao Huang. 3780-point Discrete Fourier Transformation processor. EP Patent 1750206A1, 04.08. 2005

Claims

1. Procedure for calculating the rotations of any decomposed FFT according to the Pooley-Tukey algorithm, and whose number of points, N, and radix, r, are both power of 2, with the following steps: sm obtain the sequences of angles of rotation of each of the stages of the FFT,

• calculate the rotations of each of the stages of the FFT from the generated rotation angles, characterized in that the rotation angle sequences of all the stages of the FFT are obtained from a single counter, and for one stage Any, s, of the FFT, the generation of the sequence of rotation angles of said stage, θ _s , is performed by following these steps:

"take the least significant s • Iog2r bits provided by the counter,

• of the bits taken, multiply the (s - 1) • achieve less significant bits by the most significant loss log _' zr, thus obtaining the values of the sequence α _s ,

"multiply the result by N / r ^a , thus obtaining the values of the sequence θ _s .

2. Method according to claim 1, characterized in that for the calculation of the rotations of each of the stages of the FFT, the adapted rotation vector _t , δ ', is obtained from the rotation vector, δ, of Ia following form: 0 δ ' _m - δ _m δ [= -δi ^• Í _Í -I, i = m + l,. . . , M i δM + i ^[ - ^δ M where m is the index corresponding to the first micro rotation and M the one corresponding to the last micro rotation. Method according to claims 1 to 2, characterized in that for the calculation of the rotations of each of the stages of the FFT, the calculation of the micro rotations is carried out as follows:

6, - 0.2- * if <J (= -la _τ - b _τ 2 ^{~ ι} if δ [= 1 with _τ and b _{t being} the inputs of the z-th micro-rotation stage.

4. Circuit architecture for implementing the method described in claims 1 to 3, characterized in that it comprises: s «an angle generation module that includes a single counter (1) for the entire FFT, from which the rotation angles of all stages of the FFT without resorting to any previously stored data,

«A module for calculating rotations for each of the stages of the FFT.

5. Circuit architecture according to claim 4, characterized in that the angle generation module io comprises, in addition to the counter (1), the following elements:

"combinational logic (3), which operates on the counter value,

"an accumulator block (4) for each stage of the FFT, for the calculation of the sequences a _s .

6. Circuit architecture according to claims 4 and 5, characterized in that, i5 within the module for generating angles, each accumulator block (4) comprises the following elements:

• an adder (43), which allows updating the values of the sequence to _s , "a register (45) that provides the values of the sequence to _s , m a logic gate (44) for the control of the accumulator block.

A circuit architecture according to claims 4 to 6, characterized in that the rotational calculation module of the FFT comprises blocks of calculation of the micro rotations (9) consisting of a switch (93), an adder (96 ), and a subtractor (97).

8. Circuit architecture for the calculation of the rotations of the FFT according to the 25 claims 4 'to 7, characterized in that in the case that the first block of calculation of the micro rotations is the one corresponding to ai = tg ^{~ 1} (2 ^{~ 1} ), an additional scaling compensation module consisting of two testers can be added.