WO2016007069A1  Device and method for performing a fourier transform on a three dimensional data set  Google Patents
Device and method for performing a fourier transform on a three dimensional data set Download PDFInfo
 Publication number
 WO2016007069A1 WO2016007069A1 PCT/SE2015/050689 SE2015050689W WO2016007069A1 WO 2016007069 A1 WO2016007069 A1 WO 2016007069A1 SE 2015050689 W SE2015050689 W SE 2015050689W WO 2016007069 A1 WO2016007069 A1 WO 2016007069A1
 Authority
 WO
 WIPO (PCT)
 Prior art keywords
 dimensional data
 unit
 memory
 data set
 fourier transform
 Prior art date
Links
Classifications

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
 G06F17/10—Complex mathematical operations
 G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, KarhunenLoeve, transforms
 G06F17/141—Discrete Fourier transforms
 G06F17/142—Fast Fourier transforms, e.g. using a CooleyTukey type algorithm

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
 G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling therefor
 G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
Abstract
Description
Device and method for performing a Fourier transform on a three dimensional data set
TECHNICAL FIELD
The present invention relates to a device and method for performing a Fourier transform on a three dimensional data set.
BACKGROUND
The three dimensional Fast Fourier Transform (3D FFT) is often calculated one dimension at a time. This is realized by applying three ID FFTs, one in each dimension.
The problem when performing a 3D FFT in an environment which provides and demands a fixed number of samples per time unit at the input and output respectively is the data management involved when performing the data permutations required to constantly provide correct order of input samples to the different ID FFT blocks.
Mario Garrido. "Efficient Hardware Architectures for the Computation of the FFT and other related Signal Processing Algorithms in Real Time." PhD thesis, Universidad Politecnica de
Madrid, Spain, 2009 describes an existing design wherein 2D FFT is performed in that the first permutation which takes place between the first FFT and the second FFT is a simple matrix transposition, that is, the rows and columns of a two dimensional matrix are changing place. This is a wellstudied problem that often occurs in mathematics, and hardware that performs this permutation efficiently has been designed.
Also S. Langemeyer, P. Pirsch, and H. Blume. "Using SDRAMsfor twodimensional accesses of long 2" x 2^{m} point FFTs and transposing.", In Proc. Int. Embedded Computer Systems (SAMOS) Con pages 242248, 2011 describes an existing design 2D FFT is performed in that the first permutation which takes place between the first FFT and the second FFT is a simple matrix transposition, that is, the rows and columns of a two dimensional matrix are changing place.
Existing 3D FFT designs store three dimensional data on a memory and perform the required operations on data fetched iteratively from the memory, i.e. the algorithm is calculated by reading some data from the memory, process these data and writing back the result to the memory. This is done iteratively until all calculations of the algorithm have been carried out. This means that all or almost all data have to be available before calculation can start and that no or almost no results are provided before being finished. This implies that there will be a delay while the memory is filled with input samples. Further, it will be necessary to read from and write to the same memory locations various times which increases the amount of memory accesses. Further, there will also be a delay while the memory is emptied before next calculation can be started. The memory bottleneck of loading and unloading data to and from the same memory can be reduced by double buffering, which means that two memories are used instead of one in order to increase the memory throughput. It will then be possible to access the two memories simultaneously so that the calculations can be performed using one memory while from the other the previous result is unloaded and later filled up with new data to be calculated. However, this solution almost doubles the amount of resources since these memories form a major part of the design. In addition, this iterative approach is suitable for processing data that arrives in bursts, but is not suitable for processing a continuous flow of data.
ChiLi Yu, K. Irick, C. Chakrabarti and V. Narayanan. "Multidimensional DFT IP generator for FPGA platforms." 58(4):755764, 2011 describes an existing 3D FFT design which stores three dimensional data on a memory and carries out the required operations on data fetched iteratively from the memory as described above.
U. Nidhi, Kolin Paul, Ahmed Hemani and Ansul Kumar. "High performance 3DFFT
implementation." 2013 describes a way of partially tackling this problem when computing on a supercomputer or a network of processing elements. The solution is to load the data onto local memories of the different processing elements and to carry out the permutation between the first and second FFTs locally. Then, the permutation between the second and third FFTs is performed with the aid of an interconnection network, wherein the permutation between the second and third FFTs is performed by sending data back and forth between the different processing elements. This solution is suitable when all data are available at start of calculation. If it is to be applied to real time processing the input data are first buffered and loaded onto the processing elements and then the next input data are buffered while performing all calculations. This approach requires one full size memory and a number of smaller memories since all processing elements need to store a portion of the data locally. Further, the throughput (samples per time unit) is very limited since all processing elements have to finish before the next FFT calculation can be started and also the result has to be unloaded from all the processing elements putting tough constraints for high throughput on the interconnection network.
Further, in handling large amounts of data, an external memory would typically be used. In an application as described herein, the memory would in many cases have the size of hundreds of megabytes. To enable high throughput, a fast memory would be desirable. These two requirements of a both large and fast memory lead in the contemporary available
architectures to the use of dynamic memories. However, this class of memories has to be managed in a correct way in order not to lose data, and they typically present constraints on how to access the data stored in them. Existing designs propose solutions for handling these constraints for matrix transposition but this problem has not been addressed for general permutations and permutations of more than two dimensions yet.
SUMMARY
One object of the present invention is to improve the way of determining a Fourier transform. This has in one embodiment been solved by means of a device for performing Fourier transform on a three dimensional data set. The device comprises a first one dimensional Fourier transform unit, a first data permutation unit, a second one dimensional Fourier transform unit, a second data permutation unit, and a third one dimensional Fourier transform unit.
The first one dimensional Fourier transform unit is arranged to receive the three dimensional data set as one dimensional data blocks related to a first spatial dimension and to perform a Fourier transform for the first spatial dimension based on the samples of the respective data blocks related to the first spatial dimension. The first data permutation unit is arranged to receive an output from the first one dimensional Fourier transform unit and to provide the three dimensional data set as one dimensional data blocks related to a second spatial dimension. The second one dimension Fourier transform unit is arranged to receive the one dimensional data blocks related to the second spatial dimension and to perform a Fourier transform for the second spatial dimension based on the samples of the respective data blocks related to the second spatial dimension. The second data permutation unit is arranged to receive an output from the second one dimensional Fourier transform unit and to provide the three dimensional data set as one dimensional data blocks related to a third spatial dimension. The third one dimension Fourier transform unit is arranged to receive the one dimensional data blocks related to the third spatial dimension and to perform a Fourier transform for the third spatial dimension based on the samples of the respective data blocks related to the third spatial dimension.
The first or second data permutation unit is arranged to associate a delay to each received sample determined so as to reorder readout of the samples to provide the one dimensional data blocks related to the second or third spatial dimension.
The device is in one example used for calculating a 3D FFT. Each of the spatial dimensions of the three dimensional data set corresponds to one of the dimensions of the 3D FFT.
The device is in one example used for calculating a 2D FFT. In accordance with this example, two of the spatial dimensions of the three dimensional data set correspond to one of the dimensions of the 2D FFT and the other spatial dimension of the three dimensional data set corresponds to the other dimension of the 2D FFT. Therefore, the two dimensions of the 2D FFT are interpreted as a three dimensional space.
The device is in one example used for calculating a ID FFT. In accordance with this example, all three spatial dimensions of the three dimensional data set correspond to the one dimension of the ID FFT. Therefore, the one dimension of the ID FFT is interpreted as a three
dimensional space. The Fourier transform is for example a Fast Fourier Transform, FFT.
This permutation of the first or second permutation unit can in one example be visualized as rotating the three axes, so that if the order of the axis before the permutation was Υ,Χ,Ζ, after the permutation the order will be Ζ,Υ,Χ. This problem has been solved for a continuous flow of samples.
The presented solution is based on pipelined calculation which continuously calculates the result. This makes it suitable for real time calculation since it can support continuous flow and the results do not need to be loaded to a memory before a new calculation can be carried out.
The provided solution is very resource effective. The design can easily be fitted together with other algorithms on the same FPGA or integrated circuit. As a continuous flow is maintained through all the processing elements in the circuit, there are always resources to calculate all three dimensions at all times. This is in contrast to known prior art systems which performs 3D FFT on a distributed system where calculations are performed in parallel on different processing elements, where all processing elements are involved in each dimension, preventing continuous flow. This difference is fundamental and present in all designs based on parallelization of the calculation of each dimension onto all processing elements in the design, which is the case for most (if not all) designs aimed for such networks of processing elements including supercomputers.
In one option, the first or second data permutation unit is arranged to reorder the samples so as to perform a three dimensional rotation.
This permutation of the first or second permutation unit can in one example be visualized as rotating the three axes, so that if the order of the axis before the permutation was Υ,Χ,Ζ, after the permutation the order will be Ζ,Υ,Χ. This problem has been solved for a continuous flow of samples. In one option, each sample of the three dimensional data set is associated to an index indicating its spatial position in the three dimensional data set and that the delay for the respective sample is determined in accordance with said index.
In one option, the first and/or second data permutation unit comprises at least one memory 870. The memory is for example a random access memory or a set of them, a dynamic memory or a set of them, a set of registers, etc.
In one option, the first or second permutation unit further comprises a controller arranged to control readout from and writing to the at least one memory so that readout of a sample from the memory and writing of a received sample is performed to the same memory position in the memory.
The memory bottleneck of loading and unloading data to and from the same memory has been avoided by this solution by always reading and writing to the same location in the memory.
In one option, the controller further comprises a counter arranged to count a predetermined number of clock cycles determined based on the number of spatial positions in the three dimensional data set and wherein the controller is arranged to control writing to and readout from the memory based on a counter signal from the counter. In a case wherein several inputs are handled in parallel, the number of clock cycles is also determined based on the number of samples handled in parallel.
In one option, the controller further comprises an address mapper unit arranged to receive the counter signal from the counter and to map the received counter signal to an associated memory position in the memory for reading and writing a sample.
In one option, the address mapping unit comprises a plurality of selectable mapping schemes and wherein the controller further comprises a mapping selector unit arranged to select one mapping scheme from the plurality of mapping schemes based on the counter signal and to provide a select signal indicating the selected mapping scheme. In one option, the controller further comprises a multiplexer arranged to receive the select signal from the mapping selector unit and to control output from the address mapper unit in accordance with the received select signal.
In one option, the first or second permutation unit further comprises an auxiliary permutation unit arranged to reorder samples read out from the at least one memory so as to permute locked bits in the memory.
One advantage with this solution is that the device can be used together with dynamic memories typically presenting constraints on how to access the data stored in them as the solution performs the required three dimensional permutation between the second ID FFT and the third ID FFT, (Fig. la) or between the first ID FFT and the second ID FFT (Fig. lb) in such a way that it is both made sure the permutation is correct and that the memory timings and regulations are taken into account and fulfilled.
In one option, the device is arranged to handle parallel inputs.
In one option, the device is arranged to perform three dimensional Fourier transform on the tree dimensional data set.
In one option, the device is arranged to perform Fourier transform on a cubic three dimensional data set. In one option, the device is arranged to perform three dimensional Fourier transform on the cubic three dimensional data set.
One embodiment of the disclosure relates to a method for performing Fourier transform on a three dimensional data set. The method comprises the steps of receiving the three dimensional data set as one dimensional data blocks related to a first spatial dimension performing a Fourier transform for the first spatial dimension based on the respective data blocks so as to provide the three dimensional data set Fourier transformed in the first dimension, providing the three dimensional data set as one dimensional data blocks related to a second spatial dimension, performing a Fourier transform for the second spatial dimension based on the respective data blocks so as to provide the three dimensional data set Fourier transformed in the first and second dimensions, providing the three dimensional data set as one dimensional data blocks related to a third spatial dimension, and performing a Fourier transform for the third spatial dimension based on the respective data blocks so as to provide the three dimensional data set Fourier transformed in the first, second and third spatial dimensions.
The step of providing the three dimensional data set as one dimensional data blocks related to a second or third spatial dimension comprises associating a delay to each received sample according to a permutation scheme, wherein the permutation scheme is determined so as to reorder the samples to provide the one dimensional data blocks related to the second or third spatial dimension.
In one option, the step of providing three dimensional data set as one dimensional data blocks related to a second or third spatial dimension comprises a step of controlling readout from and writing to at least one memory so that readout of a sample from the memory and writing of a received sample is performed to the same memory position in the memory. In one option, the step of providing three dimensional data set as one dimensional data blocks related to a second or third spatial dimension comprises a step of providing a counter signal counting a predetermined number of clock cycles determined based on the number of spatial positions in the three dimensional data set, wherein writing to and readout from the memory is controlled based on the counter signal. In one option, the step of providing the three dimensional data set as one dimensional data blocks related to a second or third spatial dimension comprises a step of mapping the received counter signal to an associated memory position in the memory for reading and writing a sample. One embodiment of the disclosure relates to software for executing the steps of the method for performing Fourier transform on a three dimensional data set in accordance with the above.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs la, lb, lc and Id show an overview of devices for performing a Fast Fourier Transform.
Fig 2 illustrates schematically an example of a three dimensional data set for transformation in device of Fig 1.
Fig 3 shows an example of a first FFT unit in a device of Fig 1. Fig 4 shows an example of a first permutation unit in a device of Fig 1. Fig 5 shows an example of a second FFT unit in a device of Fig 1. Fig 6 shows an example of a second permutation unit in a device of Fig 1. Fig 7 shows an example of a third FFT unit in a device of Fig 1.
Fig 8 shows detailed example of a second permutation unit in form of a 3D rotation unit. Fig 9 illustrates schematically the operation of a second permutation unit in form of a 3D rotation unit without memory constraints.
Fig 10 illustrates schematically an example of an operation on the respective samples of a three dimensional data set in a second permutation unit in form of a 3D rotation unit without memory constraints. Fig 11 illustrates schematically an example of an operation on the respective samples of a three dimensional data set in a second permutation unit in form of a 3D rotation unit with memory constraints.
Fig 12 is a flow chart illustrating a method for performing Fourier transform on a three dimensional data set. Fig 13 is a flow chart illustrating one example of a step in the method for performing a permutation with a memory.
Figs 14a. 14b and 14c illustrate schematically examples of different formats for the data set for input to a Fourier transform device.
DETAILED DESCRIPTION
Figures la and lb relate to three dimensional Fast Fourier Transform, 3D FFT, devices 100a, 100b arranged to calculate the three dimensional Fast Fourier Transform, 3D FFT, on a three dimensional data set, one dimension at a time. This is realized by applying three ID FFTs, one in each dimension, and providing the correct sequence of input data to the respective ID FFT so that the calculations are performed in the correct order.
The exemplified system of Fig la and lb aims for continuous flow applications. In the 3D FFT of Fig la, all rows are translated to columns in a 2D permutation between the first and the second FFT. In one example, the 2D permutation translates X, Y, Z to Y, X, Z.
Further, all three dimensions are rotated between the second FFT and the third FFT. This permutation can be visualized as rotating the three axes, so that if the order of the axis before the permutation was Υ,Χ,Ζ, after the permutation the order will be Ζ,Υ,Χ.
In the 3D FFT of Fig lb, all three dimensions are rotated between the first FFT and the second FFT. This permutation can be visualized as rotating the three axes, so that if the order of the axis before the permutation was Χ,Υ,Ζ, after the permutation the order will be Υ,Ζ,Χ which is a rotation in the opposite direction compared to Fig la. Further, all rows are translated to columns in a 2D permutation between the second and the third FFT. In one example, the 2D permutation translates Υ,Ζ,Χ to Ζ,Υ,Χ.
The input to the system may be continuous flow serial input data from real time applications such as e.g. motion detection in sequences of images or Synthetic Aperture Radar (SAR). The input to the system may also be data related to fluid dynamics, astrophysics, gene sequencing and molecular dynamics. The system can also be used as an accelerator for ordinary PCs that are performing 3D FFT. The dataset may be very large. The input may be configured in many ways. For example, it may have a single input where data come in series or several parallel inputs. In both cases data arrives in a continuous flow, i.e., the system receives one sample per clock cycle at each of the inputs.
In the example of Figs la and b, the three dimensional fast Fourier transform system 100a and 100b comprises a first ID Fourier transform determination unit 110, a first permutation unit 120, 140, a second ID Fourier transform unit 130, a second permutation unit 140, 120 and a third ID Fourier transform determination unit 150.
In one example, the first permutation unit 120 is a 2D translation unit and the second permutation unit is a 3D rotation unit 140. In one alternative example, the first permutation unit 140 is a 3D rotation unit and the second permutation unit is a 2D translation unit 120.
In the following description, reference is made to the example wherein the first permutation unit 120 is a 2D translation unit and the second permutation unit is a 3D rotation unit 140.
The first one dimensional Fourier transform (determination) unit 110 is arranged to receive the three dimensional data set as one dimensional data blocks related to a first spatial dimension. The first ID Fourier transform (determination) unit 110 is arranged to perform Fourier transform for the first spatial dimension based on the respective data blocks and to provide the three dimensional data set Fourier transformed in the first spatial dimension. The output from the first ID Fourier transform unit 110 is fed to the first permutation unit 120.
The first permutation unit 120 is arranged to receive the three dimensional data set Fourier transformed in the first spatial dimension as one dimensional data blocks related to the first spatial dimension and to provide the received three dimensional data set as one dimensional data blocks related to a second spatial dimension.
The second one dimensional Fourier transform (determination) unit 130 is arranged to receive the three dimensional data set as one dimensional data blocks related to the second spatial dimension. The second ID Fourier transform (determination) unit 130 is arranged to perform Fourier transform for the second spatial dimension based on the respective data blocks and to provide the three dimensional data set Fourier transformed in the second and first spatial dimension. The output from the second ID Fourier transform unit 130 is fed to the second permutation unit 140.
The two dimensional and three dimensional permutations performed by the permutation units 120, 140 of the system are adapted to the configuration of the input data. Further, the first and second 120, 140 permutation units may be connected differently in the system if the ID FFT units are adapted accordingly. Each block may then have a single input where data come in series or several parallel inputs. In both cases data arrives in a continuous flow, i.e., the system receives one sample per clock cycle at each of the inputs.
The first permutation unit 120 is arranged to operate in cooperation with one or a plurality of memories 160.
The second data permutation unit 140 is arranged to receive the three dimensional data set Fourier transformed in the second spatial dimension as one dimensional data blocks related to the second spatial dimension and provide the three dimensional data set as one dimensional data blocks related to a third spatial dimension. This will be discussed in detail later. The second data permutation unit is arranged to operate in cooperation with one or a plurality of memories 170.
The third one dimensional Fourier transform (determination) unit 150 is arranged to receive the three dimensional data set as one dimensional data blocks related to the second spatial dimension. The third ID Fourier transform unit 150 is arranged to perform Fourier transform for the third spatial dimension based on the respective data blocks and to provide the three dimensional data set Fourier transformed in the third, second and first spatial dimension. Thus, a 3D FFT is provided by the first ID Fourier transform unit 110, the first permutation unit 120, the second ID Fourier transformation unit 130, the second permutation unit 140 and the third ID Fourier transform unit 150.
The operation for computation of the three dimensional Fourier transform is in one example as follows. The formula of a 3D FFT for an input signal x[ni, n_{2}] is:
V V V  ί2π ^{1 1}  Ϊ2π ^{2 2}  Ϊ2π ^{3 3}
X[k k_{2}, k_{3}] = , n_{2}, n_{3}] e e ^{1} e ^{1 N}÷
η, η n_{9} =0 n, =0 where Ni is the number of rows of the matrix, N_{2} is the number of columns, and N_{3} is the number of heights. The equation is defined for ki = 0, 1, Ni1, k_{2} = 0, 1, N_{2}l and k_{3} = 0, 1, N_{3}l.
The 3D FFT can be performed as an FFT of each row of the matrix followed by an FFT of each column and followed by an FFT of each height, which can be observed by rewriting equation above as:
Therefore, it is possible to use three pipelined ID FFT units for the computation of the 3D FFT in real time. One of them calculates the FFT of the rows, other one obtains the FFT of the columns and the third one calculates the FFT of the heights. Common FFTs can be used as the lDFFTs for the computations of the respective blocks. In addition to this, two permutation modules are required. The first receives in one example the data row by row from the first FFT and provides them column by column, as required for the second FFT. This is equivalent to transposing the data matrix after the first FFT. The second permutation module receives data column by column and provides data height by height by performing the rotation as discussed herein.
In Fig 2 an example of the format of an input data set is illustrated. In the illustrated exampl each input data set comprises a 3D structure. The input data set forms a three dimensional matrix, wherein each position in the matrix is associated with a value. The number of samples in each spatial direction is in one example a power of two.
In one example, the samples of data are input rowwise (herein shown as the xdimension) for each layer in the third dimension (herein shown as the zdimension). The index information related to the position of the respective sample in the data set is not required as an input. In one example, starting information to start the computations can be provided before start of input of the data set or it can be provided in relation to each block. Figs 14a, 14b and 14c illustrate different examples of data sets for input to a device for performing Fourier transform on the data set. In Fig 14a, the data set is a three dimensional data set having a first Nl, a second N2 and a third N3 spatial dimension. In Fig 14b, the three dimensional data set has a first Nl, a second N2 and a third N3 spatial dimension, wherein the first and the second spatial dimensions correspond to one of the dimensions of a 2D FFT. In Fig 14c, the data three dimensional data set has a first Nl, a second N2 and a third N3 spatial dimension, wherein the first, second and third spatial dimensions all correspond to the same dimension of a ID FFT.
Figures lc and Id relate to Fast Fourier Transform FFT devices 100c and lOOd arranged to calculate the Fast Fourier Transform on a three dimensional data set, one dimension at a time. The calculation of the Fast Fourier transform is as described in relation to Figures la and lb realized by applying three ID FFTs, one in each dimension, and providing the correct sequence of input data to the respective ID FFT so that the calculations are performed in the correct order. In the same manner as the exemplified system of Fig la and lb, the exemplified system of Fig lc and lc aims for continuous flow applications.
The Fast Fourier Transform device 100c of Fig lc has the same parts as the Fast Fourier Transform device of Fig la or Fig lb. In order perform ID FFT and/or 2D FFT, the Fast
Transform Fourier device 100c of Fig lc is complemented with one or two rotation units 180a, 180b. The respective rotation unit 180a, 180b is in one example arranged to calculate the twiddle factors of the FFT. In a case wherein the Fast Fourier Transform device is arranged to calculate a 2D FFT, the Fast Fourier Transform device has one of a first rotation unit 180a and a second rotation unit 180b. The first rotation unit 180a, if present, is arranged between the first FFT unit 110 and the second FFT unit 130. The second rotation unit 180b, if present, is arranged between the second FFT unit 130 and the third FFT unit 150. In a case wherein the Fast Fourier Transform device is arranged to calculate a ID FFT, the Fast Fourier Transform device has both the first rotation unit 180a and the second rotation unit 180b. The first rotation unit 180a is arranged between the first FFT unit 110 and the second FFT unit 130. The second rotation unit 180b is arranged between the second FFT unit 130 and the third FFT unit 150. In the illustrated example of Fig lc, the first rotation unit 180a is arranged in the flow directly after the first FFT unit 110 and fed with the data from the first FFT unit 110. In the illustrative example of Fig lc, the second rotation unit 180b is arranged in the flow directly after the second FFT unit 130 and fed with the data from the second FFT unit 130.
The Fast Fourier Transform device lOOd of Fig Id has the same parts as the Fast Fourier Transform device of Fig lc. However, in the illustrated example of Fig Id, the first rotation unit 180a, if present, is arranged in the flow directly before the second FFT unit 130. In the illustrative example of Fig Id, the second rotation unit 180b, if present, is arranged in the flow directly before the third FFT unit 150.
In a not illustrated example, the first rotation unit 180a is arranged in the flow directly after the first FFT unit 110 and fed with the data from the first FFT unit 110 while the second rotation unit is arranged in the flow directly before the third FFT unit 150. In another not illustrated example, the first rotation unit 180a is arranged in the flow directly before the second FFT unit 130 while the second rotation unit 180b is arranged in the flow directly after the second FFT unit 130 and fed with the data from the second FFT unit 130. In Fig 3, a first ID Fourier transform determination unit 310 is arranged to determine a first one dimensional Fourier transform unit arranged to receive the cubic three dimensional data set as a one dimensional data blocks related to a first spatial dimension and to perform a Fourier transform for the first spatial dimension based on the respective data blocks. The first Fourier transform unit 310 is in one example arranged to receive blocks rowwise (first spatial dimension), to perform the ID Fourier transform on the respective received block and to output the results as rowwise blocks. In Fig 4, a first data permutation unit 420 in the form of a 2D transposition unit is arranged to provide the cubic three dimensional data set as one dimensional data blocks related to a second spatial dimension. In the illustrated example, the three dimensional data set is received rowwise and outputted columnwise. The first data permutation unit is arranged to cooperate with a memory 460.
In one example, the first permutation unit is arranged to manage all the samples of each 2D layer of the 3D data set. In one example it comprises 2D data sets formed by dimensions X and Y. Its complexity is of order Ni x N_{2}, where Ni is the number of samples in the first dimension and N_{2} the number of samples in the second dimension. Therefore, the memory 460 will take up a large area in general. External memories (not shown) may be used for storing all the samples. Due to realtime constraints, the system may receive a series of 2D data sets one after the other. Accordingly, the first permutation unit 120 may be capable of reading a 2D data set from the memory 160 and, at the same time, store samples of the following 2D data set.
The access to the memory 460 may be limited. In general, in small memories it is possible to read or write in any memory address. On the contrary, large memories are not so easily addressable. For instance, the access to external SDRAMs is performed by selecting a row and reading or writing samples in the columns of this row. A change in the row leads to an important overhead due to the fact that several commands need to be executed on the SDRAM in order to change the active row, which is needed before new data can be read or written. Therefore, it may not be advisable to write rows of the 2D data set in rows of the memory, since data would eventually have to be read column by column. Thus, this case demands a procedure for reading and writing that can efficiently use the memory 460. In an alternative example, additional hardware is included.
Thirdly, under certain circumstances several memories 460 are used in parallel instead of a single one. Considering that a memory characteristically achieves a throughput of one sample per clock cycle, a group of memories is used when several data are received in parallel.
Indeed, the throughput of a memory can be lower than one sample per clock cycle. This is for example the case of the external memories discussed above, which include overheads due to refresh or to activation of the rows of the memory. In this case, several memories in parallel can be used in order to meet the throughput of the system. Apart from the throughput adjustment, several memories are also used when the size of the 2D data set is larger than that of a single memory.
Fourthly, the 2D data set to be transposed can be square but also nonsquare. Further, a design problem can include any combination of the cited difficulties. For example, it could be necessary to design a circuit for the realtime transposition of a nonsquare 2D data set using several memories with access limitations with several inputs in parallel.
In Fig 5, a second ID Fourier transform determination unit 530 is arranged to determine a second one dimensional Fourier transform unit arranged to receive the three dimensional data set as a one dimensional data blocks related to the second spatial dimension and to perform a Fourier transform for the second spatial dimension based on the respective data blocks. The second Fourier transform unit 530 is in one example arranged to receive blocks columnwise (second spatial dimension), to perform the ID Fourier transform on the respective received block and to output the results as columnwise blocks. In Fig 6, a second permutation unit 640 in the form of a 3D rotation unit is arranged to provide the three dimensional data set as one dimensional data blocks related to a third spatial dimension. In the illustrated example, the three dimensional data set is received columnwise and outputted heightwise. The second data permutation unit 640 is arranged to cooperate with a memory 670. The second permutation unit 640 is arranged to perform a 3D rotation. It is arranged to perform the 3D rotation by storing values in the memory 670 using one mapping and reading them out using another. This is performed by associating a delay to each received sample, wherein each delay is determined so as to reorder the samples to provide the one dimensional data blocks related to the third spatial dimension. The second permutation unit 640 is further arranged to write new values into the locations that have just been read. In this way it saves memory and thereby both area and power consumption. Further, double buffering is avoided.
The memory 670 can comprise several memories for the same reasons as presented in the description of Fig 4 for memory 460.
In Fig 7, a third ID Fourier transform determination unit 750 is arranged to determine a third one dimensional Fourier transform unit 750 arranged to receive the three dimensional data set as a one dimensional data blocks related to the third spatial dimension and to perform a Fourier transform for the third spatial dimension based on the respective data blocks. The third Fourier transform unit 750 is in one example arranged to receive blocks heightwise (third spatial dimension), to perform the ID Fourier transform on the respective received block and to output the results as heightwise blocks. In Fig 8, a second permutation unit 840 in form of a 3D rotation unit is arranged to receive the 3D data set as one dimensional data blocks related to the second or first spatial dimension, and to associate a delay to each received sample determined so as to reorder the samples to provide the one dimensional data blocks related to the third spatial dimension. Accordingly, a three dimensional rotation of the data set is performed. The second permutation unit 840 in form of a 3D rotation unit comprises a memory 870. The memory is arranged to receive input data in the form of a three dimensional data set. A controller 845 is arranged to control readout from and writing to the memory 870. In one example, the controller 845 is arranged to control readout from and writing to the memory 870 so that readout of a sample from the memory and writing of a received sample is performed to the same memory position in the memory. This will be described in detail below.
The controller 845 comprises a counter 841 arranged to provide a count signal defining pace of operation of the second permutation unit. In one example, the counter is arranged to provide the count signal at the same pace as samples arrive at the input. In one example (not illustrated) a buffer is arranged to receive and buffer the received samples, or the samples to be sent to subsequent blocks, and guarantee reading or writing of data into the memory at the pace given by the counter 841. The controller 845 is arranged to control writing to and readout from the memory (170; 870) based on a counter signal from the counter 841. The counter 841 is arranged to count a predetermined number of clock cycles determined based on the number of spatial positions in the three dimensional data set. If the data set is handled in parallel, the predetermined clock cycles is also determined based on the number of parallel inputs. The three dimensional data set can then be associated to an index defined by the counter signal, said counter signal indicating the spatial position in the three dimensional data set of the respective sample. The delay for the respective sample is determined in accordance with said index. The controller 845 comprises further an address mapper unit 842 arranged to receive the counter signal from the counter 841 and to map the received counter signal to an associated memory position in the memory 870 for reading and writing a sample. In one example, the address mapper unit comprises one or a plurality of mapping schemes. Each mapping scheme defines a memory address position associated to each count value (i.e. index in the three dimensional data set). In one example, the mapping schemes comprise logical mapping schemes mapping each bit position in the count signal to a predetermined bit position in the memory address. Thus, the mapping scheme determines the read/write pattern in the memory.
In one example, the controller 845 comprises further a mapping selector unit 844 arranged to select one mapping scheme from the plurality of mapping schemes based on the counter signal. The controller 845 comprises further a multiplexer 843 arranged to receive the select signal from the mapping selector unit 844 and to control output from the address mapper unit 842 in accordance with the received selection signal.
In one example, the second permutation unit 840 further comprises an auxiliary permutation unit 846 arranged to reorder samples read out from the memory 870 so as to permute locked index bits in the memory. This may be necessary if the used memory is subjected to constraints in the flexibility in writing/reading data and the needed permutation therefore cannot be fully performed directly on the memory.
The second permutation unit 840 in form of a 3D rotation unit is arranged to operate as follows. The address mapper unit receives the bits from the counter and permutes them into address mappings. The number of mappings and their design depend on the constraints of the selected memory. The current mapping is determined by the mapping selector which keeps track on the number of frames or sets of 3D data that have been rotated. The mapping selector is arranged to keep track on the same amount of frames as there exists different address mappings. The mapping selector is arranged to circulate among these mappings in accordance with a predetermined selection scheme.
In Fig 9a, an example input to a second permutation unit in form of a 3D rotation unit which is arranged to receive the three dimensional data set as a one dimensional data blocks related to the second spatial dimension. In Fig 9b the output of a second permutation unit as one dimensional data blocks related to the third spatial dimension given the input in Fig 9a is presented. Accordingly, a three dimensional rotation of the data set is performed by this example of the second permutation unit. The examples illustrated in Figs 9a, 9b are simplified as the set of data comprises 4 samples in each dimension. Thus, each data in the 3D data has a relation in the data set described by two bits in each dimension. Thus, in order to index each sample of the data set, six bits are required. In Fig 10, reading out from and writing to a memory is illustrated when performed on an unconstrained memory. In the illustrated memory, the size of each dimension is 256 and hence the number of bits needed to index all samples is 8x3=24. The memory permutation is executed by writing data in a specific order and then read it in a different order so that the resulting output order is the wanted order. In order to maintain high memory bandwidth and sample throughput, new data is written to the same location as the permuted values are read. Thereby, use of double buffers can be avoided and area and power consumption can be reduced.
In the illustrated example, the memory receives one dimensional data blocks sorted as described in relation to Figure 9a and outputted as described in relation to Figure 9b. In Fig 11, a memory permutation is illustrated performed on a memory with three bits locked due to access constraints (indexes 108). In the illustrated memory the size of each dimension is 256 and hence the number of bits needed to index all samples is 8x3=24. The memory permutation is executed by writing data in a specific order and then reading it in a different order so that the resulting output is in the wanted order, or as close to the wanted order as possible. If it is not possible to achieve the full permutation on the memory, an auxiliary permutation 846 or correction circuit can be fed with the output from the memory. The address mapper is then arranged to provide as good mapping as possible given the constraints of the memory. Thus, some bits are locked in the memory and cannot be permuted by the address mapper. Those bits are permuted by the auxiliary permutation unit.
The auxiliary permutation unit is then arranged to permute the output samples which are not permuted by the address mapper.
Figure 12 illustrates an example of a method 200 for performing a three dimensional, 3D, Fourier transform on a three dimensional data set. The method comprises the steps of receiving S10 the three dimensional data set as a one dimensional data blocks related to a first spatial dimension, performing S20 a Fourier transform for the first spatial dimension based on the respective data blocks, providing S30 the three dimensional data set as one dimensional data blocks related to a second spatial dimension, performing S40 a Fourier transform for the second spatial dimension based on the respective data blocks, providing S50 the three dimensional data set as one dimensional data blocks related to a third spatial dimension, and performing S60 a Fourier transform for the third spatial dimension based on the respective data blocks. The step of providing S50 three dimensional data set as one dimensional data blocks related to a third spatial dimension comprises in the illustrated example associating a delay to each received sample according to a permutation scheme, wherein the permutation scheme is determined so as to reorder the samples to provide the one dimensional data blocks related to the third spatial dimension. In a not illustrated example, instead, the step of providing S30 three dimensional data set as one dimensional data blocks related to a second spatial dimension comprises associating a delay to each received sample according to a permutation scheme, wherein the permutation scheme is determined so as to reorder the samples to provide the one dimensional data blocks related to the second spatial dimension. In Figure 13, a step of providing S50 three dimensional data set as one dimensional data blocks related to a third spatial dimension in a method for performing three dimensional, 3D, Fourier transform on a three dimensional data set comprises the following steps:
A step of providing S51 a counter signal that counts a number of clock cycles determined by the number of spatial positions in the three dimensional data set, wherein writing to and readout from the memory (170; 870) is controlled based on the counter signal bits. He re C_{max} is the number of total memory accesses in one 3D data set and N_{max} is the total number of mappings. A step of mapping S52 the received counter signal to an associated memory position in the memory for reading and writing a sample.
A step of controlling S53 readout from and writing to at least one memory so that readout of a stored sample and writing of a received sample is performed to the same position in the memory.
Those steps are repeated until all the input data has been processed.
Claims
Priority Applications (2)
Application Number  Priority Date  Filing Date  Title 

SE1450880A SE539721C2 (en)  20140709  20140709  Device and method for performing a Fourier transform on a three dimensional data set 
SE14508808  20140709 
Publications (1)
Publication Number  Publication Date 

WO2016007069A1 true WO2016007069A1 (en)  20160114 
Family
ID=55064563
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

PCT/SE2015/050689 WO2016007069A1 (en)  20140709  20150615  Device and method for performing a fourier transform on a three dimensional data set 
Country Status (2)
Country  Link 

SE (1)  SE539721C2 (en) 
WO (1)  WO2016007069A1 (en) 
Cited By (1)
Publication number  Priority date  Publication date  Assignee  Title 

WO2018213438A1 (en) *  20170516  20181122  Jaber Technology Holdings Us Inc.  Apparatus and methods of providing efficient data parallelization for multidimensional ffts 
Citations (6)
Publication number  Priority date  Publication date  Assignee  Title 

US5339265A (en) *  19920831  19940816  University Of Maryland At College Park  Optimal unified architectures for the realtime computation of timerecursive discrete sinusoidal transforms 
US6073154A (en) *  19980626  20000606  Xilinx, Inc.  Computing multidimensional DFTs in FPGA 
US20040059889A1 (en) *  19980331  20040325  Macy William W.  Method and apparatus for performing efficient transformations with horizontal addition and subtraction 
WO2008125708A1 (en) *  20070412  20081023  Universidad Politécnica de Madrid  Storagefree method and architecture for computing fft rotations 
US20110107060A1 (en) *  20091104  20110505  International Business Machines Corporation  Transposing array data on simd multicore processor architectures 
US20140101409A1 (en) *  20121010  20140410  Altera Corporation  3d memory based address generator 

2014
 20140709 SE SE1450880A patent/SE539721C2/en unknown

2015
 20150615 WO PCT/SE2015/050689 patent/WO2016007069A1/en active Application Filing
Patent Citations (6)
Publication number  Priority date  Publication date  Assignee  Title 

US5339265A (en) *  19920831  19940816  University Of Maryland At College Park  Optimal unified architectures for the realtime computation of timerecursive discrete sinusoidal transforms 
US20040059889A1 (en) *  19980331  20040325  Macy William W.  Method and apparatus for performing efficient transformations with horizontal addition and subtraction 
US6073154A (en) *  19980626  20000606  Xilinx, Inc.  Computing multidimensional DFTs in FPGA 
WO2008125708A1 (en) *  20070412  20081023  Universidad Politécnica de Madrid  Storagefree method and architecture for computing fft rotations 
US20110107060A1 (en) *  20091104  20110505  International Business Machines Corporation  Transposing array data on simd multicore processor architectures 
US20140101409A1 (en) *  20121010  20140410  Altera Corporation  3d memory based address generator 
NonPatent Citations (1)
Title 

NIDHI, U. ET AL.: "High performance 3DFFT implementation''.", INGÅR I: CIRCUITS AND SYSTEMS (ISCAS), 2013 IEEE INTERNATIONAL SYMPOSIUM ON., 2013, pages 2227  2230, XP032446391, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6572319> [retrieved on 20150114] * 
Cited By (1)
Publication number  Priority date  Publication date  Assignee  Title 

WO2018213438A1 (en) *  20170516  20181122  Jaber Technology Holdings Us Inc.  Apparatus and methods of providing efficient data parallelization for multidimensional ffts 
Also Published As
Publication number  Publication date 

SE539721C2 (en)  20171107 
SE1450880A1 (en)  20160110 
Similar Documents
Publication  Publication Date  Title 

EP0313788B1 (en)  An aperiodic mapping method to enhance poweroftwo stride access to interleaved devices  
US7805587B1 (en)  Memory addressing controlled by PTE fields  
EP0263924B1 (en)  Onchip bit reordering structure  
US4189767A (en)  Accessing arrangement for interleaved modular memories  
US20120246380A1 (en)  Neighborhood operations for parallel processing  
US9940026B2 (en)  Multidimensional contiguous memory allocation  
US6968440B2 (en)  Systems and methods for processor memory allocation  
WO2001035419A1 (en)  Simultaneous addressing using singleport rams  
WO2011075170A1 (en)  System and method for storing data in a virtualized high speed memory system  
GB1532798A (en)  Computer memory systems  
EP1354484A1 (en)  Unit and method for memory address translation and image processing apparatus comprising such a unit  
US8793554B2 (en)  Switchable ondie memory error correcting engine  
US20040243656A1 (en)  Digital signal processor structure for performing lengthscalable fast fourier transformation  
US20120054468A1 (en)  Processor, apparatus, and method for memory management  
US8656401B2 (en)  Method and apparatus for prioritizing processor scheduler queue operations  
US20150089166A1 (en)  Reducing memory accesses for enhanced inmemory parallel operations  
KR20080107488A (en)  Interface for a block addressable mass storage system  
US4138720A (en)  Timeshared, multiphase memory accessing system  
KR101504781B1 (en)  Phase Change Memory in a Dual Inline Memory Module  
US4371949A (en)  Timeshared, multiphase memory accessing system having automatically updatable error logging means  
JP4861338B2 (en)  Improving the performance of the memory unit of the data processing apparatus by dividing the reading function and fetch function  
KR101386767B1 (en)  Apparatus and method for displaying a warped version of a source image  
US4174537A (en)  Timeshared, multiphase memory accessing system having automatically updatable error logging means  
US20080181040A1 (en)  Nport memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof  
US8533388B2 (en)  Scalable multibank memory architecture 
Legal Events
Date  Code  Title  Description 

121  Ep: the epo has been informed by wipo that ep was designated in this application 
Ref document number: 15818707 Country of ref document: EP Kind code of ref document: A1 

DPE1  Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)  
NENP  Nonentry into the national phase in: 
Ref country code: DE 

122  Ep: pct application nonentry in european phase 
Ref document number: 15818707 Country of ref document: EP Kind code of ref document: A1 