WO2008120079A2 - Improvement of defectivity of post thin layer separation by modification of its separation annealing - Google Patents
Improvement of defectivity of post thin layer separation by modification of its separation annealing Download PDFInfo
- Publication number
- WO2008120079A2 WO2008120079A2 PCT/IB2008/000747 IB2008000747W WO2008120079A2 WO 2008120079 A2 WO2008120079 A2 WO 2008120079A2 IB 2008000747 W IB2008000747 W IB 2008000747W WO 2008120079 A2 WO2008120079 A2 WO 2008120079A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- furnace
- temperature
- annealing
- phase
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Definitions
- the present invention relates to making composite structures for electronics, optics or microelectronics. More precisely, the invention relates to a method of detaching two substrates at an embrittlement zone situated at a given depth of one of the two substrates, the method comprising a separation annealing step implemented in a furnace, said annealing comprising
- the invention also relates to a Silicon On Insulator (SOI) type structure obtained by such a method.
- SOI Silicon On Insulator
- thermal separation annealing is thus one of the steps in the Smart CutTM method used to produce SOI type composite structures.
- the SOI surface (buried oxide layer and superficial silicon layer) is transferred from a donor substrate (previously oxidized and implanted) to a receiver substrate (which was bonded to the donor substrate).
- the donor substrate is detached from the receiver substrate.
- an SOI . type structure is obtained, that may also be designated as a "positive substrate” and a “residual substrate;” the residual substrate may be designated as a “negative substrate,” and may be recycled. It is specified that the separation annealing is implemented in a furnace. After separation annealing, a defect known as a "cleavage line" is sometimes observed.
- This defect may be characterized as follows: - the defect appears near the center of the negative substrate;
- the defect may cross through the entire thickness of this negative substrate
- the defect propagates by moving along the crystallographic directions of the crystal constituting the negative substrate; - the defect may propagate until a sufficient size to cause breakage of the negative substrate is reached.
- Such a “sufficient size” corresponds to the case where the defect propagates on the entire diameter of the substrate and the substrate then "spontaneously" breaks or to the case where the defect sufficiently weakens the substrate so that the substrate breaks during possible mechanical stress.
- the "cleavage line” defect may damage the positive substrate.
- the defect on the negative substrate may lead to the positive substrate being damaged.
- Figures 1a and 1b present maps of defects present on two SOI structures
- the negative substrate presents a complete "cleavage line” defect that led to breakage of the negative substrate.
- the negative substrate defect is definitely propagated on the SOI structure.
- the negative substrate presents the beginning of a "cleavage line” present in the center.
- the defect is also propagated on the SOI structure.
- the present invention proposes mitigating the abovementioned problems and particularly enabling the implementation of separation annealing allowing the "cleavage line" type defect on the positive substrate to be reduced.
- the invention proposes a method of detaching two substrates at the embrittlement zone situated at a given depth of one of the two substrates, the method comprising a separation annealing step implemented in a furnace, said annealing comprising a first phase during which the temperature changes along an upgrade allowing a high temperature to be reached and annealing at this high temperature to be stabilized, a second phase during which the temperature changes along a downgrade, at the end of which the furnace is opened, then the substrates are unloaded from the furnace, characterized in that the second phase is regulated so as to minimize temperature inhomogeneities at the surface of the detached substrates when the furnace is opened.
- aspects of this method are the following
- the period of the second phase is defined by a duration setting.
- the temperature of the furnace is regulated so as to change to a target temperature that is low enough to have not been reached at the end of the second phase, - during unloading, the temperature of the substrates is less than 200 0 C,
- this gas may be Nitrogen or Argon, the rate is equal to 12 slm before the furnace is opened and 20 slm at the end of the second phase and during the third phase,
- the target temperature is on the order of 50 0 C
- - the high temperature is on the order of 500 0 C
- the temperature decreases at a rate of 10°C per minute
- the invention relates to the application of a method of the invention for detaching a substrate whose diameter is equal to or greater than 300 mm.
- - Figure 2 illustrates a map of the surface roughness expressed in Haze measured by means of a piece of KLA Tencor SP2 inspection equipment on an SOI structure against which the negative substrate presented a "cleavage line" defect
- - Figure 3 illustrates the average temperature (dotted lines) measured in a furnace on an SOI structure during conventional separation annealing, as well as the gradient of this temperature (solid lines),
- FIG. 4 is a graph similar to that of Figure 3 for separation annealing according to the invention
- FIG. 5a and 5b illustrate maps of tearing-off type defects observed at the surface of an SOI after detachment by using conventional annealing and annealing according to the invention respectively
- FIGS. 6a, 6b and 6c illustrate diagrams of comparisons . between defects observed in an SP2 type measurement between populations of SOI structures obtained with conventional annealing and annealing according to the invention. SOD (defect at 0.15 ⁇ m) type defects are presented in Figure 6a. AC (defect at 0.5 ⁇ m) type defects are presented in Figure 6b. Tearing-off type defects in the center of the structure are presented in Figure 6c.
- the invention relates to a method of detaching two substrates at an embrittlement zone situated at a given depth of one of two substrates, the method comprising a separation annealing step implemented in a furnace, said annealing comprising
- the invention aims to prevent the appearance of "cleavage line" type defects.
- Figure 2 illustrates a map of the surface roughness expressed in Haze measured by means of a piece of KLA Tencor SP2 inspection equipment on an SOI structure against which the negative substrate presented a "cleavage line” type defect.
- a line is found that results from the support of the "damaged" negative substrate facing the positive substrate (that will provide the SOI structure) before separation of the substrates.
- the invention seeks to not lengthen the duration of the thermal annealing (and thus the duration of the method) compared to the conventional annealing known to the person skilled in the art.
- a temperature setting for the furnace to reach (for example on the order of 200 0 C, measured by temperature sensors placed at the bottom of the structure composed of the positive substrate and the negative substrate) and to wait until this temperature is reached before passing to the next step.
- the following step is the opening of the furnace for unloading the structure.
- the temperature of the substrates contained in the furnace may be higher. This is due to the molecular dynamics of the substrates cooling that is generally slower than the cooling of the furnace atmosphere (the differential being due to, in particular, the thermal inertia of the structures plus support assembly).
- opening the furnace leads to imposing a first thermal shock on the structures, which are at a high real temperature.
- opening the furnace door thus leads to the measured temperature of the furnace being lowered to under the temperature setting, and the furnace temperature regulation tends to start phasing in furnace heat in order to maintain the temperature at the temperature setting; this would impose a second thermal shock on the structures.
- the invention seeks to reduce the thermal constraints undergone by the structure during the end of its thermal separation annealing and particularly when the structure is removed from the furnace in view of limiting "cleavage line" defects. More precisely, separation annealing, and still more precisely, its second phase during which the temperature decreases, will be regulated so as to minimize temperature inhomogeneities at the surface of the substrates separated when the furnace is opened.
- the separation annealing will be interrupted at the end of a given duration and, in any case, well before the real temperature has decreased to the temperature setting value.
- the structure when the furnace is opened to unload the structure, the structure presents a low temperature with a low temperature gradient, which has the consequence of limiting the appearance of "cleavage line" defects.
- the invention thus sees to it that the substrates leaving the furnace do not undergo the effects of power bursts from the furnace, when the furnace seeks to regulate its temperature.
- Figures 3 and 4 illustrate the average temperature (dotted lines) measured on the structure in the furnace and the temperature gradient (solid lines) for conventional annealing and annealing of the invention, respectively.
- Thermal separation annealing is comprised of three periods, the first period corresponds to preconditioning of the bonding interface (period not discussed). Period Il presents two phases:
- the substrates are unloaded.
- Period III is a downgrade since at this time the structure is leaving the furnace and the structure continues to cool outside the furnace (area not discussed).
- the furnace setting is 200 0 C and when the furnace is opened, the temperature of the structure is higher than 200 0 C (approximately 250°C). In this case, the temperature of the structure is too high and, in addition, the structure undergoes thermal bursts, which leads to a "cleavage line" defect, as illustrated in Figures 1a, 1b and 2.
- the period of the second phase and the temperature setting of the furnace during the second separation annealing phase is defined to see that when the structure is unloaded from the furnace, the temperature of the structure is minimal, with a low gradient.
- the invention thus specifies that the furnace is opened, not when the furnace has reached a previously set temperature, but after a duration.
- this temperature is set at a temperature lower than that used in known separation annealings.
- the temperature setting is set at a very low value which will not be reached since the annealing will be interrupted beforehand.
- the temperature setting of the furnace is low enough to not have been reached at the end of the second phase of the thermal separation annealing.
- the temperature setting of the furnace may be set at 5O 0 C.
- this low temperature will not be reached by the furnace when the furnace is opened at the end of the second phase of period II.
- the temperature of the structure when the furnace is opened is, for example, less than 200 0 C.
- the temperature setting is lowered.
- the speed of the temperature reduction may, for example, be on the order of 10 0 C per minute.
- thermal annealings according to the invention may be conducted without lasting longer than thermal separation annealings from the prior art in conformance with the industrial constraints.
- gas is injected in the furnace and more precisely on the substrates.
- This gas is typically Nitrogen or Argon.
- the gas stream is 12 slm (standard liter per minute).
- 1 slm 1.666 1 ( T 5 m 3 .s "1 .
- This gas stream passes from 12 slm to 20 slm when the furnace is opened.
- the method of the invention enables "cleavage line” defects on structures formed from substrates with diameters equal to or greater than 300 mm to be reduced.
- the "cleavage line” defect problem appears especially when the substrates have large diameters (equal to or greater than 300 mm).
- Figures 5a and 5b illustrate maps of defects presenting tearing-off type defects by respectively using conventional annealing and annealing from the invention.
- Figures 6a and 6b respectively compare the particular defectivities at 0.15 ⁇ m and 0.50 ⁇ m recorded with a piece of KLA Tencor SP2 type equipment on these two SOI structure volumes.
- the discrepancy between the minimum value and the maximum value of the number of defectivities has reduced (between box plots 61 and 62 for particular defectivities at 0.15 ⁇ rri and between box plots 63 and 64 for particular defectivities at 0.50 ⁇ m).
- the surface of the structure issued from the detachment presents on average a number of particular defectivities at 0.15 ⁇ m and 0.50 ⁇ m on the order of 7 and 3, respectively.
- Figure 6c illustrates the occurrence of "cluster" type defects, that is, tearing-off defects at the center of the structure calculated from SP2 measurements via a dedicated algorithm.
Landscapes
- Heat Treatment Of Strip Materials And Filament Materials (AREA)
- Furnace Details (AREA)
- Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
Abstract
Description
Claims
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE112008000468.4T DE112008000468B4 (en) | 2007-03-29 | 2008-03-18 | Improving the defect frequency after thin film separation by modifying the separation heat treatment |
| US12/529,482 US8088671B2 (en) | 2007-03-29 | 2008-03-18 | Defectivity of post thin layer separation by modification of its separation annealing |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0754135A FR2914496B1 (en) | 2007-03-29 | 2007-03-29 | IMPROVING DEFECTIVITY POST DECOLUTION OF A THIN LAYER BY MODIFICATION OF ITS DECOLUTION RECOVERY. |
| FR0754135 | 2007-03-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2008120079A2 true WO2008120079A2 (en) | 2008-10-09 |
| WO2008120079A3 WO2008120079A3 (en) | 2013-07-18 |
Family
ID=38739398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2008/000747 Ceased WO2008120079A2 (en) | 2007-03-29 | 2008-03-18 | Improvement of defectivity of post thin layer separation by modification of its separation annealing |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8088671B2 (en) |
| DE (1) | DE112008000468B4 (en) |
| FR (1) | FR2914496B1 (en) |
| WO (1) | WO2008120079A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110890314A (en) * | 2018-09-11 | 2020-03-17 | 长鑫存储技术有限公司 | Preparation method of insulating layer of semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6276072B1 (en) | 1997-07-10 | 2001-08-21 | Applied Materials, Inc. | Method and apparatus for heating and cooling substrates |
| FR2839385B1 (en) * | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | PROCESS FOR TAKING OFF MATERIAL LAYERS |
| EP1429381B1 (en) * | 2002-12-10 | 2011-07-06 | S.O.I.Tec Silicon on Insulator Technologies | A method for manufacturing a material compound |
| EP1482548B1 (en) * | 2003-05-26 | 2016-04-13 | Soitec | A method of manufacturing a wafer |
| KR100571818B1 (en) * | 2003-10-08 | 2006-04-17 | 삼성전자주식회사 | Nitride-based light emitting device and its manufacturing method |
| EP1605504B1 (en) * | 2004-06-10 | 2011-05-25 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method for manufacturing a SOI wafer |
-
2007
- 2007-03-29 FR FR0754135A patent/FR2914496B1/en active Active
-
2008
- 2008-03-18 DE DE112008000468.4T patent/DE112008000468B4/en active Active
- 2008-03-18 US US12/529,482 patent/US8088671B2/en active Active
- 2008-03-18 WO PCT/IB2008/000747 patent/WO2008120079A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008120079A3 (en) | 2013-07-18 |
| DE112008000468B4 (en) | 2023-12-21 |
| DE112008000468T5 (en) | 2010-04-22 |
| US8088671B2 (en) | 2012-01-03 |
| FR2914496A1 (en) | 2008-10-03 |
| FR2914496B1 (en) | 2009-10-02 |
| US20100105217A1 (en) | 2010-04-29 |
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