Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
  • G11B20/1866—Error detection or correction; Testing, e.g. of drop-outs by interleaving
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/14—Digital recording or reproducing using self-clocking codes
  • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
  • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
  • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
  • G11B20/1803—Error detection or correction; Testing, e.g. of drop-outs by redundancy in data representation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes
  • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
  • H03M13/1515—Reed-Solomon codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
  • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
  • H03M13/2721—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions the interleaver involves a diagonal direction, e.g. by using an interleaving matrix with read-out in a diagonal direction
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/275—Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
  • H03M13/2909—Product codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
  • H03M13/53—Codes using Fibonacci numbers series
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/63—Joint error correction and other techniques
  • H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M5/00—Conversion of the form of the representation of individual digits
  • H03M5/02—Conversion to or from representation by pulses
  • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
  • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
  • H03M5/145—Conversion to or from block codes or representations thereof
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
  • G11B2020/1264—Formatting, e.g. arrangement of data block or words on the record carriers wherein the formatting concerns a specific kind of data
  • G11B2020/1265—Control data, system data or management information, i.e. data used to access or process user data
  • G11B2020/1287—Synchronisation pattern, e.g. VCO fields
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/14—Digital recording or reproducing using self-clocking codes
  • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
  • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
  • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
  • G11B2020/1446—16 to 17 modulation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
  • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
  • G11B2020/1836—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using a Reed Solomon [RS] code
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B2220/00—Record carriers by type
  • G11B2220/20—Disc-shaped record carriers
  • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
  • G11B2220/2508—Magnetic discs
  • G11B2220/2516—Hard disks
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B2220/00—Record carriers by type
  • G11B2220/20—Disc-shaped record carriers
  • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
  • G11B2220/2537—Optical discs
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B2220/00—Record carriers by type
  • G11B2220/90—Tape-like record carriers

Definitions

• the present invention relates generally to encoding data to be written to recordable media, and in particular, to providing reverse concatenation coding to product codes.
• ECC error-correcting codes
• Tape drives and CD devices employ powerful and complexity-efficient ECC, which is based on code concatenation of an outer C2-code and an inner Cl -code.
• the product code specified in the Linear Tape-Open, Generation 3 (LTO-3) standard is a particular instance of a concatenated coding scheme where both the inner and outer codes are RS-based codes of length 480 and 64, respectively as presented in TABLE I.
• Each 480-byte row comprises a codeword pair.
• the outer C2-code is an RS code over the Galois field GF (256), where N 2 denotes the length, K 2 the dimension, and d 2 the minimum Hamming distance of the code.
• the inner Cl -code is obtained by even/odd interleaving of an [240,234,7] Reed-Solomon (RS) code over GF(256).
• modulation codes are used to enable timing recovery from the read-back signal and to allow for short path memories in the detector without substantial performance loss.
• the ECC encoded data is passed through a modulation encoder.
• a modulation encoder 104 such as a 16/17 run length limited (RLL) encoder
• FC forward concatenation
• FC forward concatenation
• Fig. 2 is a block diagram of such an architecture 200.
• an RC architecture 200 the order of the ECC-encoder and modulation encoder is reversed such that the data is first passed through a modulation encoder 202 and the modulated data is ECC-encoded using a systematic encoder 204 for the error correcting code.
• the ECC parity symbols are either encoded using a second modulation encoder 206, as illustrated, or they are inserted into the data symbol stream at the bit level or symbol level. Inserting entire parity symbols into the data symbol stream is referred to as partial symbol interleaving.
• Parity insertion strategies result in simple schemes with no error propagation; however, such strategies may weaken the original modulation constraints. Nonetheless, there are three major benefits which make RC attractive: a) There is no error propagation through the modulation decoder. b) Because error propagation is not an issue, the first modulation code can be taken to be very long, allowing the use of capacity-efficient and high-rate modulation codes, and thereby resulting in code rate gains. c) In the read-back path, the ECC decoding block is located immediately after the channel detection block, which enables soft information to be passed from the detector to the decoder on a bit-by-bit basis. This creates the appropriate framework for using novel ECC techniques, which are based on turbo and LDPC codes and which hold the promise of large performance improvements. Furthermore, in this framework, parity post-processing schemes can easily be implemented.
• ECC Error Correction Code
• a preferred embodiment of the present invention provides a reverse concatenation encoding system for a recording write path.
• the system comprises means for generating a first data array of unencoded user data, a first modulation encoder to enforce a first modulation constraint on a respective row of the first data array and generate a second data array comprising modulation-constrained data.
• the system further includes a formatter operable to process the second data array by inserting predetermined empty locations in each column interleaved with the modulation-constrained data and generate a third data array.
• a C2-encoder is operable to compute a C2-parity byte for each of a plurality of the empty locations in each column of the third data array and generate a fourth data array.
• a Cl -encoder is operable to compute a Cl -parity symbol for each row of the fourth data array and generate a fifth array.
• the system further includes a second modulation encoder operable to impose a second modulation constraint on each Cl -parity symbol of the fifth data array and generate a sixth data array.
• the system further includes means for recording the rows of the sixth data array onto the tracks of a recording medium.
• Another preferred embodiment of the present invention provides a method for encoding data for recording onto media, comprising: generating a first data array of unencoded user data; imposing a first modulation constraint on each row in the first data array to generate a second data array comprising modulation-constrained data; formatting the second data array by inserting predetermined empty locations in each column of the second data array interleaved with the modulation-constrained data and generating a third data array; computing a C2-parity byte for each of a plurality of the empty locations in each column of the third data array and generating a fourth data array; computing a Cl -parity symbol for each row of the fourth data array and generating a fifth data array; imposing a second modulation constraint on each Cl -parity symbol of the fifth data array and generating a sixth data array; and recording the rows of the sixth data array onto tracks of a recording medium.
• a further preferred embodiment of the present invention provides a computer program product of a computer readable medium usable with a programmable computer, the computer program product having computer-readable code embodied therein for encoding data for recording onto media, the computer-readable code comprising instructions for: generating a first array of unencoded user data, the first data array; imposing a first modulation constraint on each row in the first data array to generate a second data array comprising modulation-constrained data; formatting the second data array by inserting predetermined empty locations in each column of the second data array interleaved with the modulation-constrained data and generating a third data array; computing a C2-parity byte for each empty location in each column of the third data array and generating a fourth data array; computing P Cl -parity symbols in each row and generating a fifth data array; enforcing a second modulation constraint on each Cl -parity symbol in each row and generating a sixth data array; and recording the rows of the sixth data array onto the tracks of
• FIG. 1 is a block diagram of prior art data encoding with forward concatenation
• Fig. 2 is a block diagram of prior art data encoding with reverse concatenation
• Fig. 3 is a block diagram of a prior art LTO-3 write path
• Fig. 4 is a high level block diagram of the reverse concatenation architecture of the present invention.
• Fig. 5 A is a block diagram of a write path in which the reverse concatenation architecture of the present invention may be incorporated;
• Fig. 5B is a block diagram of a portion of a write path of one embodiment of the present invention
• Fig. 6 is a more detailed block diagram of the reverse concatenation architecture of the present invention
• Fig. 7 illustrates a dataset array in which empty locations have been provided by the formatter of the present invention
• Fig. 8 is a functional diagram of a systematic second modulation encoder of the present invention.
• Fig. 9 illustrates the composition of a codeword quad following the encoding of data in accordance with the present invention.
• Fig. 10 is a block diagram of an alternative embodiment in which both unconstrained data bytes and parity bytes are inserted into empty locations provided by the formatter.
• Fig. 3 is a block diagram of a write path 300 according to the LTO-3 standard.
• Host records are compressed 302 and a data set and DSIT generator 304 generates subdata sets from the stream of symbols.
• An ECC encoder 306 provides ECC encoding and passes the encoded subdata sets to a codeword pair header and codeword quad generator 308.
• the resulting codeword quads are passed to a write formatter 310 in which a 16-track bit stream is generated.
• the bit stream is processed in a data randomizer 312 and then modulation encoded 314.
• the RLL encoded bit stream is transformed into a synchronized bit stream by inserting sync and formatting patterns in a sync generation block 316 and the synchronized bit stream is passed through a write equalizer 318, providing a bit stream which may then be recorded onto the media.
• the present invention 400 provides a reverse concatenation architecture in which the data is first passed through a serial/parallel block 401 to form an unencoded array. Each row of the array is modulation encoded in a first modulation encoder 402 and then an ECC is applied in an ECC encoder 404. Each row is either processed through a second modulation encoder 406 or subjected to partial symbol interleaving (not shown) to meet the required modulation constraints.
• Fig. 5A is a block diagram of a write path 500 in which the reverse concatenation architecture of the present invention may be incorporated.
• host records in the write path 500 of the present invention are compressed 502 and a data set and DSIT generator 504 generates subdata sets from the stream of symbols. The subdata sets are then randomized in a row- wise fashion in a data randomizer 506 and the randomized data passed to a first row-wise modulation encoder 508.
• C2 and Cl ECC encoders 510 encode the modulation encoded subdata sets, as will be described in more detail.
• a second modulation encoder 512 provides further modulation encoding to the encoded subdata sets after which the modulated data is processed by an interleaving and track assignment block 520.
• the resulting multi-track stream of Cl -codewords and codeword headers is transformed into a synchronized bit stream by inserting sync and formatting patterns in a sync generation block 514 and the synchronized bit stream is passed through a write equalizer 516, providing a write stream which may then be recorded onto the media 518.
• Fig. 5B is a block diagram of a portion of a write path of an embodiment of the present invention in which the interleaving and track assignment block 520 processes subdata sets into rows in the format for LTO-3 tape media.
• the interleaving and track assignment block 520 includes a codeword pair header and codeword quad generator 522 in which the modulated data from the second modulation encoder 512 are interleaved with codeword headers to form codeword quads.
• the interleaving and track assignment block 520 further includes a write formatter 524 which maps the codeword quads into logical tracks.
• the resulting 16-track bit stream is transformed into a synchronized bit stream by inserting sync and formatting patterns in the sync generation block 514 and the synchronized bit stream is passed through a write equalizer 516, providing a bit stream which may then be recorded onto the tape 530.
• a write equalizer 516 providing a bit stream which may then be recorded onto the tape 530.
• Fig. 6 is a more detailed block diagram of the RC architecture 600 of the present invention.
• the architecture 600 includes a set of high-rate modulation encoders 602, one for each of the N2 rows (also referred to herein collectively as "the modulation encoder 602") which receive data from a serial/parallel block 601, and an outer, column-by-column C2-encoder 604.
• the architecture 600 further provides a formatting block 606 interposed between the modulation encoders 602 and the C2 encoder 604.
• the format block 606 reorganizes the modulation encoded user data array such that its size is based on the length rather than the dimension of the outer code.
• C2 encoder 604 Following the C2 encoder 604 is an inner Cl encoder 608 for each row to generate parity bytes at the end of each row. Processing of the encoded rows is completed by a set of systematic modulation encoders 610. The data from the C2 encoder 604 and the data from second set of modulation encoders 610 are then multiplexed with in a multiplexer 612 to form the completed subdata set.
• the unencoded user data array of the present invention consists of M rows which are generated by the serial/parallel block 601.
• TABLE II is a modification of the subdata set array of the LTO-3 standard (TABLE I).
• the array contains 520 user bytes more than the conventional LTO-3 subdata set.
• Each row of the unencoded user data array is passed through the first modulation encoder 602 which imposes a modulation constraint at the input of the formatting block 606.
• the modulated user data array still contains M rows modulation-constrained data which are a few bytes longer due to the first modulation encoder 602.
• a dummy zero-bit is added at the beginning of the length-214 bit-sequence and, then, all sequences are encoded resulting in 15 bit-sequences all of length 216, which add up to a total of 405 bytes per row.
• the first modulation code transforms the unencoded user data array of TABLE II into the modulation-constrained user data array of TABLE III. TABLE III
• one selects for the first modulation code a code, which supports partial interleaving of unconstrained symbols such that predetermined global- G and interleaved-/ constraints are satisfied after partial symbol interleaving.
• the formatting block 606 transforms the modulated user data array of TABLE III into an array which has N2 - K2 empty components in each column.
• the N2 - K2 empty locations are the place-holding positions where the parity symbols to be generated by the C2 encoder 604 will be introduced.
• This Diophantine equation may make it necessary to adjust the parameters of the Cl-code.
• the parity bytes should be separated by a predetermined minimum amount in order to not fully destroy the modulation constraint of the first modulation code.
• 64 x 75 4800 C2-parity byte locations per parity pattern array.
• the insertion locations are specified by the following 10 linear equations (modulo 64), which relate the column indices x to the row indices
• each column contains Ni - 10 parity locations and such that the pattern repeats within as few columns as possible. In the example, the parity pattern repeats every 32 nd column. This particular parity pattern array is illustrated in Fig. 7 in which the plotted dots represent the 10 empty parity insertion locations for each column.
• each column may be encoded into a codeword of the rate-54/64 RS C2-code.
• the C2-encoder is also preferably be varying from column to column.
• the C2 code may be a Reed-Solomon code although other codes may also be used.
• the code is a maximum-distance separable code which has the useful property that every set of Ki components forms an information set. Thus, every set of Ki components uniquely determines the remaining Ni - Ki parity symbols.
• every column contains Ki modulated data bytes and Ni - Ki empty parity locations.
• the C2-encoder 604 determines the Ni - Ki parity bytes from the Ki modulated data bytes and inserts them at the empty parity locations.
• the output of the C2-encoder 604 is a C2-encoded array of size Ni x Ki, as illustrated in TABLE IV. The C2-encoded array satisfies a predetermined modulation constraint along each row.
• the C2-encoder is an encoder for a rate K 2 ZNi Reed-Solomon code over the Galois field GF (2 m ) and, in particular, the codeword components consist of m-bit symbols.
• the rows of the C2-encoded array are then passed through the Cl -encoders 608 for the Cl -code.
• the resulting Cl -parity symbols may either be processed by the second modulation encoder 610, as illustrated in Fig. 6, or be partially interleaved bit- wise or byte -wise into the data stream of the Cl-encoder 608.
• the even and odd parity bytes in a row are represented by asterisks and dots, respectively.
• the Cl -encoder may be obtained from an even/odd interleaved Reed-Solomon code of dimension K ⁇ and length Ni over GF (2 8 ).
• the Cl -encoder may be derived from a linear code over a Galois field GF(2 r ), i.e., with r-bit symbols, and which has dimension mK ⁇ over GF (2).
• the Cl -encoder may also be derived from a low-density parity-check code over a Galois field GF(2 r ) and which has dimension mK ⁇ over GF(2).
• the 12 Cl -parity bytes in each row are preferably passed through a systematic second modulation encoder 610 which adds a single modulation bit to the beginning of each of the Cl -parity bytes in each row.
• the modulation bit is preferably determined by inverting the second bit pi in each Cl -parity byte, which characterizes a secondary systematic encoder, and prepending it to the parity byte.
• codeword quads are assembled by a multiplexer 612 in a manner similar to the LTO-3 standard. As illustrated in Fig. 9, consecutive rows of C1/C2 encoded subdata sets 902A, 902B, such as the first and second rows, are interleaved with encoded headers 906A, 906B to form the first and second codeword pairs 902A, 902B, respectively.
• the two codeword pairs 902A, 902B comprise a codeword quad 900.
• the rate of the RC modulation scheme is:
• a typical forward concatenation architecture is based on a 16/17 code.
• RS Reed-Solomon
• Each row of the unencoded user data array is passed through the first modulation encoder 602 and, thus, satisfies a modulation constraint at the input of the formatting block 606.
• N 2 - K 2 16 "empty" components in each column.
• M 400
• the 12 parity bytes in each row are passed through a simple systematic second modulation encoder 610, which adds a single bit at the beginning of each parity byte.
• the second embodiment which is based on a C2-code of length 96 and dimension 80, has advantages over the previously described first embodiment, which is based on a C2-code of length 64 and dimension 54:
• the first modulation encoder 602 of the second embodiment is based on a rate- 199/200 Fibonacci code, whose length evenly divides the row-length of the modulated user data array and, thus, for each row one can apply 16 times the identical Fibonacci encoder in the second embodiment.
• the column-dependent C2-encoding is simpler for the second embodiment because the parity pattern repeats every sixth column and, thus, at most six different C2-encoders 604 are required whereas for the first embodiment the proposed parity pattern repeats only every 32 columns.
• the present invention further provides a third embodiment of an RC architecture which is based on partial interleaving of a predetermined number of unconstrained data bytes and illustrates the versatility of the empty locations generated by the formatting block 606.
• the C2-encoder inserts parity bytes into the empty locations.
• the empty locations may also be used in a different way: some may be filled with C2-parity bytes and some may be filled with unconstrained data bytes.
• Fig. 10 illustrates a block diagram of a RC architecture 1000 for product codes in which unconstrained data bytes are inserted into some of the empty locations provided by the formatter 606 and parity bytes are inserted into the remaining empty locations.
• the insertion of the unconstrained data bytes occurs prior to the C2-encoder because the C2-encoder needs these bytes for computing the parity bytes.
• the unconstrained data bytes are generated by a de-multiplexer 1002.
• the de-multiplexer 1002 splits the user data into one part that is processed by the first set of modulation encoders 602 and a second part that bypasses the first set of modulation encoders 602 and is processed by the insertion block 1004 prior to the C2-encoder 604.
• the Cl -code is selected in the same fashion as it is selected for the previously described first and second embodiments.
• the 12 parity bytes in each row are passed through a simple systematic second modulation encoder ME2 610, which adds a single bit at the beginning of each parity byte.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Probability & Statistics with Applications (AREA)
• Signal Processing (AREA)
• Mathematical Physics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Algebra (AREA)
• General Physics & Mathematics (AREA)
• Pure & Applied Mathematics (AREA)
• Error Detection And Correction (AREA)
• Signal Processing For Digital Recording And Reproducing (AREA)

Priority Applications (4)

Applications Claiming Priority (4)

Publications (1)

Family

ID=39431114

Family Applications (1)

Country Status (4)

Cited By (6)

Citations (3)

Family Cites Families (1)

• 2008
  • 2008-02-29 WO PCT/EP2008/052510 patent/WO2008116725A1/en active Application Filing
  • 2008-02-29 KR KR1020097012034A patent/KR101120780B1/ko not_active IP Right Cessation
  • 2008-02-29 EP EP20080709262 patent/EP2140452A1/en not_active Ceased
  • 2008-02-29 JP JP2009553992A patent/JP5063709B2/ja not_active Expired - Fee Related

Patent Citations (3)

Non-Patent Citations (8)

Also Published As

Similar Documents

Legal Events