WO2008114331A1 - アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法 - Google Patents

アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法 Download PDF

Info

Publication number
WO2008114331A1
WO2008114331A1 PCT/JP2007/053091 JP2007053091W WO2008114331A1 WO 2008114331 A1 WO2008114331 A1 WO 2008114331A1 JP 2007053091 W JP2007053091 W JP 2007053091W WO 2008114331 A1 WO2008114331 A1 WO 2008114331A1
Authority
WO
WIPO (PCT)
Prior art keywords
accelerator chip
dedicated
memory
memories
accelerator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053091
Other languages
English (en)
French (fr)
Inventor
Yuichiro Ajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/053091 priority Critical patent/WO2008114331A1/ja
Publication of WO2008114331A1 publication Critical patent/WO2008114331A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

　メインメモリと各専用メモリとの間でデータの送受信が可能となるように接続し、かつ、それぞれ同数の汎用アクセラレータと専用メモリを交互にリング状に接続する。こうすることで、ＤＭＡコントローラなどによってメインメモリから各専用メモリにデータが読み出され、いずれの専用メモリからでも処理を開始することができる。そして、各汎用アクセラレータがリング状同方向に接続された専用メモリに処理後のデータを書き込むことで、専用メモリ間でデータの読み書きに係る帯域幅を平均化する。
PCT/JP2007/053091 2007-02-20 2007-02-20 アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法 Ceased WO2008114331A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053091 WO2008114331A1 (ja) 2007-02-20 2007-02-20 アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053091 WO2008114331A1 (ja) 2007-02-20 2007-02-20 アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法

Publications (1)

Publication Number Publication Date
WO2008114331A1 true WO2008114331A1 (ja) 2008-09-25

Family

ID=39765452

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053091 Ceased WO2008114331A1 (ja) 2007-02-20 2007-02-20 アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法

Country Status (1)

Country Link
WO (1) WO2008114331A1 (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103664A (en) * 1979-02-02 1980-08-08 Nec Corp Multiprocessor system
JPH01177667A (ja) * 1988-01-08 1989-07-13 Yuuseishiyou Tsushin Sogo Kenkyusho マルチプロセッサ間データ転送方式
JP2001067329A (ja) * 1999-08-30 2001-03-16 Mitsumasa Koyanagi ネットワーク装置およびプロセッシングシステム
JP2002207710A (ja) * 2001-01-11 2002-07-26 Mitsubishi Electric Corp マルチプロセッサ信号処理装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103664A (en) * 1979-02-02 1980-08-08 Nec Corp Multiprocessor system
JPH01177667A (ja) * 1988-01-08 1989-07-13 Yuuseishiyou Tsushin Sogo Kenkyusho マルチプロセッサ間データ転送方式
JP2001067329A (ja) * 1999-08-30 2001-03-16 Mitsumasa Koyanagi ネットワーク装置およびプロセッシングシステム
JP2002207710A (ja) * 2001-01-11 2002-07-26 Mitsubishi Electric Corp マルチプロセッサ信号処理装置

Similar Documents

Publication Publication Date Title
TWI365375B (en) Storage controller which writes retrived data directly to a memory,method and system of processing read request with the storage controller
WO2010036819A3 (en) System and method of providing multiple virtual machines with shared access to non-volatile solid-state memory using rdma
EP2005303A4 (en) MEMORY SWITCHING SYSTEM AND METHOD
WO2007095080A8 (en) Memory circuit system and method
CN203909710U (zh) 一种适用于SoC芯片的多功能低电平复位电路
WO2010051621A8 (en) Bridge device having a virtual page buffer
WO2010053756A3 (en) Method and system for improving serial port memory communication latency and reliability
WO2009067522A3 (en) A memory buffering system that improves read/write performance and provides low latency for mobile systems
DE602007011223D1 (de) Firmware-sockelmodul zur fpga-basierten pipeline-verarbeitung
WO2013039318A3 (en) Double data rate controller having shared address and separate data error correction
EP2455942A3 (en) Memory write error correction circuit
WO2008076892A3 (en) Direct memory access controller
WO2007135522A3 (en) Mass storage device, in particular of the usb type, and related method for transferring data
EP2565772A4 (en) STORAGE ASSEMBLY, STORAGE SYSTEM, AND METHOD OF ACCESSING DATA
TW200642321A (en) System and method for wireless signal transmission
WO2005114645A3 (en) System and method for a universal data write unit
WO2009002940A3 (en) Systems and methods of reading nonvolatile memory
EP2293492A3 (en) Method and system for determining securely manhattan distances
WO2009092152A8 (en) Nand flash memory access with relaxed timing constraints
WO2008027508A3 (en) Framebuffer sharing for video processing
EP2045813A3 (en) Storage apparatus for using adaptive clock to temperature change and broadcast receiving apparatus using the same
WO2011046677A3 (en) Dynamic protocol for communicating command and address information
WO2008133980A3 (en) System and method for multi-port read and write operations
WO2008114331A1 (ja) アクセラレータチップ、アクセラレータチップを搭載した計算機、アクセラレータチップで行う演算方法
TW200710656A (en) Nonvolatile memory device and method of reducing data transfer time of nonvolatile memory device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07714594

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07714594

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP