WO2008114208A2 - Metal pads with reduced parasitic capacitance - Google Patents

Metal pads with reduced parasitic capacitance Download PDF

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Publication number
WO2008114208A2
WO2008114208A2 PCT/IB2008/051004 IB2008051004W WO2008114208A2 WO 2008114208 A2 WO2008114208 A2 WO 2008114208A2 IB 2008051004 W IB2008051004 W IB 2008051004W WO 2008114208 A2 WO2008114208 A2 WO 2008114208A2
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WO
WIPO (PCT)
Prior art keywords
metal
chip
ring
bonding structure
bonding
Prior art date
Application number
PCT/IB2008/051004
Other languages
French (fr)
Other versions
WO2008114208A3 (en
Inventor
Hans-Martin Ritter
Nicolas Guebert
Hans H. Heick
Wolfgang Schnitt
Joerg Syre
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2008114208A2 publication Critical patent/WO2008114208A2/en
Publication of WO2008114208A3 publication Critical patent/WO2008114208A3/en

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Definitions

  • the present invention relates to a bonding structure for a chip, in particular to a bonding structure for a chip, comprising a solder bump, an underbump metal (UBM) under the solder bump, and a metal pad under the UBM and to be connected to a substrate of the chip.
  • the present invention further relates to a method for connecting an underbump metal with a metal pad layer of a bonding structure for a chip, in particular a bonding structure as indicated above.
  • Bonding structures for a chip are for example used for joining a chip with a printed circuit board.
  • Such bonding technique is also called a flip chip bonding technique if the chip has an active surface with a plurality of bonding metal pads arranged into an array. Normally, each metal pad on the chip has a corresponding under bump metal layer and a solder bump. Hence, the solder bumps may connect with a corresponding set of contact pads on the printed circuit board when the chip is flipped over.
  • the flip chip technique is able to produce a high-pin-count package with a smaller overall area and a shorter circuit length. Consequently, most semiconductor manufacturers have adapted the flip chip technique to fabricate chip packages, especially to high-pin-count packages.
  • US 6,118,180 shows a metal layout on a semiconductor chip to be used in such a flip chip technique.
  • This reference wants to have a flip chip metal layout which is compatible with reduced chip pitches by providing a metal layout on a semiconductor chip which comprises a surface metal bonding pad, a metal region and an UBM (i.e. under bump metallisation).
  • the metal layout is shown in Fig 7.
  • Fig 7A shows a cross-sectional view and Fig. 7B shows a corresponding top view.
  • the surface metal bonding pad has reference numeral 402.
  • the metal region is shown with reference numerals 404 and 430.
  • the UBM has reference numeral 408.
  • On top of the UBM 408, a solder bump 412 is present.
  • the metal region 404 is a solder bump 412 is present.
  • 430 is defined adjacent to said bonding pad 402 and spaced between about 1,0 and 3,0 ⁇ m from said bonding pad 402. It can comprise a metal trace 404 or a dummy metal 430.
  • the UBM 408 overlyies said surface metal pad 402 and at least a portion of said adjacent metal region 404, 430.
  • This metal layout is particularly suitable for integrated circuits in advanced technology, which was an integrated circuit with channel length of 0.35 ⁇ m and 0.25 ⁇ m at the time of filing of US6,118,180.
  • parasitic impedance of elements in the chip can never be neglected.
  • the internal resistance, the parasitic capacitance and any parasitic inductance of the elements of the bonding structure are relevant for the RF performance of the chip.
  • Particularly relevant herein is the parasitic capacitance. Accordingly, it would be advantageous to achieve a bonding structure for a chip which provides enhanced mechanical stability, reliability or integrity while having a reduced parasitic capacitance.
  • an embodiment of the present invention provides a bonding structure for a chip, comprising a solder bump, an UBM under the solder bump, and a metal pad under the UBM, wherein the metal pad comprises a ring-like structure at least partially underlying the UBM.
  • the term "under” can mean that one object is directly under the other object but also can mean that there is another object between those objects.
  • ring-like structure can be anything which reminds of a ring, i.e. can be a donut-like structure, a toroidal structure, a loop-like structure, can have edges and can also have interruptions.
  • the afore-mentioned ring-like structure it is possible to minimize the area of the bonding metal pad and accordingly to minimize the projected area of the metal pad on the substrate of the chip so that this projected area is replaced by the projected area of the UBM on the substrate. It has turned out that the capacitance between the UBM and the substrate of the chip or an underlying metallisation is smaller than the capacitance between the metal pad and the substrate of this chip or any underlying metallisation. Accordingly, by using a ring-like structure it is possible to reduce the total of the parasitic capacitance.
  • the present invention also comprises the perception that there are no minimal areas defined for inter-metal connections between the metal pad and the UBM it is possible to have such ring-like structure with both the inner diameter and the outer diameter of the structure in the range of the diameter of the solder bump so that within this ring it is possible to have no metal structure and therefore not contribution to any parasitic capacitance.
  • the ring-like structure has a larger outer diameter than the the bump. This measure further enhances mechanical stability since the one of the most critical mechanical parts of the bonding structure is the edge of the metal pad where crack initiation can start so that it is advisable that the last metal layer of the chip, i.e., the metal pad has a diameter bigger than the diameter of the bump.
  • the ring-like structure has a smaller inner diameter than the the bump. This also further enhances mechanical stability of the bonding structure of this embodiment.
  • the diameter of the bump is the diameter measured between the edges of the bump.
  • the ring-like structure of the metal pad is connected to the UBM directly.
  • the connection between the metal pad and the UBM is not in the center of the metal pad, but in the ring-shaped structure. This gives maximum reduction of the total area of the metal pad because there is no need for another metal pad part to make the connection to the UBM. The center area might even be left out from the design.
  • the mechanical reliability turns out to be good, as there is optimal mechanical support in the outer ring. I.e. the edge of the UBM and more precisely the edge of the sphere of the solder bump are supported in the best possible manner.
  • the metal pad can comprise a dot-like structure or additional metal circle preferably in the centre of the ring-like structure.
  • the dot-like structure is connected to the UBM, while the ring-like structure is only connected to the UBM via the dot- like structure.
  • the term "dot-like structure" can be anything which reminds of a dot, i.e., can be a circular structure but can also be a polygonal structure or a structure with an edged circumference or arbitrary circumference.
  • the mechanical integrity of this embodiment may be somewhat less optimal, but this need not to be problematic if the UBM itself has sufficient mechanical integrity.
  • an UBM comprising a relatively thick layer of a ductile material, such as aluminium or certain aluminium alloys or copper or stacked combinations of both.
  • the term 'relatively thick' should be understood to refer particularly to a thickness of at least 0.5 microns up to 3 microns, more suitably in the range of 0.8 to 2.0 microns.
  • This embodiment differs from the prior art (US6118180) particularly in the distance between dot-structure and ring-shaped structure. While the prior art minimizes this distance to achieve a planar surface to 1-3 microns, the distance is maximized in the present invention. It is suitably in the order of 50-100 microns.
  • the area of the bonding pad is removed in the invention, and more preferably at least 40%. This removal is measured in comparison to a bonding pad with the same outer diameter. In case of complete removal of the inner dot, the removed area may extend to more than 50%.
  • the outer ring is here used for the mechanical integrity. It further enables the provision of an interconnect in the same metal layer. This embodiment turns out highly suitable for the event in which there is an
  • ESD protection structure in the chip and particularly for so-called system-level ESD protections with a protection up to 8 kV or even 15 kV as measured according to ESD system test (IEC-6100-4-2 ) as known to the skilled person in the field.
  • ESD system test IEC-6100-4-2
  • the ESD protection is suitably defined, at least partially, below the inner dot of the bonding pad.
  • the ESD protection is suitably a diode, such as a Zener diode. As such, an ESD pulse may be flow to the protection without any delay, and hence minimizing the risk of damage to the chip.
  • the chip comprises a filter.
  • filters are usually limited in the total amount of 'line capacitance' (this is the parasitic capacitance of the filter measured between data line and ground or another data line). Too high filter capacitance limits the rising and falling time of signals to be transmitted through the filter; thereby limiting the useable data rate or rate of bits transmitted per time period. Examples include RC-filters, LC-filters, C-R-C-filters (pi topology) etc as known to the skilled person. However, a filter may also be constituted by a plurality of resistors. Such structures are for instance used for applications in which there is a need for the provision of large quantities of data, also known as high bit-rate applications.
  • a typical example is for instance data transfer according to the USB protocol, and particularly high-speed versions of the USB protocol.
  • Another example is data exchange in the field of displays.
  • the invention is evidently particularly relevant for such circuits without capacitor: in a chip with a capacitor it is often possible to make a design in which the parasitic capacitance forms part of the needed capacitance. In case no capacitance is desired, any parasitic capacitance is problematic. Particularly, requirements are set by customers or through standardisation on the in-line capacitance. This is particularly the case for high-speed and high-data rate applications as mentioned above.
  • the chip is made in advanced technology such as C90 and beyond.
  • Such integrated circuits typically have eight or more metallisation levels.
  • the resulting parasitic capacitance is then particularly due to overlap between the bonding structure and the uppermost metallisation level. Due to the short distance, the reduction in parasitic capacitance by removal of the area below the UBM is significant.
  • the chip comprises a limited number of metallisation levels.
  • Limited means here generally three or less, such that the parasitic capacitance is present primarily between the semiconductor substrate and the bonding structure. The problem can evidently be reduced by increasing the resistivity of the substrate. However, for certain applications, such as ESD protection, it is highly suitable to have a conducting zone in the semiconductor substrate.
  • the bonding structure comprises a metal pad which comprises a closed ring-like structure.
  • a closed ring-like structure by itself provides an enhanced mechanical stability, reliability or integrity of the whole bonding structure and in particular of the connection between solder ball, UBM and metal pad.
  • a closed ring is more able to provide optimum mechanical support to all parts of the critical edge of the UBM and the solder bump while still reducing the parasitic capacitance.
  • the ring-like structure is not being connected to the UBM and is floating and only a dot-like structure or additional metal circle preferably in the centre of the ring-like structure is connected to the UBM.
  • the ring-like structure is not directly connected to the UBM but being indirectly connected to the UBM via a connection to a dot-like structure or additional metal circle within the ring-like structure, preferably in the centre of the ring-like structure, which dot-like structure or additional metal circle being directly connected to the UBM.
  • the chip may comprise several bonding pad structures, such that a first bond pad structure has a layout according to the first embodiment (e.g. direct connection between outer ring-like structure and UBM), and a second bond pad structure has a layout according to the second embodiment (e.g. provision of a dot-like structure within the ring-like structure, wherein the connection between the metal pad and the UBM is made via the dot-like structure).
  • the first bond pad structure is for instance used at the periphery of the chip, where stress in thermal cycling is largest.
  • the second bond pad structure is used at locations where there is a functional need to provide a direct, short connection to the bond pad structure, particularly with a vertical interconnect below the metal pad.
  • the bonding structure of the present invention is particularly suitable for so-called chip scale packages.
  • the bump is connected with a carrier of the customer, i.e. without using a carrier as part of the package.
  • the chip scale package is very sensitive to mechanical reliability, as in thermal cycling differences in thermal expansion between the chip and the carrier need to be dealt with by the solder bump and UBM only.
  • the UBM may have a larger thickness, as for instance described in the non-prepublished application PCT/IB2007/050174, which is included herein by reference.
  • a method for connecting an underbump metal with a metal pad layer of a bonding structure for a chip comprising the steps of defining a ring-like structure in a passivation layer between the metal pad and the underbump metal, and/or connecting the underbump metal and metal pad outside the area of a solder bump of the bonding structure.
  • Embodiments of the present invention can be used in any flip chip applications.
  • the basic idea of embodiments of the present invention is the proposal of the use of a ring-like or donut-like or loop-like structure or layout for the metal pad of the bonding structure for a chip. This is preferably done by leaving the centre of the metal pad without metal, only using a ring of metal that covers the chip preferably only in the area below the edge of the UBM, more preferably in the area of the edge of the sphere of the solder ball. In such a way the mechanical stability, reliability or integrity of the bump-chip- connection is still supported and at the same time the parasitic capacitance of the metal pad is reduced because the area of the metal pad is reduced.
  • Fig. 1 shows a bonding structure of the prior art
  • Fig. 2 shows a first embodiment of a bonding structure of the present invention
  • Fig. 3 shows a second embodiment of a bonding structure of the present invention
  • Fig. 4 shows a schematic circuit diagram for showing some parts of what was comprised by the present invention with respect to parasitic capacitances
  • Fig. 5 shows a schematic top view on a bonding structure of the prior art
  • Fig. 6 shows a schematic top view on a third embodiment of a bonding structure of the present invention
  • Fig. 7A shows a schematic cross-sectional view of the prior art
  • Fig. 7B shows a schematic top view of the prior art.
  • Fig. 1 shows a bonding structure 1 of the prior art.
  • Bonding structure 1 comprises a substrate 2 of a (not shown) chip.
  • Substrate 2 schematically depicts two layers only for illustration purposes.
  • Substrate 2 can comprise any integrated circuit.
  • On top of substrate 2 there is provided a metal pad layer or uppermost metal layer 4.
  • On top of metal pad 4 there is provided a passivation layer 6.
  • Passivation layer 6 also partly overlaps metal pad 4 at the edge of metal pad 4 to come in direct contact with substrate 2. Through an opening 8 of passivation layer 6 metal pad 4 is in contact with an
  • a solder bump sphere 12 is positioned over the UBM layer 10.
  • the prior art bonding structure 1 of Fig. 1 has a metal pad 4 which has a bigger diameter than the UBM layer 10. As a consequence a large parasitic capacitance is connected with metal pad 4.
  • the diameter of the UBM layer 10 should be defined as minimal 280 ⁇ m so that the metal pad area 4 has a diameter of about 300 ⁇ m. In a single metal layer process with reasonable dialectic layer thicknesses this metal pad 4 will have a parasitic capacitance to the silicon substrate 2 of 3 to 5pF.
  • the present invention has comprised that for applications with limited allowance for the total capacitance of the circuit this is not acceptable (See also the description of Fig. 4 below).
  • Fig. 2 shows a first embodiment of a bonding structure 20 of the present invention.
  • the layout of bonding structure 20 of Fig. 2 is comprised of a substrate 22 of a (not shown) chip, a metal pad 24 on top of substrate 22, a passivation layer 26 on top of metal pad 24 and partly overlapping metal pad 24 to be in direct contact with the substrate
  • openings 28a, 28b in the passivation layers 26 to allow a overlying UBM layer 30 to be in contact with metal pad 24 through openings 28a, 28b, and an overlying solder bump 32 on top of UBM layer 30.
  • the metal pad 24 of the chip is designed as a ring of metal with an inner diameter of about 270-260 ⁇ m which is smaller than the diameter of about 280 ⁇ m of the solder bump 32 and of the UBM layer 30, respectively, and with an outer diameter of about 300-320 ⁇ m which is bigger than the diameter of the solder bump 32 and of the UBM layer 30, respectively.
  • the overlap of the embodiment 20 is in the range of 10-20 ⁇ m. According to this overlap a critical edge of the metal pad 24 is far away enough from the edge of the ball 32 where the biggest mechanical stress is produced during thermal or mechanical cycling.
  • the thickness of the metal pad 24 is about 0,7-2,0 ⁇ m
  • the thickness of the passivation 26 is about 0,5-2,0 ⁇ m
  • the thickness of the UBM 30 is about 0,5-3,0 ⁇ m.
  • Fig. 3 shows a second embodiment of a bonding structure according to the present invention.
  • same parts or parts with similar function as in the embodiment 20 of Fig. 2 are referenced by the same reference numbers.
  • the main difference between the embodiment 20 of Fig. 2 and the embodiment 20' of Fig. 3 is that the ring-like metal pad 24 is not in contact with UBM layer 30 and that an additional dot-like structure 40 or circle of metal is placed in the centre of the metal ring 24 in order to connect with UBM layer 30 through a central opening 28c in the passivation layer 26..
  • the central circle 40 might or might not be also connected to the outer metal ring 24.
  • FIG. 4 shows a schematic circuit diagram for showing some parts of what was comprised by the present invention with respect to parasitic capacitances.
  • the diagram of Fig. 4 shows a line resistor 50, a first pad capacitance 52, a first diode capacitance 54, a second diode capacitance 56, and a second pad capacitance 58, a ground 60, an in-terminal 62 and an out-terminal 64.
  • the total line capacitance can be for example limited to 2OpF in order to allow a high speed data transfer.
  • the diodes have to be quite big in order to achieve electrostatic discharge (ESD) protection and ESD robustness >15kV. Accordingly, such ESD protection diodes 54, 56 consume the greatest part of the allowed capacitance. Therefore, only limited capacitance is left for the pad capacitances 52, 58. This means that the parasitic pad capacitances 52 and 58 have to be reduced as far as possible.
  • This principle can preferably applied to integrated discrete products with a highly doped, conductive silicon substrate and a bonding metal pad in the first metallization layer.
  • the parasitic capacitance is then present between metal pad and substrate.
  • the parasitic capacitance is here problematic, if the product comprises ESD protection and LCR filters for RF applications. Hence parasitic capacitance modifies the filter.
  • Fig. 5 shows a schematic top view on a bonding structure of the prior art. Same parts or parts with similar function as in the embodiment 1 of Fig. 1 are referenced by the same reference numbers. It can be seen that metal pads 4 cover a large area of the substrate 2 and therefore are a source of large parasitic capacitances.
  • Fig. 6 shows a schematic top view on a third embodiment of 20" of the present invention. Same parts or parts with similar function as in the embodiment 20 of Fig. 2 are referenced by the same reference numbers. As can be seen from the top view of Fig. 6 the area of the metal pads 24, 40 projected on the substrate 22 is reduced compared to the area of the metal pads 4 projected on the substrate 2 of the prior art of Fig. 5.
  • the design shown in Fig. 6 is the design of a 3-channel RC low pass filter array which is designed to provide filtering of undesired RF signals in the 800-3000 MHz frequency band.
  • the design shown in Fig. 6 incorporates diodes to provide protection to downstream components from ESD voltages as high as ⁇ 15 kV contact discharge.
  • the design shown in Fig. 6 is fabricated using thin film-on-silicon technology and integrates three resistors and seven high-level ESD-protection diodes in a single Wafer-Level chip-scale package measuring 1.4mm by 1.4mm (typical) only. It is used in applications requiring component miniaturization and ESD protection , such as mobile phone handsets, cordless telephones and personal digital devices.

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Abstract

The present invention relates to a bonding structure (20, 20', 20') for a chip, the bonding structure (20, 20', 20') comprising a solder bump (32), an underbump metal (30) under the solder bump (32), and a metal pad (24, 40) under the underbump metal (30) and to be connected to a substrate (22) of the chip, wherein the metal pad (24, 40) comprises a ring-like structure (24) underlying the under bump metal (30) at least partially which metal pad (24, 40) shows a reduced area when projected on the substrate (22) and therefore a reduced parasitic capacitance. The present invention further relates to method for connecting an underbump metal (30) with a metal pad layer (24) of a bonding structure (20, 20', 20') for a chip, comprising the step of defining a ring-like structure (24) in a passivation layer (26) between the metal pad (24) and the underbump metal (39).

Description

METAL PADS WITH REDUCED PARASITIC CAPACITANCE
BACKGROUND OF THE INVENTION
The present invention relates to a bonding structure for a chip, in particular to a bonding structure for a chip, comprising a solder bump, an underbump metal (UBM) under the solder bump, and a metal pad under the UBM and to be connected to a substrate of the chip. The present invention further relates to a method for connecting an underbump metal with a metal pad layer of a bonding structure for a chip, in particular a bonding structure as indicated above.
Bonding structures for a chip are for example used for joining a chip with a printed circuit board. Such bonding technique is also called a flip chip bonding technique if the chip has an active surface with a plurality of bonding metal pads arranged into an array. Normally, each metal pad on the chip has a corresponding under bump metal layer and a solder bump. Hence, the solder bumps may connect with a corresponding set of contact pads on the printed circuit board when the chip is flipped over. The flip chip technique is able to produce a high-pin-count package with a smaller overall area and a shorter circuit length. Consequently, most semiconductor manufacturers have adapted the flip chip technique to fabricate chip packages, especially to high-pin-count packages.
US 6,118,180 shows a metal layout on a semiconductor chip to be used in such a flip chip technique. This reference wants to have a flip chip metal layout which is compatible with reduced chip pitches by providing a metal layout on a semiconductor chip which comprises a surface metal bonding pad, a metal region and an UBM (i.e. under bump metallisation). The metal layout is shown in Fig 7. Fig 7A shows a cross-sectional view and Fig. 7B shows a corresponding top view. The surface metal bonding pad has reference numeral 402. The metal region is shown with reference numerals 404 and 430. The UBM has reference numeral 408. On top of the UBM 408, a solder bump 412 is present. The metal region 404. 430 is defined adjacent to said bonding pad 402 and spaced between about 1,0 and 3,0μm from said bonding pad 402. It can comprise a metal trace 404 or a dummy metal 430. The UBM 408 overlyies said surface metal pad 402 and at least a portion of said adjacent metal region 404, 430. This metal layout is particularly suitable for integrated circuits in advanced technology, which was an integrated circuit with channel length of 0.35 μm and 0.25 μm at the time of filing of US6,118,180.
It is a disadvantage of the known chip with said bonding structure that it turns out to affect the RF properties of the chip. As known to the skilled person, examples of RF properties are rising time of signals, matching of phases, intermodulation distortion etc.
Moreover, in RF circuits, parasitic impedance of elements in the chip can never be neglected. In other words, the internal resistance, the parasitic capacitance and any parasitic inductance of the elements of the bonding structure are relevant for the RF performance of the chip.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a chip with a bonding structure that meets the requirements of proper mechanical integrity and reliability of the solder bump and provides a reduction of parasitic impedance of the bonding structure. Particularly relevant herein is the parasitic capacitance. Accordingly, it would be advantageous to achieve a bonding structure for a chip which provides enhanced mechanical stability, reliability or integrity while having a reduced parasitic capacitance.
To achieve these targets an embodiment of the present invention provides a bonding structure for a chip, comprising a solder bump, an UBM under the solder bump, and a metal pad under the UBM, wherein the metal pad comprises a ring-like structure at least partially underlying the UBM.
In the context of this application the term "under" can mean that one object is directly under the other object but also can mean that there is another object between those objects. In the present application the term "ring-like structure" can be anything which reminds of a ring, i.e. can be a donut-like structure, a toroidal structure, a loop-like structure, can have edges and can also have interruptions.
By using the afore-mentioned ring-like structure it is possible to minimize the area of the bonding metal pad and accordingly to minimize the projected area of the metal pad on the substrate of the chip so that this projected area is replaced by the projected area of the UBM on the substrate. It has turned out that the capacitance between the UBM and the substrate of the chip or an underlying metallisation is smaller than the capacitance between the metal pad and the substrate of this chip or any underlying metallisation. Accordingly, by using a ring-like structure it is possible to reduce the total of the parasitic capacitance.
Since the present invention also comprises the perception that there are no minimal areas defined for inter-metal connections between the metal pad and the UBM it is possible to have such ring-like structure with both the inner diameter and the outer diameter of the structure in the range of the diameter of the solder bump so that within this ring it is possible to have no metal structure and therefore not contribution to any parasitic capacitance. Preferably, the ring-like structure has a larger outer diameter than the the bump. This measure further enhances mechanical stability since the one of the most critical mechanical parts of the bonding structure is the edge of the metal pad where crack initiation can start so that it is advisable that the last metal layer of the chip, i.e., the metal pad has a diameter bigger than the diameter of the bump. Preferably, the ring-like structure has a smaller inner diameter than the the bump. This also further enhances mechanical stability of the bonding structure of this embodiment.
Preferably, the diameter of the bump is the diameter measured between the edges of the bump. In a preferred embodiment, the ring-like structure of the metal pad is connected to the UBM directly. Thus, the connection between the metal pad and the UBM is not in the center of the metal pad, but in the ring-shaped structure. This gives maximum reduction of the total area of the metal pad because there is no need for another metal pad part to make the connection to the UBM. The center area might even be left out from the design. Simultaneously, the mechanical reliability turns out to be good, as there is optimal mechanical support in the outer ring. I.e. the edge of the UBM and more precisely the edge of the sphere of the solder bump are supported in the best possible manner. Moreover, since the outer ring covers a larger area, the stress will be distributed over a larger area. This leads to a reduction in peak stress, and hence a reduced failure risk. It is observed for clarity that US6, 187,680 discloses a bonding structure in which the UBM is connected to two metal bonding pads. However, it is not disclosed or suggested in that document that the two bonding pads form a single ring-shaped structure. Moreover, the bonding pads are defined outside the area of the solder bump. Therefore, the mechanical behaviour of the bonding structure is completely different than that of the invention. The support of the invention appears better. Furthermore, the definition of the solder bump in this prior art document requires an additional mask, which is not needed in the invention.
According to another embodiment of the present invention the metal pad can comprise a dot-like structure or additional metal circle preferably in the centre of the ring-like structure. Herein, the dot-like structure is connected to the UBM, while the ring-like structure is only connected to the UBM via the dot- like structure. In the context of the present patent application the term "dot-like structure" can be anything which reminds of a dot, i.e., can be a circular structure but can also be a polygonal structure or a structure with an edged circumference or arbitrary circumference. The mechanical integrity of this embodiment may be somewhat less optimal, but this need not to be problematic if the UBM itself has sufficient mechanical integrity. Good results have been obtained with an UBM comprising a relatively thick layer of a ductile material, such as aluminium or certain aluminium alloys or copper or stacked combinations of both. The term 'relatively thick' should be understood to refer particularly to a thickness of at least 0.5 microns up to 3 microns, more suitably in the range of 0.8 to 2.0 microns. This embodiment differs from the prior art (US6118180) particularly in the distance between dot-structure and ring-shaped structure. While the prior art minimizes this distance to achieve a planar surface to 1-3 microns, the distance is maximized in the present invention. It is suitably in the order of 50-100 microns. Generally, at least 25% of the area of the bonding pad is removed in the invention, and more preferably at least 40%. This removal is measured in comparison to a bonding pad with the same outer diameter. In case of complete removal of the inner dot, the removed area may extend to more than 50%. The outer ring is here used for the mechanical integrity. It further enables the provision of an interconnect in the same metal layer. This embodiment turns out highly suitable for the event in which there is an
ESD protection structure in the chip, and particularly for so-called system-level ESD protections with a protection up to 8 kV or even 15 kV as measured according to ESD system test (IEC-6100-4-2 ) as known to the skilled person in the field. This has been further explained in the application WO2006/008680, that is included herein by reference. In this specific embodiment, the ESD protection is suitably defined, at least partially, below the inner dot of the bonding pad. The ESD protection is suitably a diode, such as a Zener diode. As such, an ESD pulse may be flow to the protection without any delay, and hence minimizing the risk of damage to the chip.
In a suitable embodiment, the chip comprises a filter. Such filters are usually limited in the total amount of 'line capacitance' (this is the parasitic capacitance of the filter measured between data line and ground or another data line). Too high filter capacitance limits the rising and falling time of signals to be transmitted through the filter; thereby limiting the useable data rate or rate of bits transmitted per time period. Examples include RC-filters, LC-filters, C-R-C-filters (pi topology) etc as known to the skilled person. However, a filter may also be constituted by a plurality of resistors. Such structures are for instance used for applications in which there is a need for the provision of large quantities of data, also known as high bit-rate applications. A typical example is for instance data transfer according to the USB protocol, and particularly high-speed versions of the USB protocol. Another example is data exchange in the field of displays. The invention is evidently particularly relevant for such circuits without capacitor: in a chip with a capacitor it is often possible to make a design in which the parasitic capacitance forms part of the needed capacitance. In case no capacitance is desired, any parasitic capacitance is problematic. Particularly, requirements are set by customers or through standardisation on the in-line capacitance. This is particularly the case for high-speed and high-data rate applications as mentioned above.
In an even further embodiment, the chip is made in advanced technology such as C90 and beyond. Such integrated circuits typically have eight or more metallisation levels. The resulting parasitic capacitance is then particularly due to overlap between the bonding structure and the uppermost metallisation level. Due to the short distance, the reduction in parasitic capacitance by removal of the area below the UBM is significant.
In another embodiment, the chip comprises a limited number of metallisation levels. Limited means here generally three or less, such that the parasitic capacitance is present primarily between the semiconductor substrate and the bonding structure. The problem can evidently be reduced by increasing the resistivity of the substrate. However, for certain applications, such as ESD protection, it is highly suitable to have a conducting zone in the semiconductor substrate.
In a further embodiment of the present invention the bonding structure comprises a metal pad which comprises a closed ring-like structure. For this embodiment it is herewith claimed independent protection because a closed ring-like structure by itself provides an enhanced mechanical stability, reliability or integrity of the whole bonding structure and in particular of the connection between solder ball, UBM and metal pad. In particular a closed ring is more able to provide optimum mechanical support to all parts of the critical edge of the UBM and the solder bump while still reducing the parasitic capacitance.
In another embodiment it is possible that the ring-like structure is not being connected to the UBM and is floating and only a dot-like structure or additional metal circle preferably in the centre of the ring-like structure is connected to the UBM. By this measure the total parasitic capacitance can be further reduced. In further embodiments of the present invention the ring-like structure is not directly connected to the UBM but being indirectly connected to the UBM via a connection to a dot-like structure or additional metal circle within the ring-like structure, preferably in the centre of the ring-like structure, which dot-like structure or additional metal circle being directly connected to the UBM.
In a further embodiment, the chip may comprise several bonding pad structures, such that a first bond pad structure has a layout according to the first embodiment (e.g. direct connection between outer ring-like structure and UBM), and a second bond pad structure has a layout according to the second embodiment (e.g. provision of a dot-like structure within the ring-like structure, wherein the connection between the metal pad and the UBM is made via the dot-like structure). The first bond pad structure is for instance used at the periphery of the chip, where stress in thermal cycling is largest. The second bond pad structure is used at locations where there is a functional need to provide a direct, short connection to the bond pad structure, particularly with a vertical interconnect below the metal pad.
The bonding structure of the present invention is particularly suitable for so- called chip scale packages. Herein, the bump is connected with a carrier of the customer, i.e. without using a carrier as part of the package. As compared to packages with a carrier, the chip scale package is very sensitive to mechanical reliability, as in thermal cycling differences in thermal expansion between the chip and the carrier need to be dealt with by the solder bump and UBM only. Thereto, the UBM may have a larger thickness, as for instance described in the non-prepublished application PCT/IB2007/050174, which is included herein by reference.
In a further embodiment of the present invention there is provided a method for connecting an underbump metal with a metal pad layer of a bonding structure for a chip, in particular a bonding structure as claimed in any of the above claims, comprising the steps of defining a ring-like structure in a passivation layer between the metal pad and the underbump metal, and/or connecting the underbump metal and metal pad outside the area of a solder bump of the bonding structure. Embodiments of the present invention can be used in any flip chip applications.
The basic idea of embodiments of the present invention is the proposal of the use of a ring-like or donut-like or loop-like structure or layout for the metal pad of the bonding structure for a chip. This is preferably done by leaving the centre of the metal pad without metal, only using a ring of metal that covers the chip preferably only in the area below the edge of the UBM, more preferably in the area of the edge of the sphere of the solder ball. In such a way the mechanical stability, reliability or integrity of the bump-chip- connection is still supported and at the same time the parasitic capacitance of the metal pad is reduced because the area of the metal pad is reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. In the following drawings: Fig. 1 shows a bonding structure of the prior art;
Fig. 2 shows a first embodiment of a bonding structure of the present invention;
Fig. 3 shows a second embodiment of a bonding structure of the present invention; Fig. 4 shows a schematic circuit diagram for showing some parts of what was comprised by the present invention with respect to parasitic capacitances;
Fig. 5 shows a schematic top view on a bonding structure of the prior art; and Fig. 6 shows a schematic top view on a third embodiment of a bonding structure of the present invention; Fig. 7A shows a schematic cross-sectional view of the prior art
Fig. 7B shows a schematic top view of the prior art.
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 shows a bonding structure 1 of the prior art. Bonding structure 1 comprises a substrate 2 of a (not shown) chip. Substrate 2 schematically depicts two layers only for illustration purposes. Substrate 2 can comprise any integrated circuit. On top of substrate 2 there is provided a metal pad layer or uppermost metal layer 4. On top of metal pad 4 there is provided a passivation layer 6. Passivation layer 6 also partly overlaps metal pad 4 at the edge of metal pad 4 to come in direct contact with substrate 2. Through an opening 8 of passivation layer 6 metal pad 4 is in contact with an
UBM layer 10. A solder bump sphere 12 is positioned over the UBM layer 10.
The prior art bonding structure 1 of Fig. 1 has a metal pad 4 which has a bigger diameter than the UBM layer 10. As a consequence a large parasitic capacitance is connected with metal pad 4. If for example in a chip scale package (not shown) the distance between each solder bump 12 is 500μm the diameter of the UBM layer 10 should be defined as minimal 280μm so that the metal pad area 4 has a diameter of about 300μm. In a single metal layer process with reasonable dialectic layer thicknesses this metal pad 4 will have a parasitic capacitance to the silicon substrate 2 of 3 to 5pF. However, the present invention has comprised that for applications with limited allowance for the total capacitance of the circuit this is not acceptable (See also the description of Fig. 4 below).
Fig. 2 shows a first embodiment of a bonding structure 20 of the present invention. The layout of bonding structure 20 of Fig. 2 is comprised of a substrate 22 of a (not shown) chip, a metal pad 24 on top of substrate 22, a passivation layer 26 on top of metal pad 24 and partly overlapping metal pad 24 to be in direct contact with the substrate
22, openings 28a, 28b in the passivation layers 26 to allow a overlying UBM layer 30 to be in contact with metal pad 24 through openings 28a, 28b, and an overlying solder bump 32 on top of UBM layer 30.
According to the second embodiment 20 of Fig. 2 the metal pad 24 of the chip is designed as a ring of metal with an inner diameter of about 270-260 μm which is smaller than the diameter of about 280 μm of the solder bump 32 and of the UBM layer 30, respectively, and with an outer diameter of about 300-320 μm which is bigger than the diameter of the solder bump 32 and of the UBM layer 30, respectively. The overlap of the embodiment 20 is in the range of 10-20 μm. According to this overlap a critical edge of the metal pad 24 is far away enough from the edge of the ball 32 where the biggest mechanical stress is produced during thermal or mechanical cycling.
The thickness of the metal pad 24 is about 0,7-2,0 μm, the thickness of the passivation 26 is about 0,5-2,0 μm, and the thickness of the UBM 30 is about 0,5-3,0 μm. For connecting the UBM layer 30 with the metal pad layer 24 there is used a method with which either a similar ring-like structure is defined in the passivation layer 26 or UBM 30 and metal pad 24 are connected outside the area of the solder bump 32 (not shown).
Fig. 3 shows a second embodiment of a bonding structure according to the present invention. In Fig. 3 same parts or parts with similar function as in the embodiment 20 of Fig. 2 are referenced by the same reference numbers. The main difference between the embodiment 20 of Fig. 2 and the embodiment 20' of Fig. 3 is that the ring-like metal pad 24 is not in contact with UBM layer 30 and that an additional dot-like structure 40 or circle of metal is placed in the centre of the metal ring 24 in order to connect with UBM layer 30 through a central opening 28c in the passivation layer 26.. Although not shown in Fig. 3 the central circle 40 might or might not be also connected to the outer metal ring 24. Fig. 4 shows a schematic circuit diagram for showing some parts of what was comprised by the present invention with respect to parasitic capacitances. The diagram of Fig. 4 shows a line resistor 50, a first pad capacitance 52, a first diode capacitance 54, a second diode capacitance 56, and a second pad capacitance 58, a ground 60, an in-terminal 62 and an out-terminal 64. The total line capacitance can be for example limited to 2OpF in order to allow a high speed data transfer. Moreover, the diodes have to be quite big in order to achieve electrostatic discharge (ESD) protection and ESD robustness >15kV. Accordingly, such ESD protection diodes 54, 56 consume the greatest part of the allowed capacitance. Therefore, only limited capacitance is left for the pad capacitances 52, 58. This means that the parasitic pad capacitances 52 and 58 have to be reduced as far as possible.
This principle can preferably applied to integrated discrete products with a highly doped, conductive silicon substrate and a bonding metal pad in the first metallization layer. The parasitic capacitance is then present between metal pad and substrate. The parasitic capacitance is here problematic, if the product comprises ESD protection and LCR filters for RF applications. Hence parasitic capacitance modifies the filter.
To further clarify the differences between embodiments of the present invention and the prior art Fig. 5 shows a schematic top view on a bonding structure of the prior art. Same parts or parts with similar function as in the embodiment 1 of Fig. 1 are referenced by the same reference numbers. It can be seen that metal pads 4 cover a large area of the substrate 2 and therefore are a source of large parasitic capacitances.
Fig. 6 shows a schematic top view on a third embodiment of 20" of the present invention. Same parts or parts with similar function as in the embodiment 20 of Fig. 2 are referenced by the same reference numbers. As can be seen from the top view of Fig. 6 the area of the metal pads 24, 40 projected on the substrate 22 is reduced compared to the area of the metal pads 4 projected on the substrate 2 of the prior art of Fig. 5.
The design shown in Fig. 6 is the design of a 3-channel RC low pass filter array which is designed to provide filtering of undesired RF signals in the 800-3000 MHz frequency band. In addition, the design shown in Fig. 6 incorporates diodes to provide protection to downstream components from ESD voltages as high as ±15 kV contact discharge. The design shown in Fig. 6 is fabricated using thin film-on-silicon technology and integrates three resistors and seven high-level ESD-protection diodes in a single Wafer-Level chip-scale package measuring 1.4mm by 1.4mm (typical) only. It is used in applications requiring component miniaturization and ESD protection , such as mobile phone handsets, cordless telephones and personal digital devices. While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.
Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:
1. Bonding structure (20, 20', 20") for a chip, the bonding structure (20, 20',
20") comprising: a solder bump (32), an underbump metal (30) under the solder bump (32), and - a metal pad (24, 40) under the underbump metal (30) and to be connected to a substrate (22) of the chip, wherein the metal pad (24, 40) comprises a ring-like structure (24) underlying the under bump metal (30) at least partially.
2. Bonding structure as claimed in claim 1, wherein the ring-like structure (24) has a larger outer diameter than the solder bump (32).
3. Bonding structure as claimed in any one of the above claims, wherein the ring-like structure (24) has a smaller inner diameter than the solder bump (32).
4. Bonding structure as claimed in any one of the above claims, wherein, the metal pad (24, 40) comprises a dot-like structure (40).
5. Bonding structure as claimed in any of the above claims, wherein the dot-like structure (40) is located in the centre of the ring-like structure (24).
6. Bonding structure as claimed in any one of the above claims, wherein the dot-like structure (40) being connected to the underbump metal (30).
7. Bonding structure as claimed in any of the claims 1-5, wherein the ring-like structure (40) is connected to the underbump metal (30).
8. Bonding structure as claimed in any of the above claims, wherein the metal pad (24, 40) has a surface area which is reduced at least 25% in comparison with a fully extending metal pad with a corresponding outer diameter.
9. Bonding structure (20, 20', 20") for a chip, comprising: a solder bump (32), an underbump metal (30) under solder bump (32), and a metal pad (24, 40) under the underbump metal (30) and to be connected to a substrate (22) of the chip, wherein the metal pad (24, 40) comprises a closed ring-like structure (24).
10. Bonding structure as claimed in claim 9, wherein the ring- like structure (24) is not connected to the underbump metal (30).
11. Bonding structure as claimed in claim 9, wherein the ring-like structure (24) is not directly connected to the underbump metal (30) but is indirectly connected to the underbump metal (30) via a connection to a dot-like structure (40) within the ring-like structure (24) which dot-like structure (40) being directly connected to the underbump metal (30).
12. Chip comprising a bonding structure (20, 20', 20' ') of any one of the above claims.
13. Chip as claimed in claim 12, wherein the bonding structure (20') of claim 6 is used, and wherein the chip comprises an ESD-protection element, which underlies the dot- like structure (40) and is also coupled to the dot- like structure (40).
14. Chip as claimed in claim 12, wherein the chip comprises an RF filter.
15. Chip package, preferably flip chip package, comprising the chip of claim 12.
16. Method for connecting an underbump metal (30) with a metal pad layer (24) of a bonding structure (20, 20', 20") for a chip, in particular a bonding structure (20, 20', 20") as claimed in any of the above claims, comprising the steps of: defining a ring-like structure (24) in a passivation layer (26) between the metal pad (24) and the underbump metal (39), and/or connecting the underbump metal (30) and metal pad (24) outside the area of a solder bump (32) of the bonding structure (20, 20', 20").
PCT/IB2008/051004 2007-03-21 2008-03-17 Metal pads with reduced parasitic capacitance WO2008114208A2 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050093176A1 (en) * 2003-10-29 2005-05-05 Meng-Chi Hung Bonding pad structure
US7098540B1 (en) * 2003-12-04 2006-08-29 National Semiconductor Corporation Electrical interconnect with minimal parasitic capacitance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050093176A1 (en) * 2003-10-29 2005-05-05 Meng-Chi Hung Bonding pad structure
US7098540B1 (en) * 2003-12-04 2006-08-29 National Semiconductor Corporation Electrical interconnect with minimal parasitic capacitance

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