WO2008114095A1

WO2008114095A1 - Circuit arrangement for signal transmission between voltage domains

Info

Publication number: WO2008114095A1
Application number: PCT/IB2007/050980
Authority: WO
Inventors: Brent Buchanan
Original assignee: Nxp B.V.
Priority date: 2007-03-20
Filing date: 2007-03-20
Publication date: 2008-09-25

Abstract

According to one example embodiment, an IC arrangement (105) passes a signal between voltage domains without risking harm from a damagingly high- voltage disparity. In another aspect of the invention, such an arrangement automatically self-calibrates and the signal is passed with little alteration as the high- voltage varies over time. The arrangement includes a first circuit (110) operating in a first voltage domain, a second circuit (112) operating in a second voltage domain, and a resistive circuit (114). The resistive circuit passes a signal from the first circuit to the second circuit and carries all the current for any voltage differential between the circuits. The resistive circuit maintains a fixed voltage across the resistive circuit, such that a voltage change at one of the circuits causes a voltage at the other of the circuits to be set by both the voltage across the resistive circuit and the voltage at the circuit experiencing voltage change.

Description

CIRCUIT ARRANGEMENT FOR SIGNAL TRANSMISSION BETWEEN VOLTAGE DOMAINS

The present invention is directed generally to passing signals between voltage domains without risking harm from a high- voltage disparity between the domains.

Advances in complementary metal-oxide semiconductor (CMOS) technology are driving the operating core voltage of integrated circuits (ICs) lower. As device dimensions shrink, the voltage of the core logic, scales down proportionally in order to avoid gate-oxide breakdown and hot electron effects. However, such circuits often require operating at higher voltages in order to interface with other circuits. Some complex integrated circuits can operate with relatively low supply voltages, but in order to incorporate these circuits into existing systems it is necessary to provide interfaces from the low- voltage logic to logic devices operating at relatively high voltages, even though such high voltage levels can be damaging.

As geometries shrink with progressive IC manufacturing generations, concern for such circuitry damage has increased. For example, as SiO₂ gate insulation gets thinner, so does the allowable maximum voltage across it before the IC shorts through and the device is permanently destroyed. The maximum hold-off voltage across transistors decreases as well. A standard oxide minimum gate length N- or P- MOS transistor in a particular submicron CMOS technology can sustain no more than 2.5 volts across its drain and source before the voltage field strength punches through the intervening silicon, leading to unrecoverable failure, i.e., destructive breakdown.

Despite such physical limitations, voltages much higher than the above examples must occasionally be used. For example, the programming voltage required for a certain IC is 5.25 volts. Many standard techniques exist for isolating such high- voltages to particular circuit structures that can withstand them without harm. For this technology, N-well to P-substrate breakdown limits are near 20 volts. Therefore, devices restrained to such a high-voltage biased well can operate without risk as long as the relative voltage differences within the well do not exceed the standard limits. For many circuits, however, there are problems in transferring control or data signals between circuits that operate at standard- voltages and such isolated high- voltage sections. These problems arise because the control circuitry must interface across a voltage span that will destroy all available active components (e.g., any transistor available in the technology), and because such high- voltages may vary substantially over time (e.g., as a charge pump builds up voltage, and again when loaded). The latter situation causes the difference between voltage domains to vary considerably as a function of time and complicates the task of transferring a control signal to the high-voltage domain.

One aspect of the present invention is directed to a circuit that passes a signal (either analog or digital) between first and second circuits, each having its own voltage domain without risking harm from a damagingly high- voltage disparity between the domains. In certain applications, the passed signals are control and/or data signals.

Another aspect of the present invention is directed to such a circuit that also automatically self-calibrates such that the signal is passed with little alteration as the high- voltage varies over time.

Another aspect of the present invention is directed to an arrangement that employs IC-formed resistors (e.g., polysilicon and N- well) to transfer signals between circuits that operate in significantly-different voltage domains. In such an IC-based environment, an aspect of the present invention concerns the recognition that unlike transistors and capacitors, such resistor types are not constrained by circuit-confined (absolute) voltage limitations. Such resistor types can be designed to withstand arbitrarily large voltage drops as may be limited by the voltage- operation feasibilities of an IC.

An example embodiment of the present invention is directed to an arrangement of circuits in an integrated circuit. The arrangement includes a first circuit operating in a first voltage domain, a second circuit operating in a second voltage domain that is significantly different than the first voltage domain, and a resistive circuit. The first and second circuits also provide respective first and second connection nodes. The resistive circuit passes a signal from the first circuit to the second circuit and is connected so as to carry all the current for any voltage differential between the two connection nodes. The resistive circuit is arranged with the first and second circuits to maintain a fixed voltage across the resistive circuit, such that a voltage change at one of the connection nodes causes a voltage at the other of the connection nodes to be set by the voltage across the resistive circuit and the voltage at the connection node experiencing the change in voltage.

Another example embodiment of the present invention is directed to arrangement of circuits in an integrated circuit having a first circuit operating in a first voltage domain, a second circuit operating in a second voltage domain that is significantly different that the first voltage domain, and a current mirror. The first and second circuits also provide respective first and second connection nodes. The current mirror includes the first and second connection nodes adapted to pass a signal from the first circuit to the second circuit and a resistive circuit. The resistive circuit has respective first and second resistive legs to carry current in the current mirror and between the first connection node and the second connection node. The resistive circuit is further arranged, as discussed above, to pass a signal from the first circuit to the second circuit and is connected to carry all the current for any voltage differential between the first and second connection nodes. The resistive circuit is also arranged with the first and second circuits to maintain a fixed voltage across the resistive circuit, such that a voltage change at one of the connection nodes causes a voltage at the other of the connection nodes to be set by the voltage across the resistive circuit and the voltage at the connection node experiencing the change in voltage.

The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.

The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:

FIG 1 is an integrated circuit arrangement shown with a corresponding graphical representation of example voltage changes for the integrated circuit arrangement, according to an example embodiment of the present invention; and FIG 2 is a circuit diagram of an arrangement for passing signals between two differing voltage domains, according to an example embodiment of the present invention.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

The present invention is believed to be applicable to an integrated circuit that passes a signal between voltage domains without risking harm from a damagingly high- voltage disparity. The invention has been found to be particularly useful in passing current between voltage domains where there is a high- voltage disparity and where there is need for automatic self-calibration; such an arrangement passes the current with little alteration as the high- voltage varies over time. While the present invention is not necessarily limited to such applications, various aspects of the invention may be appreciated through a discussion of various examples using this context.

An example embodiment is directed to an arrangement of circuits in an integrated circuit. The arrangement includes a first circuit operating in a first voltage domain, a second circuit operating in a second voltage domain that is significantly different than the first voltage domain, and a resistive circuit. The first and second circuits also provide respective first and second connection nodes. The resistive circuit passes a signal from the first circuit to the second circuit and is connected so as to carry all the current for any voltage differential between the two connection nodes. The resistive circuit is arranged with the first and second circuits to maintain a fixed voltage across the resistive circuit, such that a voltage change at one of the connection nodes causes a voltage at the other of the connection nodes to be set by the voltage across the resistive circuit and the voltage at the connection node experiencing the change in voltage. FIG. 1 illustrates an example embodiment of a circuit arrangement, consistent with the above embodiment and also according to the present invention. The circuit arrangement is located in integrated circuit (IC) 105 and includes a first circuit 110 operating in a first voltage domain connected to a second circuit 112 operating in a second voltage domain via a resistive-transmission circuit 114. The resistive- transmission circuit 114 includes a first connection node (V_1n) and a second connection node (V₀Ut)- The connection nodes are also located in respective voltage domains with the first connection node being in the first voltage domain and the second connection node being in the second voltage domain. The second voltage domain significantly differs from the first voltage domain in that, without the resistive-transmission circuit 114, due to the voltage disparity passing the signal between the two domains might damage one of the two circuits. For example, where the second voltage domain varies from 5.5 volts to 10 volts and the first voltage domain is a standard voltage of about 1.5 volts, passing a 10-volt signal between the two domains might damage one of the circuits; whereas in an arrangement where the second voltage domain varies from 3.5 volts to 4.0 volts and the first voltage domain is a standard voltage of about 1.5 volts, a 4.0- volt signal could be passed between the two domains without an expectation that one of the circuits would be damaged.

In order to pass signals across this damagingly high- voltage differential, the signal to be processed is provided at the first node (e.g., V_1n). The resistive- transmission circuit 114 maintains a fixed voltage across the circuit and otherwise the two ends of resistive processing circuit 114 are floating. In this context, the resistive- transmission circuit 114 is the sole component in the arrangement exposed to the high- voltage differential. By manipulating the voltage at one end of the resistive- transmission circuit 114 (e.g., at V_1n in the first voltage domain), the voltage at the other end (e.g., V_out in the second voltage domain) is set by the combination of the fixed voltage across resistive-transmission circuit 114 and the voltage set at the input end.

Since voltage is defined as a linear function of current multiplied by resistance, a fixed resistance in the resistive-transmission circuit 114 would render the voltage differential across resistive-transmission circuit 114 dependent upon the current that flows through resistive-transmission circuit 114. As shown in the right- hand portion of FIG. 1, the output voltage (e.g., V_out) would therefore be correspondingly fixed to be a constant, predetermined value above the input voltage (e.g., V_1n), where V_R is the fixed voltage of the resistive-transmission circuit 114. Moreover, since V_R is a linear function of the current I, making current I a function of Vhigh voitage can be used to scale V_R as Vhigh-voitage changes, allowing V_R to then automatically adjust to the appropriate voltage difference. In its simplest form, the current I could be a linear function of V_hi_gh voita_ge, but could also be more complex to account for gain, clipping, and the like.

It is also recognized that while V_out and V_1n in FIG. 1 are arranged such that a signal is passed from the first circuit 110 to the second circuit 112, V_out and V_1n can be swapped with no loss or change in operation other than the signal would be passed from the second circuit 112 to the first circuit 110. FIG. 2 illustrates a CMOS implementation of the present invention, according to an example embodiment. A four PMOS transistor group 212 forms a cascoded current mirror (MPIa matched to MPIb and MP2a matched to MP2b) such that as long as all four transistors are in saturation, the same amount of current that flows through the 'a' branch will also flow through the 'b' branch independent of the output voltage V_out- Similarly, a four NMOS transistor group 210 forms a cascoded current mirror (MNIa matched to MNIb and MN2a matched to MN2b) such that as long as all four devices are in saturation, the same amount of current that flows through the 'a' branch will flow through the 'b' branch independent of the input voltage V_1n. A resistive-transmission circuit 214 connects the PMOS 212 and NMOS 210 devices. The resistive-transmission circuit 214 includes two resistive legs (R_a and R_b) that pass current between the respective 'a' and 'b' branches of the PMOS 212 and NMOS 210 devices.

The voltage changes across the 'a' and 'b' branches of each of the circuit devices are interrelated. The voltage change across the PMOS 212 device 'b' branch is a function of: i) Vp (the voltage change across the PMOS 212 'a' branch), ii) V_1n, and iii) V_N (the voltage change across the 'a' branch of the NMOS 210 device). More particularly, this 'b' branch differential

Vb-PMOS 212 = Vp + (V_N " V_1n).

Similarly, the voltage change across the NMOS 210 device 'b' branch is a function of: i) V_N (the voltage change across the NMOS 210 'a' branch), and ii) V_1n. More particularly, this 'b' branch differential

Vb-NMOs 210 = VN - (VN - V_1n). Further, the voltage change across both resistive legs of the resistive-transmission circuit 214 is the difference between the high- voltage of the PMOS 212 device (V_hi_gh voita_ge) and the sum of the voltage changes across the 'a' branches of both the PMOS 212 and NMOS 210 devices. In one example application, the bias current that flows through branch 'a' is set via R_a, and R_b is selected to be less than R_a. This provides proportionally more voltage head space for the 'b' branch transistors to remain in saturation across a wider variation in V_1n and V_out- Since the bias current generated by R_a and mirrored into Rb is a function of Vhi_gh- voltage {e.g., roughly linearly proportional), Vhigh voitage can vary across a wide range while the resistive-transmission circuit 214 automatically self-calibrates so that V_out maintains its relationship to V_hi_gh voita_ge {i.e., the reference voltage in the high-voltage domain) while still tracking V_1n {i.e., the linkage 'span' automatically changes to the appropriate size for V_hi_gh voita_ge)-

While certain aspects of the present invention have been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention. For example, the present invention can be applied to any electric/electronic circuit that must pass information (control or data) between voltage domains. While the embodiments above are in an integrated circuit, the present invention could similarly be implemented with discrete components and also be used in such diverse fields as power supply design or power generation control and distribution. Aspects of the invention are set forth in the following claims.

Claims

CLAIMS:

1. An arrangement of circuits in an integrated circuit, the arrangement comprising: a first circuit (110) operating in a first voltage domain and providing a first connection node (V_1n); a second circuit (112) operating in a second voltage domain and providing a second connection node (V_out), the second voltage domain being significantly different than the first voltage domain; a resistive circuit (114) to pass a signal from the first circuit (110)to the second circuit (112) and connected to carry all current for any voltage differential between the first and second connection nodes, the resistive circuit (114) being arranged with the first and second circuits (110, 112) to maintain a fixed voltage across the resistive circuit, wherein a voltage change at one of the first and second connection nodes causes a voltage at the other of the first and second connection nodes to be set by the voltage across the resistive circuit and the voltage at said one of the first and second connection nodes.

2. The arrangement of claim 1, wherein the resistive circuit (114) is arranged with the first and second circuits to provide a self-calibrating voltage differential at the other of the first and second connection nodes.

3. The arrangement of claim 1, wherein the resistive circuit is connected to a current-mirror (210 or 212).

4. The arrangement of claim 1, wherein the resistive circuit is connected to a current- mirror and is implemented with a first resistive path in a first leg of the current-mirror and with a second resistive path in a second leg of the current-mirror.

5. The arrangement of claim 4, wherein the first resistive path provides a first resistance to set a bias current that flows through the first leg of the current-mirror, and the second resistive path provides a second resistance in the second leg of the current-mirror, the second resistance being less than the first resistance to produce a voltage differential across the second leg that is less than the voltage differential across the first leg.

6. The arrangement of claim 5, wherein the current mirror further includes transistors to drive current through the first and second resistive paths, and wherein the voltage differential across the second leg maintains selected ones of the transistors, connected to the other of the first and second connection nodes, in saturation.

7. The arrangement of claim 4, wherein the first resistive path provides a first resistance to set a bias current that flows through the first leg of the current-mirror, and the second resistive path provides a second resistance in the second leg of the current-mirror, the second resistance being less than the first resistance and set to produce a voltage differential that maintains transistor circuitry connected to the other of the first and second connection nodes, in saturation.

8. The arrangement of claim 1, further including transistor circuitry connected to the other of the first and second connection nodes wherein the resistive circuit is arranged as part of a current-mirror and is implemented with a first resistive path in a first leg of the current-mirror and with a second resistive path in a second leg of the current- mirror, wherein each of the first circuit and the second circuit respectively includes a set of transistors to drive current through the first and second resistive paths, and wherein the voltage differential across the second leg maintains the transistor circuitry in saturation.

9. The arrangement of claim 8, wherein the transistor circuitry includes MOS transistors.

10. The arrangement of claim 9, further including MOS transistor circuitry connected to said one of the first and second connection nodes.

11. The arrangement of claim 10, wherein the MOS transistor circuitry connected to said one of the first and second connection nodes is NMOS transistor circuitry, and the MOS transistor circuitry connected to the other of the first and second connection nodes is PMOS transistor circuitry.

12. An arrangement of circuits in an integrated circuit, the arrangement comprising: a first circuit operating in a first voltage domain and providing a first connection node; a second circuit operating in a second voltage domain and providing a second connection node, the second voltage domain being significantly different than the first voltage domain; a current mirror including the first connection node and the second connection node and adapted to pass a signal from the first circuit to the second circuit, a resistive circuit having respective first and second resistive legs to carry current in the current mirror and between the first connection node and the second connection node, the resistive circuit arranged to pass a signal from the first circuit to the second circuit and connected to carry all current for any voltage differential between the first and second connection nodes, and with the first and second circuits to maintain a fixed voltage across the resistive circuit, wherein a voltage change at one of the first and second connection nodes causes a voltage at the other of the first and second connection nodes to be set by the voltage across the resistive circuit and the voltage at said one of the first and second connection nodes.

13. The arrangement of claim 12, wherein the first resistive leg provides a first resistance to set a bias current that flows through the first leg of the current-mirror, and the second resistive path provides a second resistance in the second leg of the current-mirror, the second resistance being less than the first resistance to produce a voltage differential across the second leg that is less than the voltage differential across the first leg and to maintain a selected level of circuit saturation .

14. The arrangement of claim 12, wherein the current mirror is arranged with the first and second circuits to provide a self-calibrating voltage differential at the other of the first and second connection nodes.

15. The arrangement of claim 12, wherein the voltage in the second voltage domain is in a range that includes voltages greater than 4V.

16. The arrangement of claim 12, wherein the signal is a data signal.

17. The arrangement of claim 12, wherein the signal is a control signal.

18. An integrated circuit, comprising: a first circuit operating in a first voltage domain and providing a first connection node; a second circuit operating in a second voltage domain and providing a second connection node, the second voltage domain being significantly different than the first voltage domain; a current-conducting circuit including the first connection node and the second connection node and adapted to pass a signal from the first circuit to the second circuit, resistive means having respective first and second resistive legs for carrying current between the first connection node and the second connection node, the resistive means for passing a signal from the first circuit to the second circuit and connected to carry all current for any voltage differential between the first and second connection nodes, and maintaining a fixed voltage across the resistive circuit, wherein a voltage change at one of the first and second connection nodes causes a voltage at the other of the first and second connection nodes to be set by the voltage across the resistive circuit and the voltage at said one of the first and second connection nodes.