WO2008107969A1 - 演算装置 - Google Patents

演算装置 Download PDF

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Publication number
WO2008107969A1
WO2008107969A1 PCT/JP2007/054265 JP2007054265W WO2008107969A1 WO 2008107969 A1 WO2008107969 A1 WO 2008107969A1 JP 2007054265 W JP2007054265 W JP 2007054265W WO 2008107969 A1 WO2008107969 A1 WO 2008107969A1
Authority
WO
WIPO (PCT)
Prior art keywords
computing unit
network
bit
bit wide
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/054265
Other languages
English (en)
French (fr)
Inventor
Ichiro Kasama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to JP2009502386A priority Critical patent/JP4410842B2/ja
Priority to PCT/JP2007/054265 priority patent/WO2008107969A1/ja
Publication of WO2008107969A1 publication Critical patent/WO2008107969A1/ja
Priority to US12/552,651 priority patent/US8150949B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Computer And Data Communications (AREA)

Abstract

　３２ビット幅の演算器からなる演算器ネットワーク（１）、１６ビット幅の演算器からなる演算器ネットワーク（２）、８ビット幅の演算器からなる演算器ネットワーク（３）、４ビット幅の演算器からなる演算器ネットワーク（４）、およびそれらを制御する演算制御信号用ネットワーク（５）を有する。各ネットワークは、複数の演算器により再構成可能な構成となっている。ある演算器ネットワークから、その演算器ネットワークとは異なるビット幅の演算器からなる別の演算器ネットワークにデータが渡される場合には、ビット幅変換器（６），（７），（８）により、データが渡される側の演算器ネットワークのビット幅に合うように、データのビット数を変換する。
PCT/JP2007/054265 2007-03-06 2007-03-06 演算装置 Ceased WO2008107969A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009502386A JP4410842B2 (ja) 2007-03-06 2007-03-06 演算装置
PCT/JP2007/054265 WO2008107969A1 (ja) 2007-03-06 2007-03-06 演算装置
US12/552,651 US8150949B2 (en) 2007-03-06 2009-09-02 Computing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054265 WO2008107969A1 (ja) 2007-03-06 2007-03-06 演算装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/552,651 Continuation US8150949B2 (en) 2007-03-06 2009-09-02 Computing apparatus

Publications (1)

Publication Number Publication Date
WO2008107969A1 true WO2008107969A1 (ja) 2008-09-12

Family

ID=39737874

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/054265 Ceased WO2008107969A1 (ja) 2007-03-06 2007-03-06 演算装置

Country Status (3)

Country Link
US (1) US8150949B2 (ja)
JP (1) JP4410842B2 (ja)
WO (1) WO2008107969A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012093893A (ja) * 2010-10-26 2012-05-17 Fujitsu Semiconductor Ltd リコンフィグ可能なｌｓｉ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005222142A (ja) * 2004-02-03 2005-08-18 Nec Corp アレイ型プロセッサ
JP2006203795A (ja) * 2005-01-24 2006-08-03 Matsushita Electric Ind Co Ltd 映像信号処理回路および撮像装置
JP2006303730A (ja) * 2005-04-18 2006-11-02 Mitsubishi Electric Corp 半導体集積回路装置および半導体集積回路装置の設計装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768561A (en) * 1992-06-30 1998-06-16 Discovision Associates Tokens-based adaptive video processing arrangement
US7032031B2 (en) * 2000-06-23 2006-04-18 Cloudshield Technologies, Inc. Edge adapter apparatus and method
US8204082B2 (en) * 2000-06-23 2012-06-19 Cloudshield Technologies, Inc. Transparent provisioning of services over a network
JP3896083B2 (ja) 2003-01-15 2007-03-22 三洋電機株式会社 リコンフィギュラブル回路とそれを利用可能な集積回路装置
JP2005157653A (ja) 2003-11-25 2005-06-16 Ip Flex Kk データ処理装置および処理方法
US20060245390A1 (en) * 2005-04-28 2006-11-02 Yukihiro Omoto Base station and mobile station constituting mobile communication system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005222142A (ja) * 2004-02-03 2005-08-18 Nec Corp アレイ型プロセッサ
JP2006203795A (ja) * 2005-01-24 2006-08-03 Matsushita Electric Ind Co Ltd 映像信号処理回路および撮像装置
JP2006303730A (ja) * 2005-04-18 2006-11-02 Mitsubishi Electric Corp 半導体集積回路装置および半導体集積回路装置の設計装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012093893A (ja) * 2010-10-26 2012-05-17 Fujitsu Semiconductor Ltd リコンフィグ可能なｌｓｉ

Also Published As

Publication number Publication date
US8150949B2 (en) 2012-04-03
JPWO2008107969A1 (ja) 2010-06-03
US20090327461A1 (en) 2009-12-31
JP4410842B2 (ja) 2010-02-03

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