WO2008106562A2

WO2008106562A2 - Methods & apparatus for memory allocation interleaving & deinterleaving

Info

Publication number: WO2008106562A2
Application number: PCT/US2008/055197
Authority: WO
Inventors: John Archambeault
Original assignee: Slacker, Inc.
Priority date: 2007-02-27
Filing date: 2008-02-27
Publication date: 2008-09-04
Also published as: WO2008106562A3

Abstract

An interleaving apparatus and method sequentially stores a received data frame in an interleaver's memory. The data is then block interleaved and outputted. While the first data frame is being output, data is written from a subsequent frame to the interleaver's memory, where the outputted data was previously stored. The process may be repeated multiple times. An associated deinterleaver is also described, wherein the deinterleaver memory receives an interleaved data from a buffer memory and, when frame reception is complete, outputs part of the deinterleaved data while receiving a subsequent interleaved frame.

Description

METHODS & APPARATUS FOR MEMORY ALLOCATION INTERLEAVING &

DEINTERLEAVING

RELATED APPLICATIONS

[0001] This application claims priority to United States Provisional Patent

Application Serial No. 60/891,918, entitled METHODS & APPARATUS FOR MEMORY ALLOCATION INTERLEAVING & DEINTERLEAVING, filed February 27, 2007, the content of which is hereby incorporated by reference herein in its entirety for all purposes.

FIELD OF THE INVENTION

[0002] The present invention relates generally to memory block interleaving and deinterleaving for improved error correction in digital communication systems. More particularly but not exclusively, the invention relates to memory efficient methods and apparatus for interleaving and deinterleaving data by utilizing shared memory space between

multiple frames of interleaved or deinterleaved data.

BACKGROUND OF THE INVENTION

[0003] Interleaving techniques enable error correction codes to work more efficiently in a bursty-error environment. Interleaving disperses data in a data stream before transmission so that when a burst error occurs the error is spread over an interleaved frame rather than over continuous data bits.

[0004] Conventional interleaving/deinterleaving methods and apparatus write a frame to memory, interleave the data by either taking a row or column of data at a time from the frame until the memory is empty, and then write another frame to memory. Such a

structure necessitates a buffer size at least equal to that of the interleaver's frame, which can be of substantial size. Assuming equal interleaving and deinterleaving speeds, a subsequent frame will be fully transmitted as the previous frame is fully deinterleaved by the receiver. Since traditional block interleavers do not load a new frame into memory until the first frame is completely deinterleaved, a buffer is needed to store the subsequent interleaved frame.

[0005] Accordingly, there is a need in the art for more memory efficient methods for interleaving and deinterleaving data.

SUMMARY

[0006] The present invention is directed to data interleaving and deinterleaving such as may be used in digital communication systems for improving burst error performance. In one embodiment a memory buffer size is limited to the size of a block code's row or column if a square interleaver is used.

[0007] In one embodiment, using a rectangular interleaver may require a larger buffer, but the size may still be less than the size of an interleaved frame. Since data may be written to memory one interleaved row or column at a time, the required buffer memory need not hold an entire frame of data, thereby reducing memory size.

[0008] In one embodiment, data constituting a data frame is provided to a block interleaver' s memory. The data and frame sizes may be selected based on the particular communication system or based on other constraints. Data is stored in the memory and is then interleaved for output by selecting a row or column from the memory block. Then data from another frame replaces in memory the data just transmitted while the interleaver continues to interleave data from the current frame. The process may be repeated multiple times. When the next frame of data has been fully written into the interleaver's memory and thus transmission of the first frame has been completed, the data can be reorganized within the interleaver's memory in the same way the first interleaving frame was organized to simplify the output interleaving step. [0009] In one embodiment, when a deinterleaver receives the first frame, it begins to

deinterleave and output a row or column of data at a time. The outputted row or column is replaced with data from the next interleaved frame. Because the memory is used more efficiently than in a conventional interleaver/deinterleaver system, memory buffer size may

be reduced.

[0010] Additional aspects of the present invention are further described and illustrated in the detailed description and figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0012] FIG. 1 illustrates one embodiment of a memory allocation interleaving

method in accordance with aspects of the present invention.

[0013] FIG. 2 illustrates one embodiment of a memory allocation interleaving method in accordance with aspects of the present invention.

[0014] FIG. 3 illustrates one embodiment of a memory allocation deinterleaving

method in accordance with aspects of the present invention.

[0015] FIG. 4 illustrates one embodiment of a memory allocation deinterleaving

method in accordance with aspects of the present invention.

[0016] FIG. 5 illustrates one embodiment of a communication system transmitter

and receiver that may be used to facilitate embodiments of the memory allocation interleaving and deinterleaving methods of the present invention.

DETAILED DESCRIPTION

[0017] In the following description reference is made to the accompanying drawings wherein are shown, by way of illustration, several embodiments of the present invention. It is

understood by those of ordinary skill in the art that other embodiments may be utilized and structural changes made without departing from the spirit and scope of the present invention. [0018] The present invention is directed to data interleaving and deinterleaving such as may be used in digital communication systems for improving burst error performance. In a non-real time communication channel, latency is not as large as concern as it is in a real time environment. Thus, a large interleaving frame having latency drawbacks nevertheless gives a larger distance between neighboring bits and may be capable of sending more data per frame.

[0019] In accordance with one or more embodiments, the present invention enables use of a large data frame without requiring a memory buffer equal to or larger than the size of an interleaver frame. In one embodiment of the present invention a memory buffer size is limited to the size of a block code's row or column if a square interleaver is used.

[0020] In one embodiment, using a rectangular interleaver may require a larger buffer, but the size may still be less than the size of an interleave frame. Since data may be written to memory one interleaved row or column at a time, the required buffer memory need not hold an entire frame of data, thereby reducing memory size.

[0021] In one embodiment, data constituting a data frame is provided to a block interleaver' s memory. The data and frame sizes may be selected based on the particular communication system or based on other constraints. Data is stored in the memory and is then interleaved for output by selecting a row or column from the memory block. Then data from another frame replaces in memory the data just transmitted while the interleaver continues to interleave data from the current frame. The process may be repeated multiple times. When the next frame of data has been fully written into the interleaver's memory and thus transmission of the first frame has been completed, the data can be reorganized within the interleaver's memory in the same way the first interleaving frame was organized to simplify the output interleaving step. [0022] In one embodiment, when a deinterleaver receives the first frame, it begins to deinterleave and output a row or column of data at a time. The outputted row or column is replaced with data from the next interleaved frame. Because the memory is used more efficiently than in a conventional interleaver/deinterleaver system, memory buffer size may be reduced.

[0023] Additional aspects of the present invention are further described below and illustrated in the accompanying figures.

[0024] Attention is initially directed to FIG. 5, which illustrates a communication system 500 in which embodiments of memory allocation interleaving and deinterleaving methods of the present invention may be implemented. A server 501 sends data to an interleaver apparatus 502 where the data is then interleaved by an interleaving method in accordance with aspects of the present invention. The data is converted to a digital signal which may then be converted into a baseband analog signal by a digital to analog converter 503, and modulated by a signal modulator 504. The modulated signal is transmitted by a satellite uplink apparatus 505 to a satellite 506, which retransmits a signal to receiver units such as receiver units 520 and 530. The received signal may then be demodulated by a tuner 508. After demodulation, the signal is converted back to a digital signal and corresponding digital data by an analog to digital converter 509 and associated apparatus or modules. The data may then be deinterleaved 510 by a deinterleaver apparatus applying a method in accordance with aspects of the present invention. Resulting deinterleaved data may then be stored in memory 511.

[0025] Referring now to FIG. 1, there is illustrated one embodiment of a memory allocation interleaving method capable of being implemented within the system 500 in accordance with the present invention. It is noted that while the embodiment illustrated in FIG. 1 is explained in terms of a data interleaver, the teachings apply equally to embodiments of a corresponding deinterleaving method according to aspects of the present invention. In addition, the embodiment described with respect to FIG. 1, as well as those described with respect to FIGS. 2-4, make reference to particular data and memory configuration parameters such as rows, columns, frames and packets, as well as sizes associated with those parameters. Specific descriptions are provided for illustrative purposes only, and it will be apparent to those of ordinary skill in the art that other configuration parameters and sizes are included within the spirit and scope of the present invention.

[0026] The interleaving method as illustrated in FIG. 1 begins generally with allocation of a memory space in accordance with the general configuration of a data frame, such as by data packet row or column orientation. A data packet is provided to the memory (not shown) of interleaver 502 as shown in FIG. 5, fully written to the memory and then output progressively in part to the digital to analog converter 503, while the memory space is then filled with a new data packet from the server 501 as the previously provided data packet is output to the digital to analog converter 503. The process may continue repeatedly with new data packets being stored in part of the memory of the interleaver 502 while the previous data packet is being interleaved and output to the digital to analog converter 503.

[0027] More specifically, in accordance with one embodiment rows 101a-c are rows of data to be interleaved, with 101a, 101b and 101c each constituting a whole frame worth of data (i.e., each having four rows of packets in this example). The individually labeled packets ('A', 'B', etc.) constitute one row by three columns worth of memory. Thus, the block interleaver 502 will output a frame by sending out three columns of interleaved data.

[0028] The first column sent from the memory space is shown in 102a and 102b, with 102a being a visual representation of the memory space and 102b being a representation of the data output from the interleaver 502. Once the first column of data is output as shown in 102b, new data can be added to the space 112 previously occupied by the first column of data originally in the memory, as shown in updated representation 103 of the memory space. In particular, the updated representation 103 illustrates data packet 'E' and partial packet 'F' written into memory, filling up the space left by the outputting of the first column of data 102b from the memory space.

[0029] Updated representation 104 of the memory space illustrates how the complete packets E, F, G and H may be arranged in the memory space after the first full frame (packets 'A'-'D') has been fully outputted. That is, updated representation 104 corresponds to the point in time at which the second frame (packets 'E'-'H') has been fully written into memory.

[0030] As shown in updated representation 105, the packets E, F, G and H may be reorganized in the memory space in a configuration similar to the way the packets were arranged in representation 102a. This allows the interleaving process to continue as previously described, with output provided one column at a time. For example, packets E, F, G and H may be rearranged in the memory space from a column orientation to a row orientation as shown in representation 105 and then output from the memory space in a similar manner to packets A, B, C and D. It is noted, however, that this reorganization is provided for purposes of illustration and not limitation, and other ways of reorganization of the data frame are also possible.

[0031] The process may then be repeated one or more times until data transmission is completed, with updated representations 106a and 106b of the memory space corresponding to representations 102a and 102b for packets I and J of the next frame, and space 112b representing space where new data can be added to representation 106a of the memory space. Updated representation 107a illustrates packets T and partial packet 'J' written into space 112b, with space 114 representing a space where new data can be added to updated representation 107a. Representation 107b illustrates the output of another column of interleaved data from second frame outputted from the memory space.

[0032] FIG. 2 illustrates another embodiment of an interleaving method in accordance with aspects of the present invention. 201a-c are the rows of data to be interleaved, with 201a and 201b constituting a whole frame worth of data, i.e. four rows of packets. The individually labeled packets ('A', 'B', etc.) are one row and three columns worth of memory. The first column sent is shown in 202a and 202b, with 202a being a visual representation of memory and 202b being the data output of the interleaver, similar to the embodiment illustrated in FIG. 1. Once the first column of data is output as shown in 202b, new data can be added to the space 212 previously occupied by the first column of data originally in the memory, as shown in updated representation 203 of the memory space. Updated representation 203 shows data packet 'E' and partial packet 'F' written into memory, filling up the space left by the first output of data. Updated representation 204 shows how the packets are arranged after the first frame ('A'-'D') has been fully outputted, which corresponds with the second frame fully written into memory ('E '-'H').

[0033] Unlike the embodiment illustrated in FIG. 1, at updated representation 205a the data is not rearranged by the interleaver 502 before output. Instead, the data is taken directly out by columns based on its location in the memory space as interleaved data 205b, and space 214 representing space where new data can be added to representation 205a of the memory space. Updated representations 206a and 206b correspond with updated representations 107a and 107b, respectively, with space 216 representing space where new data can be added to representation 206b.

[0034] Referring now to FIG. 3, there is illustrated one embodiment of a corresponding memory allocation deinterleaving method capable of being implemented within the system 500 in accordance with the present invention. The deinterleaving method as illustrated in FIG. 3 begins generally with receipt of data in a buffer memory of deinterleaver 510 of FIG. 5 (not shown) and allocation of a deinterleaver 510 memory space in accordance with the general configuration of a data frame, such as by data packet row or column orientation. Interleaved data is received at the buffer from analog to digital converter 509 and written to the deinterleaver 510 memory, where part of a previously received packet may simultaneously be output to memory 511 while the incoming interleaved data is transferred from the buffer to the deinterleaver 510. The process may continue repeatedly with deinterleaved data packets being output from deinterleaver 510 while incoming interleaved data is provided from the buffer to the deinterleaver 510 memory.

[0035] More specifically, in accordance with one embodiment 302a-307a are visual representations of buffer memory of deinterleaver 510. 302b-307b are visual representations of a deinterleaver' s memory, and 304c, 305c and 307c are deinterleaved packets output by the interleaver. The buffer's memory 302a is empty while the deinterleaver 's memory is not full, initially having only two columns worth of data. At representation 303b, a full frame is in the deinterleaver 510, and thus the deinterleaver 510 is able to begin to output data packets. At the same time, a column from a subsequent frame is buffered. At representation 304b, a packet 304c has been outputted and part of the next frame is now stored in the space 312a of the first row of deinterleaver 510's memory. Visual representations 305b and 305c illustrate a representation of the memory space of deinterleaver 510 after repeating this step, with another part of the next frame stored in space 314 of the second row of deinterleaver 510's memory. Visual representation 306b shows the results of repeating this step again, where the subsequent frame is now fully loaded into deinterleaver 510's memory.

[0036] In accordance with one embodiment, as shown in visual representation 307b, the data may be deinterleaved in memory, arranged in rows, and the first row output to memory 511. For example, packets E, F, G and H may be rearranged in the memory space into a row orientation as shown in visual representation 307b and then output to memory 511 in a similar manner to packets A, B, C and D. It is noted, however, that this rearrangement is provided for purposes of illustration and not limitation, and other ways of reorganization of the data frame prior to output are also possible.

[0037] Additionally, the memory space left by outputted packet 'E' may now be filled with part of a subsequent frame. The process may be repeated one or more times until data deinterleaving and output is completed.

[0038] FIG. 4 illustrates another embodiment of a deinterleaving method in accordance with aspects of the present invention. 402a-407a are visual representations of buffer memory. 402b-407b are visual representations of a deinterleaver 510 's memory, and 404c, 405c and 407c are deinterleaved packets output by the deinterleaver 510. The buffer's memory 402a is empty as the deinterleaver' s memory is not full, having only two columns worth of data. At representation 403b, a full frame is in the deinterleaver 510 and the deinterleaver 510 is now able to output data packets to memory 511. At the same time, a column from a subsequent frame is buffered as shown in representation 403a. At representation 404b, a packet 404c has been outputted and part of the next frame is now stored in the deinterleaver' s memory at space 412 representing the first row of the memory space. This step is then repeated, with the resulting memory spaces as shown in visual representations 405b and 405c illustrating filling of the additional rows.

[0039] As with the embodiment illustrated in FIG. 3, at representation 406b the subsequent frame is now fully loaded into the deinterleaver' s memory. However, unlike the embodiment illustrated in FIG. 3, in this embodiment at visual representation 407b, the data is not deinterleaved into the memory space as shown in visual representation 307b, but rather is outputted from the memory space directly deinterleaved as data 407c. [0040] Some embodiments of the present invention may include computer software and/or computer hardware/software combinations configured to implement one or more processes or functions associated with the present invention, such as those described above. These embodiments may be in the form of modules implementing functionality in software and/or hardware software combinations. Embodiments may also take the form of a computer storage product with a computer-readable medium having computer code thereon for performing various computer-implemented operations, such as operations related to functionality as describe herein. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts, or they may be a combination of both.

[0041] Examples of computer-readable media within the spirit and scope of the present invention include, but are not limited to: magnetic media such as hard disks; optical media such as CD-ROMs, DVDs and holographic devices; magneto-optical media; and hardware devices that are specially configured to store and execute program code, such as programmable microcontrollers, application-specific integrated circuits ("ASICs"), programmable logic devices ("PLDs") and ROM and RAM devices. Examples of computer code may include machine code, such as produced by a compiler, and files containing higher- level code that are executed by a computer using an interpreter. Computer code may be comprised of one or more modules executing a particular process or processes to provide useful results, and the modules may communicate with one another via means known in the art. For example, some embodiments of the invention may be implemented using assembly language, Java, C, C#, C++, or other programming languages and software development tools as are known in the art. Other embodiments of the invention may be implemented in hardwired circuitry in place of, or in combination with, machine-executable software instructions.

[0042] The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the invention are presented for purposes of illustration and description, not limitation. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. Consequently, variations and modifications of the embodiments disclosed herein may be made without departing from the spirit and scope of the invention as set forth by the claims.

[0043] The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications; they thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the invention.

Claims

CLAIMS I claim:

1. A method for providing interleaved data, comprising: storing a first data frame in a memory; providing, from a first portion of the memory, an interleaved part of the first data frame; and storing, in the first portion of the memory, part of a second data frame prior to providing a remaining interleaved part of the first data frame from the memory.

2. The method of claim 1 further including: repetitively providing, from additional portions of the memory, additional interleaved parts of the first data frame until all of the first data frame has been provided from the memory; and storing, in the additional portions of the memory, corresponding additional parts of the second data frame.

3. The method of claim 1 wherein said storing the first data frame comprises storing the first data frame in the memory in a row format, and said providing comprises providing said interleaved part of the first data frame from the memory in a column format.

4. The method of claim 3 wherein said data frame comprises a plurality of packets wherein one or more of said plurality of packets are stored in each row of the memory.

5. The method of claim 1 wherein said storing the first data frame comprises storing the first data frame in the memory in a column format, and said providing comprises providing said interleaved part of the first data frame from the memory in a row format.

6. The method of claim 5 wherein said first data frame comprises a plurality of packets wherein one or more of said plurality of packets are stored in each column of the memory.

7. The method of claim 2 wherein the first data frame is stored in accordance with a first configuration in the memory space and the second data frame is stored in accordance with a second configuration in the memory space.

8. The method of claim 7 wherein the second data frame is rearranged in accordance with the first configuration after all of the first data frame has been provided.

9. The method of claim 8 further comprising providing the second data frame from the memory.

10. The method of claim 1 further comprising: providing, from a second portion of the memory, an additional interleaved part of the first data frame; and storing, in the second portion of the memory, an additional part of the second data frame.

11. A method for deinterleaving data, comprising: storing, in a memory, a first interleaved data frame; providing, from a first portion of the memory, a deinterleaved part of the first data frame; storing, in the first portion of the memory, an interleaved part of a second data frame .prior to providing a remaining deinterleaved part of the first data frame from the memory.

12. The method of claim 11 further including: repetitively providing, from additional portions of the memory, additional deinterleaved parts of the first data frame until all of the first data frame has been provided from the memory; and storing, in the additional portions of the memory, corresponding additional interleaved parts of the second data frame.

13. The method of claim 11 wherein said first and said second interleaved data frames are received at the memory from a data buffer.

14. The method of claim 13 wherein the data buffer size is less than the data frame size.

15. The method of claim 14 wherein the interleaved data frames are provided by a square interleaver and the data buffer size is greater than the interleaver row size.

16. The method of claim 14 wherein the data buffer size is equal to the interleaver row size.

17. The method of claim 14 wherein the interleaver data frames are provided by a rectangular interleaver and the data buffer size is greater than the larger of the interleaver column or row size.

18. The method of claim 14 wherein the data buffer size is equal to the larger of the interleaver column or row size.

19. The method of claim 12 wherein the first data frame is stored in accordance with a first configuration in the memory space and the second data frame is stored in accordance with a second configuration in the memory space.

20. The method of claim 19 wherein the second data frame is rearranged in accordance with the first configuration after all of the first data frame has been provided.

21. The method of claim 20 further comprising providing the second data frame from the memory.

22. A system for interleaving data, comprising: a memory; a processor module; and a machine readable medium comprising instructions executable by the processor module for: storing a first data frame in the memory; providing, from a first portion of the memory, an interleaved part of the first data frame; and storing, in the first portion of the memory, part of a second data frame prior to providing a remaining interleaved part of the first data frame from the memory.

23. The system of claim 22 wherein the machine readable medium further comprises instructions to repetitively provide, from additional portions of the memory, additional interleaved parts of the first data frame until all of the first data frame has been provided from the memory; and store, in the additional portions of the memory, corresponding additional parts of the second data frame.

24. A system for deinterleaving data, comprising: a memory; a processor module; and a machine readable medium comprising processor executable instructions for: storing, in the memory, a first interleaved data frame; providing, from a first portion of the memory, a deinterleaved part of the first data frame; and storing, in the first portion of the memory, an interleaved part of a second data frame prior to providing a remaining deinterleaved part of the first data frame from the memory.

25. The system of claim 24 wherein the machine readable medium further comprises instructions to: repetitively provide, from additional portions of the memory, additional deinterleaved parts of the first data frame until all of the first data frame has been provided from the memory; and store, in the additional portions of the memory, corresponding additional interleaved parts of the second data frame.