WO2008102450A1 - 入出力回路装置 - Google Patents

入出力回路装置 Download PDF

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Publication number
WO2008102450A1
WO2008102450A1 PCT/JP2007/053308 JP2007053308W WO2008102450A1 WO 2008102450 A1 WO2008102450 A1 WO 2008102450A1 JP 2007053308 W JP2007053308 W JP 2007053308W WO 2008102450 A1 WO2008102450 A1 WO 2008102450A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
circuit
input
output
generating
Prior art date
Application number
PCT/JP2007/053308
Other languages
English (en)
French (fr)
Inventor
Masaya Kibune
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07714805A priority Critical patent/EP2128986A4/en
Priority to PCT/JP2007/053308 priority patent/WO2008102450A1/ja
Priority to JP2009500045A priority patent/JP4900471B2/ja
Publication of WO2008102450A1 publication Critical patent/WO2008102450A1/ja
Priority to US12/541,633 priority patent/US7859300B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　本発明は、製造バラツキに影響を受けることなく入出力回路への供給信号を最適に調整することが可能な入出力回路装置を提供することを目的とする。入出力回路装置は、第１の信号を生成する信号生成回路と、第１の信号を信号生成回路から受け取るとともに第２の信号を受け取り第１の信号と第２の信号とに応じた出力信号を生成する入出力回路と、入出力回路と実質的に同一の回路構成を有し、第１の信号を信号生成回路から受け取るとともに第３の信号を受け取り第１の信号と第３の信号とに応じた出力信号を生成する動作試験回路と、動作試験回路が正常に動作しているか否かを示す判定信号を動作試験回路の出力信号に応じて生成する判定回路と、判定回路が出力する判定信号に応じて信号生成回路を制御することにより第１の信号を調整する調整回路を含むことを特徴とする。
PCT/JP2007/053308 2007-02-22 2007-02-22 入出力回路装置 WO2008102450A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07714805A EP2128986A4 (en) 2007-02-22 2007-02-22 INPUT / OUTPUT CIRCUIT DEVICE
PCT/JP2007/053308 WO2008102450A1 (ja) 2007-02-22 2007-02-22 入出力回路装置
JP2009500045A JP4900471B2 (ja) 2007-02-22 2007-02-22 入出力回路装置
US12/541,633 US7859300B2 (en) 2007-02-22 2009-08-14 Input and output circuit apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053308 WO2008102450A1 (ja) 2007-02-22 2007-02-22 入出力回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/541,633 Continuation US7859300B2 (en) 2007-02-22 2009-08-14 Input and output circuit apparatus

Publications (1)

Publication Number Publication Date
WO2008102450A1 true WO2008102450A1 (ja) 2008-08-28

Family

ID=39709736

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053308 WO2008102450A1 (ja) 2007-02-22 2007-02-22 入出力回路装置

Country Status (4)

Country Link
US (1) US7859300B2 (ja)
EP (1) EP2128986A4 (ja)
JP (1) JP4900471B2 (ja)
WO (1) WO2008102450A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010226703A (ja) * 2009-02-27 2010-10-07 Renesas Electronics Corp レベルシフト回路及びこれを備えたスイッチ回路
CN102571060B (zh) * 2010-12-31 2015-08-12 意法半导体研发（上海）有限公司 高频智能缓冲器
US9948315B2 (en) 2016-06-10 2018-04-17 Analog Devices Global Digital to analog converter including logical assistance
US10027338B2 (en) * 2016-06-10 2018-07-17 Analog Devices Global Buffer, and digital to analog converter in combination with a buffer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026712A (ja) * 2000-07-13 2002-01-25 Nec Corp スルーレート調整回路
JP2004030338A (ja) * 2002-06-26 2004-01-29 Nec Corp 情報処理装置及び診断プログラム
US20040100838A1 (en) 2002-11-20 2004-05-27 Fujitsu Limited Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device
JP2005217949A (ja) * 2004-01-30 2005-08-11 Advantest Corp ドライバ回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3547854B2 (ja) * 1995-06-08 2004-07-28 株式会社ルネサステクノロジ 駆動電流調整機能付きバッファ回路
US6023174A (en) * 1997-07-11 2000-02-08 Vanguard International Semiconductor Corporation Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols
US6848346B1 (en) * 2003-07-09 2005-02-01 Illinois Tool Work Inc Hurricane shutter fastener installation bit
US7088160B2 (en) * 2004-04-08 2006-08-08 Infineon Technologies Ag Circuit arrangement for regulating a parameter of an electrical signal

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026712A (ja) * 2000-07-13 2002-01-25 Nec Corp スルーレート調整回路
JP2004030338A (ja) * 2002-06-26 2004-01-29 Nec Corp 情報処理装置及び診断プログラム
US20040100838A1 (en) 2002-11-20 2004-05-27 Fujitsu Limited Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device
JP2004172980A (ja) 2002-11-20 2004-06-17 Fujitsu Ltd バッファ回路装置
JP2005217949A (ja) * 2004-01-30 2005-08-11 Advantest Corp ドライバ回路
WO2005074127A1 (en) 2004-01-30 2005-08-11 Advantest Corporation A driver circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2128986A4 *

Also Published As

Publication number Publication date
EP2128986A4 (en) 2011-12-21
JPWO2008102450A1 (ja) 2010-05-27
EP2128986A1 (en) 2009-12-02
JP4900471B2 (ja) 2012-03-21
US20090302922A1 (en) 2009-12-10
US7859300B2 (en) 2010-12-28

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