WO2008099348A3 - Semiconductor device identifier generation - Google Patents
Semiconductor device identifier generation Download PDFInfo
- Publication number
- WO2008099348A3 WO2008099348A3 PCT/IB2008/050515 IB2008050515W WO2008099348A3 WO 2008099348 A3 WO2008099348 A3 WO 2008099348A3 IB 2008050515 W IB2008050515 W IB 2008050515W WO 2008099348 A3 WO2008099348 A3 WO 2008099348A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- identifier
- layer
- key
- stray capacitances
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
The present invention relates to a semiconductor device (11) for generating an identifier comprising a volatile memory (13) having a plurality of memory cells (21), to a method of generating an identifier using such a semiconductor device (11) and to a method of detecting a tampering on said semiconductor device (11). Providing a layer (27) comprising conductive and non conductive materials (28, 29) with said semiconductor device allows for a cooperation between elements or properties of a memory cell (21) which are responsible for the assuming of a random state by the memory cell (21) during initialization and the layer (27) acting as stray capacitances (26, 26 ). From the random states of the memory cells (21) a key or identifier can be generated. Due to said cooperation, i.e. the influence of the stray capacitances (26, 26 ) formed by the layer, the key or identifier can be generated more reliably over a wider range of operation parameters. Further, a tampering on said layer (27) leads to a change to the stray capacitances (26, 26 ) and thus changes the identifier or key.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07102549 | 2007-02-16 | ||
EP07102549.8 | 2007-02-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008099348A2 WO2008099348A2 (en) | 2008-08-21 |
WO2008099348A3 true WO2008099348A3 (en) | 2008-10-30 |
Family
ID=39591179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2008/050515 WO2008099348A2 (en) | 2007-02-16 | 2008-02-13 | Semiconductor device identifier generation |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2008099348A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2968454A1 (en) * | 2010-12-06 | 2012-06-08 | St Microelectronics Rousset | Method for identifying integrated circuit that is utilized in personal digital assistant, involves determining impression of granular structure of metallic zone from digital image obtained by backscattered electron diffraction |
DE102014016644A1 (en) * | 2014-11-11 | 2016-05-12 | Giesecke & Devrient Gmbh | Method for protection against unauthorized access |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010033012A1 (en) * | 1999-12-30 | 2001-10-25 | Koemmerling Oliver | Anti tamper encapsulation for an integrated circuit |
WO2003046802A2 (en) * | 2001-11-28 | 2003-06-05 | Koninklijke Philips Electronics N.V. | Semiconductor device, card, methods of initializing, checking the authenticity and the identity thereof |
-
2008
- 2008-02-13 WO PCT/IB2008/050515 patent/WO2008099348A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010033012A1 (en) * | 1999-12-30 | 2001-10-25 | Koemmerling Oliver | Anti tamper encapsulation for an integrated circuit |
WO2003046802A2 (en) * | 2001-11-28 | 2003-06-05 | Koninklijke Philips Electronics N.V. | Semiconductor device, card, methods of initializing, checking the authenticity and the identity thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2008099348A2 (en) | 2008-08-21 |
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