WO2008097090A1 - Emballage de grille matricielle à billes scellé - Google Patents

Emballage de grille matricielle à billes scellé Download PDF

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Publication number
WO2008097090A1
WO2008097090A1 PCT/NL2008/050071 NL2008050071W WO2008097090A1 WO 2008097090 A1 WO2008097090 A1 WO 2008097090A1 NL 2008050071 W NL2008050071 W NL 2008050071W WO 2008097090 A1 WO2008097090 A1 WO 2008097090A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
substrates
seal
electric component
connectors
Prior art date
Application number
PCT/NL2008/050071
Other languages
English (en)
Inventor
Erik Peter Veninga
Original Assignee
Nederlandse Organisatie voor toegepastnatuurweten schappelijk Onderzoek TNO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nederlandse Organisatie voor toegepastnatuurweten schappelijk Onderzoek TNO filed Critical Nederlandse Organisatie voor toegepastnatuurweten schappelijk Onderzoek TNO
Priority to US12/524,517 priority Critical patent/US20100109145A1/en
Priority to EP08712597A priority patent/EP2122681A1/fr
Publication of WO2008097090A1 publication Critical patent/WO2008097090A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Definitions

  • the invention relates to the field of packages for packaging one or more chips.
  • the present invention relates to micro-electronics or Micro- electro-mechanical systems (MEMS) and devices that are assembled on substrates.
  • MEMS Micro- electro-mechanical systems
  • the present invention also relates to a method of packaging such MEMS devices and systems.
  • the packages function as modular elements that are connectable, usually by soldering or glueing.
  • the packages define a housing for one or more electrical components such as chips and supporting circuitry peripheral to the chips.
  • a typical package material is Low-Temperature Co-Fired Ceramic ("LTCC") which is eligible due to its strength and low thermal expansion properties.
  • LTCC Low-Temperature Co-Fired Ceramic
  • iT,he package protects its fragile system components and can more easily be integrated in larger electronic systems.
  • the packages can be stacked structures, where a plurality of chips and/or electronic circuitry is provided on different stacked layers, which are electrically connected by circuitry that connect the stacked layers and thus form a electrical connection traversing the layers and connecting electrical components arranged on different layers.
  • a package for micro-electronics or microsystems (MEMS) thus devised comprises mechanical and electric connections between several functional package -layers.
  • MEMS micro-electronics or microsystems
  • US2003/0020173 discloses a ' Badio Frequency (RF) Micro-electromechanical system (MEMS) that is fabricated on or within Low-Temperature Co- Fired Ceramic (“LTCC”) substrates. The sealing and bonding of such packages is provided by resin or by hermetic solder layers.
  • RF Radio-electromechanical system
  • LTCC Low-Temperature Co- Fired Ceramic
  • US2005087883 discloses a no flow underfill seal to provide mechanical stabilization of a chip on a substrate.
  • an electrical package device comprising: a first substrate comprising a first electric component; a second substrate comprising a second electric component, a plurality of connectors for mechanically connecting said first and second substrates in a stacked arrangement; and a seal provided between said first and second substrates at a distance fronl said first electric component; wherein said first electric component is electrically connected to said second electric component by connecting circuitry comprising said connectors; and wherein said connectors are provided in said seal.
  • said seal comprises a no flow resin material.
  • Figure 1 shows a side view impression of an electrical package device according to an aspect of the invention
  • Figure 2 shows a detailed aspect view of a seal area of the package device according to an aspect of the invention.
  • Figure 3 shows an example of a process-flow for manufacture of the electrical package device according jto an aspect of the invention.
  • Figure 1 shows an ernbodiment according an aspect of the invention showing an electrical package 1.
  • First substrate 2 is provided as a base substrate; second substrate 3 is provided as a top substrate. Note that the substrates are devised of stacked layers.
  • First substrate 2 and second substrate 3 are providing a housing for an electrical component 4, in particular a radio frequency chip that is bonded to a lower side of the second substrate 3.
  • This bonding can be a conventional bonding, for instance a resin type bonding or thermo-compression bonding.
  • the chip 4 faces a cavity 8 which is provided on substrate 2 to provide a dielectric medium in front of the chip 4.
  • the dielectric constant is about 1 and is provided to prevent malfunction of the radio frequency chip.
  • the cavity- area spans about 0.2 - 0.3 mm but can varied accordingly.
  • the chip 4 is electrically connected by connectors 10 to the lower substrate 2. These provide the driving signals for the radio frequency chip 4 from connecting circuitry provided through the base substrate 2 by interconnecting contacts 5 (see also figure 2).
  • a further electric component, in particular a flipchip-bonded chip 7 is provided on top of substrate 3 .
  • the chip 7 can be connected to radio frequency chip 4 or to circuitry (not shown) to be attached via a lower - si ite - i o'f substrate 2 via connectors 5.
  • the connectors 5 function in addition as a mechanical bond between substrate 2 and substrate 3. In this way a stacked arrangement is provided having a flipchip 7 bonded on a top of substrate 3 and a radio frequency chip 4 bonded to a lower site of substrate 3.
  • the dimensions of the package 1 are typically about 10 X 10 mm having a height of about 3 mm and can be' varied accordingly.
  • the radio frequency chip 4 is protected by a seal 6 according to an aspect of the invention, which seal 6 is preferably of a no-flow underfill material none in the art.
  • connectors 5 providing mechanical en electrical connections are provided in the seal 6.
  • the connectors are formed by solder balls or bumps.
  • This seal 6 is preferably matched to a thermal expansion coefficient of the substrate 2,3.
  • the substrates 2 and 3 are formed of identical material so that a thermal mismatch will not arise and accordingly no further requirements relating to thermal expansion of the, underfill material 6 are necessary.
  • the thermal expansion coefficients of the chips 4 and 7, in particular radio frequency chip 4 are preferably matched to the substrate 2 and 3, in particular so that no further mechanical stabilization of connectors 10 is necessary. This provides an advantage of keeping the seal 6 distanced from the cavity 8, so that a uniform dielectric is formed without a risk of a flow of seal material into the cavity 8.
  • LTCC lowtemperature co-fired ceramic
  • the radio frequency chip 4 is preferably provided as a flipchip, that is, having the electrical connections e made directly to connectors 10 provided on substrate 2 and having an active side of the chip facing downward.
  • a package seal 6 according to the invention is provided no further sealing is necessary inside package.
  • a thick film AuPt (Pd-Ag) may be provided on a top layer package to facilitate Au bonding for a chip an solder bonding for example with solder types SnPb37 or SnAgCu in the sealing.
  • the chip interconnection structure maybe provided by laser structuring the thick film.
  • Figure 2 shows a detailed aspect view of the seal area 6 of the package device 1 showing in figure 1, in particular a seal area 6 having connectors 5 provided in the seal 6.
  • the connectors provided electrical and mechanical connections according to an aspect of the invention.
  • Interconnections 9 provide electrical interconnection in the plane of substrate 2.
  • Figure 3 is an example of process-flow for the manufacturing a package according to an aspect of the invention.
  • the inventive seal can be provided in a single process step that provides the electrical interconnection between the package substrates.
  • the inventive method can be easily integrated in conventional manufacturing steps.
  • the invention provides a possibility for providing a quasi hermetically sealed package that is as thin as 3 mm, and that has a footprint as small as 10 mm x 10 mm; which package may be provided on a organic or ceramic substrate material.
  • a no-flow underfill seal is conventionally known as an alternative to resin type seals, to provide mechanical stabilisation of a chip on a substrate.
  • the package sealing is preferably provided between materials having matching thermal expansion coefficients, in contrast to the common applications where the underfill seal is used to comply with mismatching thermal expansion coefficients.
  • an underfill seal is conventionally kn ⁇ Wn " for sealing chips, where according to the invention, the sealing is provided on a different level of system integration; that is, not the chip integration, but the manufacturing of a package.
  • first and second substrate parts may be soldered to each other and a seal may be provided on the outside of the soldered connection.
  • alternative electrical connections between the package parts for instance, of a ceramic type
  • electrical connections may be provided, including electrical 1 conductive adhesives or the like.
  • Further alternative mechanical connections may be further provided by glass, solder or epoxy .
  • An advantage of inventive solution is that miniature modular packaging is made feasible.
  • the packages may be (hermetically) sealed to at least protect the inner circuitry from moist and dirt. It may be preferably to adjust and tune the sealing material to match thermal expansion coefficients with the substrate.
  • the flow characteristic of the seal may be tuned, in particular, by adapting a fluxcomponent of the underfill.
  • radio frequency used herein is not limited to a specified frequency range in the electromagnetic spectrum, but may encompass all kinds of radiation frequencies, including the radar and/or microwave frequencies.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Selon un aspect de l'invention, on propose un dispositif d'emballage électrique comprenant : un premier substrat et un second substrat contenant un premier composant électrique ; le second substrat supportant un second composant électrique, une pluralité de connecteurs destinés à raccorder mécaniquement lesdits premier et second substrats dans une disposition empilée ; et un joint formé entre lesdits premier et second substrats à une certaine distance dudit premier composant électrique ; ledit premier composant électrique étant raccordé électriquement audit second composant électrique par des circuits de connexion comprenant lesdits connecteurs ; et dans lequel lesdits connecteurs sont formés dans ledit joint. De préférence, ledit joint comprend un matériau à base de résine sans écoulement.
PCT/NL2008/050071 2007-02-08 2008-02-08 Emballage de grille matricielle à billes scellé WO2008097090A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/524,517 US20100109145A1 (en) 2007-02-08 2008-02-08 Sealed ball grid array package
EP08712597A EP2122681A1 (fr) 2007-02-08 2008-02-08 Emballage de grille matricielle à billes scellé

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07102001A EP1956652A1 (fr) 2007-02-08 2007-02-08 Boîtier hermétique à matrice de billes
EP07102001.0 2007-02-08

Publications (1)

Publication Number Publication Date
WO2008097090A1 true WO2008097090A1 (fr) 2008-08-14

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Application Number Title Priority Date Filing Date
PCT/NL2008/050071 WO2008097090A1 (fr) 2007-02-08 2008-02-08 Emballage de grille matricielle à billes scellé

Country Status (3)

Country Link
US (1) US20100109145A1 (fr)
EP (2) EP1956652A1 (fr)
WO (1) WO2008097090A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2792246A1 (fr) 2013-04-17 2014-10-22 Basf Se Procédé de fabrication d'une suspension d'astaxanthine

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205542769U (zh) * 2015-11-30 2016-08-31 奥特斯(中国)有限公司 电子装置和电子设备
CN112086371B (zh) * 2020-08-19 2023-03-14 中国电子科技集团公司第二十九研究所 宽带射频板级互连集成方法、结构及装置

Citations (11)

* Cited by examiner, † Cited by third party
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