WO2008093257A3 - Method of protecting against attacks and circuit therefor - Google Patents

Method of protecting against attacks and circuit therefor Download PDF

Info

Publication number
WO2008093257A3
WO2008093257A3 PCT/IB2008/050203 IB2008050203W WO2008093257A3 WO 2008093257 A3 WO2008093257 A3 WO 2008093257A3 IB 2008050203 W IB2008050203 W IB 2008050203W WO 2008093257 A3 WO2008093257 A3 WO 2008093257A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
protecting against
against attacks
circuit therefor
address
Prior art date
Application number
PCT/IB2008/050203
Other languages
French (fr)
Other versions
WO2008093257A2 (en
Inventor
Joachim Garbe
Soenke Ostertun
Original Assignee
Nxp Bv
Joachim Garbe
Soenke Ostertun
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Joachim Garbe, Soenke Ostertun filed Critical Nxp Bv
Publication of WO2008093257A2 publication Critical patent/WO2008093257A2/en
Publication of WO2008093257A3 publication Critical patent/WO2008093257A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Storage Device Security (AREA)

Abstract

The invention relates to a method and to a circuit having a memory module (1) that comprises a memory matrix (2), a column decoder (3), and a line decoder (4), the circuit of the memory module in addition comprising a validation circuit (5), wherein said validation circuit (5) is capable of reconstructing an address from selection signals and comparing this address with the original address or carrying out a plausibility test, whereupon a validation signal can be given if the addresses match or the plausibility thereof is established.
PCT/IB2008/050203 2007-01-30 2008-01-21 Method of protecting against attacks and circuit therefor WO2008093257A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07001951 2007-01-30
EP07001951.8 2007-01-30

Publications (2)

Publication Number Publication Date
WO2008093257A2 WO2008093257A2 (en) 2008-08-07
WO2008093257A3 true WO2008093257A3 (en) 2008-10-30

Family

ID=39523547

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/050203 WO2008093257A2 (en) 2007-01-30 2008-01-21 Method of protecting against attacks and circuit therefor

Country Status (1)

Country Link
WO (1) WO2008093257A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3010822B1 (en) * 2013-09-17 2015-10-02 Inside Secure MEMORY CIRCUIT COMPRISING MEANS FOR DETECTING AN ERROR INJECTION

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912710A (en) * 1988-02-29 1990-03-27 Harris Corporation Self-checking random access memory
US20060156193A1 (en) * 2004-11-30 2006-07-13 Nicolas Demange Error test for an address decoder of a non-volatile memory
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912710A (en) * 1988-02-29 1990-03-27 Harris Corporation Self-checking random access memory
US20060156193A1 (en) * 2004-11-30 2006-07-13 Nicolas Demange Error test for an address decoder of a non-volatile memory
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals

Also Published As

Publication number Publication date
WO2008093257A2 (en) 2008-08-07

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