WO2008088686A1 - Sensors using a passive s/h and dda - Google Patents

Sensors using a passive s/h and dda Download PDF

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Publication number
WO2008088686A1
WO2008088686A1 PCT/US2008/000205 US2008000205W WO2008088686A1 WO 2008088686 A1 WO2008088686 A1 WO 2008088686A1 US 2008000205 W US2008000205 W US 2008000205W WO 2008088686 A1 WO2008088686 A1 WO 2008088686A1
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WO
WIPO (PCT)
Prior art keywords
voltage
receiving
charge
bus
amplifier
Prior art date
Application number
PCT/US2008/000205
Other languages
French (fr)
Inventor
Weize Xu
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Publication of WO2008088686A1 publication Critical patent/WO2008088686A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the invention relates generally to the field of CMOS image sensors, and in particular to such sensors having a differential difference amplifier for buffering, amplification and single-ended to differential signal conversion.
  • each pixel 10 having the photosensitive region 20 electrically connected to a floating diffusion 30 via a transfer gate (TG) 40 which is selectively pulsed to transfer charge to the floating diffusion (FD) 30.
  • the floating diffusion 30 converts the charge to a voltage which is sensed by an amplifier (M3) 50, preferably a source follower.
  • a reset transistor (RG) 60 resets the signal level on the floating diffusion 30 to a known level.
  • a row select transistor (RS) 70 is pulsed for selecting the particular row for readout to the pixel column bus 75 to a sample and hold circuit 80.
  • Each sample and hold circuit 80 includes a pair of capacitors 90a and 90b each electrically connected to the pixel column bus 75 respectively via switches 100a and 100b. Each capacitor 90a and 90b is respectively, electrically connected to a buffer amplifier 11 Oa and 100b for storing the charge from the capacitors 90a and 90b and for isolating the signal from the capacitors 90a and 90b from the local bus 120.
  • the buffer amplifiers 110a and 1 10b are preferably selected for unity gain, but other gains may be desirable based on the pixel array size.
  • the buffer amplifiers 110a and 110b are respectively, electrically connected to the local bus 120 through switches 115a and 115b and eventually to the global bus 130 via switches 140a and 140b that passes the signal to the differential correlated double sampling amplifier 150 (CDS).
  • the CDS 150 typically includes an amplifier, a switched capacitor network and a clock generator circuit (all of which are not shown for simplicity).
  • the sample and hold circuit 80 typically includes a bias transistor (M) 155 for providing current for the amplifier.
  • the switched capacitor network inherently includes switching noise and KT/C noise associated with capacitors.
  • the switching between the ON and OFF states also significantly slows down the speed.
  • CMOS image sensor comprising (a) a photosensitive region for collecting charge in response to incident light; (b) a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage; (c) an amplifier for receiving and amplifying the voltage; (d) a sample and hold circuit comprising (i) a first capacitor one for receiving the voltage and a second capacitor for receiving a reset level; (e) a first bus for receiving the voltage from the first capacitor and a second bus for receiving the reset level from the second capacitor; (f) a differential difference amplifier for receiving the image voltage and the reset level and for determining a difference level between the image voltage and the reset level and for removing offset of the amplifier; and (g) first and second switches respectively connected to the first and second bus for providing an electrical path for removing charge from each bus.
  • the present invention includes the advantages of high speed, low fixed pattern noise and low temporal noise.
  • FIG. 1 is a schematic diagram of a prior art image sensor
  • Fig. 2 is a schematic diagram of an image sensor of the present invention
  • Fig. 3 is a detailed schematic of a portion of Fig. 2 illustrating a pixel with its associated sample and hold circuit
  • Fig. 4a is a schematic symbol for a single-ended DDA
  • Fig. 4b is a schematic symbol for a differential-ended DDA having a closed loop configuration.
  • Active pixel sensor refers to an active electrical element within the pixel, other than transistors functioning as switches.
  • the floating diffusion or the amplifier are active elements.
  • an image sensor 160 having a pixel array 170 which includes a plurality of pixels 175, each pixel includes a photosensitive region (not shown in Fig. 2, shown in Fig. 3) that converts incident light into charge.
  • the pixels 175 are arranged in a two-dimensional array having a plurality of rows and columns.
  • a sample and hold array 180 includes a plurality of subsections of sample and hold arrays 190.
  • Each sample and hold subsection 190 includes a plurality of sample and hold circuits 200 connected to a column of pixels 175 via a pixel output column bus (not shown in Fig. 2, but is shown in Fig. 3).
  • Each sample and hold circuit 200 is connected to a local bus 210 via a switch 220, and each local bus 210 is electrically connected to a global bus 230 via a switch 240.
  • the global bus 230 is electrically connected to the input of a differential difference amplifier (DDA) 250.
  • DDA differential difference amplifier
  • each pixel 175 having the photosensitive region 260 (preferably either a photodiode or a pinned photodiode) electrically connected to a floating diffusion (FD) 270 via a transfer gate (TG) 280 which is selectively pulsed to transfer charge to the floating diffusion 270.
  • the floating diffusion 270 converts the charge to a voltage which is sensed by an amplifier (M3) 290, preferably a source follower.
  • a reset transistor (RG) 300 resets the signal level on the floating diffusion 270 to a known level.
  • a row select transistor (RS) 310 is pulsed for selecting the particular row for readout to the pixel column bus 320 to a sample and hold circuit 200.
  • Each sample and hold circuit 200 includes a pair of capacitors 33Oa and 330b each electrically connected to the pixel column bus 320 respectively via a pair of switches 340a and 340b.
  • the switch 340a is closed, and the capacitor 330a receives the reset signal level from the reset transistor 300 for resetting the charge level on the capacitor 330a to a known reference level.
  • the switch 340a is opened.
  • the reset transistor (RG) 300 is turned OFF and the transfer gate (TG) 280 is turned ON for passing the image signal to the floating diffusion (FD) 270 which is sensed by the amplifier (M3)290.
  • Switch 340b is closed for passing the image signal from the amplifier 290 to the capacitor 33Ob.
  • Each capacitor 33Oa and 330b is electrically connected to the local bus 210 via switches 220a and 220b.
  • the two switches 220a and 220b are closed for passing the signal to the DDA 250 (withy switches 240a and 240b closed) via the global bus 230 which includes two distinct lines for respectively passing the charge from the capacitors 33Oa and 330b.
  • the DDA 250 will amplify the signal and convert the signal to a fully differential signal at the output of the DDA 250.
  • the DDA 250 runs continuously so that it is low noise and high speed since it does not include a lot of switches as in the CDS 150 of the prior art.
  • the sample and hold circuit 200 includes a bias transistor 350 for providing current for the amplifier 290.
  • a charge clearing circuit 360 is electrically connected to ground for clearing the charge from both the local 210 and global buses 230 before passing charge from the capacitors 330a and 33Ob so that any residual charge is removed.
  • Figs. 4a and 4b there is shown representative symbols for the DDA 250.
  • DDAs 250 are well known in the art, and given the representative symbols, they can be readily produced by those skilled in the art. It is instructive to note that Fig. 4a is single output DDA 250a and Fig. 4b is a differential output DDA 250b.
  • the differential-ended output DDA 250b is preferably used in the present invention; however, it is noted that the single-ended output DDA 250a can also be used.
  • a closed loop configuration is preferably used as illustrated in Fig. 4b.
  • the closed loop 370 includes a feedback block for setting the gain (represented by ⁇ ).

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

A CMOS image sensor includes a photosensitive region for collecting charge in response to incident light; a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage; an amplifier for receiving and amplifying the voltage; a sample and hold circuit includes (i) a first capacitor one for receiving the voltage and a second capacitor for receiving a reset level; a first bus for receiving the voltage from the first capacitor and a second bus for receiving the reset level from the second capacitor; a differential difference amplifier for receiving the image voltage and the reset level and for determining a difference level between the image voltage and the reset level and for removing offset of the amplifier; and first and second switches respectively connected to the first and second bus for providing an electrical path for removing charge from each bus.

Description

SENSORS USING A PASSIVE S/H AND PDA
FIELD OF THE INVENTION
The invention relates generally to the field of CMOS image sensors, and in particular to such sensors having a differential difference amplifier for buffering, amplification and single-ended to differential signal conversion.
BACKGROUND OF THE INVENTION
Referring to Fig. 1 , there is shown each pixel 10 having the photosensitive region 20 electrically connected to a floating diffusion 30 via a transfer gate (TG) 40 which is selectively pulsed to transfer charge to the floating diffusion (FD) 30. The floating diffusion 30 converts the charge to a voltage which is sensed by an amplifier (M3) 50, preferably a source follower. A reset transistor (RG) 60 resets the signal level on the floating diffusion 30 to a known level. A row select transistor (RS) 70 is pulsed for selecting the particular row for readout to the pixel column bus 75 to a sample and hold circuit 80.
Each sample and hold circuit 80 includes a pair of capacitors 90a and 90b each electrically connected to the pixel column bus 75 respectively via switches 100a and 100b. Each capacitor 90a and 90b is respectively, electrically connected to a buffer amplifier 11 Oa and 100b for storing the charge from the capacitors 90a and 90b and for isolating the signal from the capacitors 90a and 90b from the local bus 120. The buffer amplifiers 110a and 1 10b are preferably selected for unity gain, but other gains may be desirable based on the pixel array size. The buffer amplifiers 110a and 110b are respectively, electrically connected to the local bus 120 through switches 115a and 115b and eventually to the global bus 130 via switches 140a and 140b that passes the signal to the differential correlated double sampling amplifier 150 (CDS). The CDS 150 typically includes an amplifier, a switched capacitor network and a clock generator circuit (all of which are not shown for simplicity). The sample and hold circuit 80 typically includes a bias transistor (M) 155 for providing current for the amplifier.
Although the prior art is satisfactory, the switched capacitor network inherently includes switching noise and KT/C noise associated with capacitors. The switching between the ON and OFF states also significantly slows down the speed.
SUMMARY OF THE INVENTION The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in a CMOS image sensor comprising (a) a photosensitive region for collecting charge in response to incident light; (b) a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage; (c) an amplifier for receiving and amplifying the voltage; (d) a sample and hold circuit comprising (i) a first capacitor one for receiving the voltage and a second capacitor for receiving a reset level; (e) a first bus for receiving the voltage from the first capacitor and a second bus for receiving the reset level from the second capacitor; (f) a differential difference amplifier for receiving the image voltage and the reset level and for determining a difference level between the image voltage and the reset level and for removing offset of the amplifier; and (g) first and second switches respectively connected to the first and second bus for providing an electrical path for removing charge from each bus. The above and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
Advantageous Effect Of The Invention
The present invention includes the advantages of high speed, low fixed pattern noise and low temporal noise.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a prior art image sensor;
Fig. 2 is a schematic diagram of an image sensor of the present invention; Fig. 3 is a detailed schematic of a portion of Fig. 2 illustrating a pixel with its associated sample and hold circuit;
Fig. 4a is a schematic symbol for a single-ended DDA; and Fig. 4b is a schematic symbol for a differential-ended DDA having a closed loop configuration.
DETAILED DESCRIPTION OF THE INVENTION
Before discussing the present invention in detail, it is instructive to note that the present invention is preferably used in, but not limited to, an active pixel sensor. Active pixel sensor refers to an active electrical element within the pixel, other than transistors functioning as switches. For example, the floating diffusion or the amplifier are active elements.
Referring to Fig. 2, there is shown an image sensor 160 having a pixel array 170 which includes a plurality of pixels 175, each pixel includes a photosensitive region (not shown in Fig. 2, shown in Fig. 3) that converts incident light into charge. The pixels 175 are arranged in a two-dimensional array having a plurality of rows and columns. A sample and hold array 180 includes a plurality of subsections of sample and hold arrays 190. Each sample and hold subsection 190 includes a plurality of sample and hold circuits 200 connected to a column of pixels 175 via a pixel output column bus (not shown in Fig. 2, but is shown in Fig. 3). Each sample and hold circuit 200 is connected to a local bus 210 via a switch 220, and each local bus 210 is electrically connected to a global bus 230 via a switch 240. The global bus 230 is electrically connected to the input of a differential difference amplifier (DDA) 250. Referring to Fig. 3, there is shown each pixel 175 having the photosensitive region 260 (preferably either a photodiode or a pinned photodiode) electrically connected to a floating diffusion (FD) 270 via a transfer gate (TG) 280 which is selectively pulsed to transfer charge to the floating diffusion 270. The floating diffusion 270 converts the charge to a voltage which is sensed by an amplifier (M3) 290, preferably a source follower. A reset transistor (RG) 300 resets the signal level on the floating diffusion 270 to a known level. A row select transistor (RS) 310 is pulsed for selecting the particular row for readout to the pixel column bus 320 to a sample and hold circuit 200.
Each sample and hold circuit 200 includes a pair of capacitors 33Oa and 330b each electrically connected to the pixel column bus 320 respectively via a pair of switches 340a and 340b. The switch 340a is closed, and the capacitor 330a receives the reset signal level from the reset transistor 300 for resetting the charge level on the capacitor 330a to a known reference level. The switch 340a is opened. Then the reset transistor (RG) 300 is turned OFF and the transfer gate (TG) 280 is turned ON for passing the image signal to the floating diffusion (FD) 270 which is sensed by the amplifier (M3)290. Switch 340b is closed for passing the image signal from the amplifier 290 to the capacitor 33Ob. Each capacitor 33Oa and 330b is electrically connected to the local bus 210 via switches 220a and 220b. When the particular sample and hold circuit 200 is addressed, the two switches 220a and 220b are closed for passing the signal to the DDA 250 (withy switches 240a and 240b closed) via the global bus 230 which includes two distinct lines for respectively passing the charge from the capacitors 33Oa and 330b. The DDA 250 will amplify the signal and convert the signal to a fully differential signal at the output of the DDA 250. The DDA 250 runs continuously so that it is low noise and high speed since it does not include a lot of switches as in the CDS 150 of the prior art.
The sample and hold circuit 200 includes a bias transistor 350 for providing current for the amplifier 290. A charge clearing circuit 360 is electrically connected to ground for clearing the charge from both the local 210 and global buses 230 before passing charge from the capacitors 330a and 33Ob so that any residual charge is removed.
Referring to Figs. 4a and 4b, there is shown representative symbols for the DDA 250. DDAs 250 are well known in the art, and given the representative symbols, they can be readily produced by those skilled in the art. It is instructive to note that Fig. 4a is single output DDA 250a and Fig. 4b is a differential output DDA 250b. The differential-ended output DDA 250b is preferably used in the present invention; however, it is noted that the single-ended output DDA 250a can also be used. In using the differential DDA 250b in the present invention, a closed loop configuration is preferably used as illustrated in Fig. 4b. The closed loop 370 includes a feedback block for setting the gain (represented by β).
PARTS LIST pixel photodiode/photosensitive region floating diffusion transfer gate amplifier reset transistor row select transistor pixel column bus sample and hold circuit a capacitors b capacitors 0a switch 0b switch Oa buffer amplifier Ob buffer amplifier 5a switch 5b switch 0 local bus 0 global bus 0a switch 0b switch 0 correlated double sampling amplifier (CDS)5 bias transistor 0 image sensor 0 pixel array 5 pixel 0 sample and hold array 0 subsection of sample and hold arrays0 sample and hold circuit 0 local bus 0 switch 220a switch
220b switch
230 global bus
240 switch
240a switch
240b switch
250 differential difference amplifier (DDA)
250a single output DDA
250b differential output DDA
260 photodiode/photosensitive region
270 floating diffusion
280 transfer gate
290 amplifier
300 reset transistor
310 row select transistor
320 pixel column bus
33Oa capacitor
330b capacitor
340a switch
340b switch
350 bias transistor
360 charge clearing circuit
370 closed-loop (feedback block)

Claims

CLAIMS:
1. An active image sensor comprising;
(a) a photosensitive region for collecting charge in response to incident light; (b) a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage;
(c) an amplifier for receiving and amplifying the voltage;
(d) a sample and hold circuit comprising:
(i) a first capacitor one for receiving the voltage and a second capacitor for receiving a reset level;
(e) a first bus for receiving the voltage from the first capacitor and a second bus for receiving the reset level from the second capacitor;
(f) a differential difference amplifier for receiving the image voltage and the reset level and for determining a difference level between the image voltage and the reset level and for removing offset of the amplifier; and
(g) first and second switches respectively connected to the first and second bus for providing an electrical path for removing charge from each bus.
2. The active image sensor as in claim 1 , wherein the sample and hold circuit is independent of a buffer amplifier.
3. The active image sensor as in claim 1, wherein the sample and hold circuit includes only passive electrical components.
4. The active image sensor as in claim 1, wherein the differential difference amplifier operates continuously.
PCT/US2008/000205 2007-01-12 2008-01-07 Sensors using a passive s/h and dda WO2008088686A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/622,777 US20080169845A1 (en) 2007-01-12 2007-01-12 Sensors using a passive s/h and dda
US11/622,777 2007-01-12

Publications (1)

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WO2008088686A1 true WO2008088686A1 (en) 2008-07-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011078970A1 (en) 2009-12-22 2011-06-30 Omnivision Technologies, Inc. Column output circuits for image sensors
CN103491320B (en) * 2013-09-05 2017-02-08 北京立博信荣科技有限公司 Image sensing circuit and method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7969494B2 (en) * 2007-05-21 2011-06-28 Aptina Imaging Corporation Imager and system utilizing pixel with internal reset control and method of operating same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331421A (en) * 1985-11-15 1994-07-19 Canon Kabushiki Kaisha Solid state image pickup apparatus
EP1083655A2 (en) * 1999-09-10 2001-03-14 Kabushiki Kaisha Toshiba Amplifier circuit
US20030223003A1 (en) * 2002-03-21 2003-12-04 Guy Meynants Fast and low-power multiplexing circuit and use thereof in imaging devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060077273A1 (en) * 2004-10-12 2006-04-13 Hae-Seung Lee Low noise active pixel image sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331421A (en) * 1985-11-15 1994-07-19 Canon Kabushiki Kaisha Solid state image pickup apparatus
EP1083655A2 (en) * 1999-09-10 2001-03-14 Kabushiki Kaisha Toshiba Amplifier circuit
US20030223003A1 (en) * 2002-03-21 2003-12-04 Guy Meynants Fast and low-power multiplexing circuit and use thereof in imaging devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011078970A1 (en) 2009-12-22 2011-06-30 Omnivision Technologies, Inc. Column output circuits for image sensors
CN102656880A (en) * 2009-12-22 2012-09-05 全视科技有限公司 Column output circuits for image sensors
US8411184B2 (en) 2009-12-22 2013-04-02 Omnivision Technologies, Inc. Column output circuits for image sensors
TWI497999B (en) * 2009-12-22 2015-08-21 Omnivision Tech Inc Column output circuits for image sensors
CN103491320B (en) * 2013-09-05 2017-02-08 北京立博信荣科技有限公司 Image sensing circuit and method

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US20080169845A1 (en) 2008-07-17

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