KR100691190B1 - Image Censor Array - Google Patents

Abstract

The present invention relates to an image sensor array capable of effectively reducing fixed pattern noise caused by an amplifier and a gain difference of an image sensor. The image sensor array according to the present invention is connected to a photodiode and the photodiode, and is connected to a source follower. A plurality of image sensors including a drive transistor configured to be connected to the drive transistor, and a select transistor connected in series with the drive transistor to receive a selection signal and operating the drive transistor; And a common input terminal commonly connected to the plurality of image sensors, differentially coupled to a drive transistor and a select transistor of each image sensor, and having a switching control signal applied in synchronization with the selection signal. And a common output unit constituting an operational amplifier including the drive transistor and the select transistor of the image sensor to which the first input terminal is applied, and the common input terminal as the second input terminal.

Image Sensor, CIS, Fixed Pattern Noise (FPN), Operational Amplifiers, Buffers, Offsets

Description

Image Sensor Array

1 is a block diagram illustrating a pixel array and a peripheral device for image sensing.

2 is a circuit diagram of a conventional pixel image sensor.

3 is a circuit diagram of another conventional pixel image sensor.

4 is a circuit diagram of an image sensor array according to the present invention.

5 is another circuit diagram of an image sensor array according to the present invention.

Explanation of symbols on the main parts of the drawings

100a, 100b: image sensor 200: common output

PD: photodiode M1: reset transistor

M2: Drive Transistor M3: Select Transistor

M4, M5, M8: first to third PMOS transistors

M6, M7: first and second NMOS transistors

I1, I2: current source

The present invention relates to an image sensor array, and more particularly to an image sensor array capable of effectively reducing fixed pattern noise.

The image sensor is an element that outputs a voltage signal at a level capable of signal processing when electrons and holes generated in the photoconductor vary according to the wavelength and intensity of light when the light enters the photoconductor through the color filter. Image sensors are classified into CCD (Charge Coupled Device) image sensors and CMOS image sensors.

CCD type image sensor transfers electrons generated from the light receiving part and converts them into voltage form at the last stage.

CMOS image sensor converts electrons generated from each light receiver into voltage and transfers them to the last stage. However, the CMOS image sensor has a weak signal and a lot of paths for noise. However, with the development of semiconductor process technology, CDS (Correlated Double) As a method of reducing noise by using a sampling method has been developed, the use range of digital cameras, mobile phones with camera functions, and PC cameras is expanding.

In general, an image sensor is used as a unit pixel, and an image sensor array in which a plurality of image sensors are arranged in predetermined columns and rows is used to obtain an image of a predetermined standard.

1 illustrates a pixel array implemented in a camera or the like and a peripheral device thereof, and includes a pixel array 10 in which a plurality of image sensors are arranged in a matrix and simultaneously reset by a reset signal, and according to a column selection signal and a transfer signal. The column decoder 11 for activating the image sensor of the pixel array 10 in units of rows and the voltage generated by each image sensor of the pixel array 10 activated by the column decoder 11 in units of rows. A row sampling circuit and multiplexer 12 for sampling and outputting the data, an analog-to-digital converter 14 for converting voltages output from the row sampling circuit and multiplexer 12 into digital data, and the column decoder in a predetermined order. (11) and a counter 13 for controlling the row sampling circuit and the multiplexer 12.

In the pixel array 10, output lines of image sensors belonging to the same row are connected in common and connected to the row sampling circuit and the multiplexer 12, so that the image sensors of the columns selected by the operation of the column decoder 11 are provided. The voltage generated at is output via the row sampling circuit and the multiplexer 12.

Each image sensor included in the pixel array 10 is configured as shown in FIG. 2 or 3.

The image sensor shown in FIG. 2 includes a photodiode PD whose capacitance is changed in response to light, a reset transistor M1 for resetting the photodiode PD by a reset signal to enable the next read processing, A drive transistor M2 operating as a source follower by an electrical signal stored in the photodiode PD and a selector operating in response to a column selection signal to output a voltage generated by the drive transistor M2. The transistor M3 is included.

That is, when the reset transistor M1 is turned on for a predetermined time by applying the reset signal Rx, an amount of current in proportion to the wavelength or intensity of the received light is generated in the photodiode PD and the column select signal S Is converted into a voltage signal by the drive transistor M2 and output to the row sampling circuit and the multiplexer 12 of FIG. The image sensor shown in FIG. 2 is generally referred to as a 3TR image sensor because only three CMOS transistors are implemented.

In this case, the photodiode may further include a transfer transistor between the photodiode PD and the drive transistor M2 to amplify an electric signal stored in the photodiode PD and transmit the amplified electric signal to the drive transistor M2. In this case, since four CMOS transistors are used, it is called a 4TR image sensor.

In order to reduce the size of the pixel array, the above-described 3TR or 4TR image sensor is mainly used, but image sensors having various structures have been proposed.

3 is an image sensor having another structure, in which an operational amplifier OP1 is used instead of the drive transistor M2 of the image sensor of FIG. 2, and a photo diode PD whose capacitance is changed in response to light, and a reset A reset transistor M1 for resetting the photodiode PD by a signal to enable next read processing, and an operational amplifier OP1 for amplifying and converting the charge generated in the photodiode PD into a voltage signal. And a select transistor M3 which operates in accordance with the column selection signal to output a voltage signal from the operational amplifier OP1.

However, when the pixel array is implemented using the image sensor having the above-described structure, since the process deviation may occur between the respective image sensors, fixed pattern noise (hereinafter referred to as FPN) due to process dispersion may be Cause.

The FPN is a visible combination caused by variations in output values due to the device and interconnect mismatch across the image sensor, the main factor of which is the offset and gain difference between the amplifiers.

In order to reduce the FPN, conventionally, digital image data output from the analog-to-digital converter of FIG. 1 is processed by image processing, or a separate noise removing circuit is provided on the column signal output side of the image sensor array. There is a problem that an additional additional configuration of the conventional method is increased, and it is difficult to obtain an effective noise reduction effect.

In addition, the conventional CDS (Correlated Double Sampling) method can reduce the FPN due to the offset difference, but can not reduce the FPN due to the gain difference between the sensors.

The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide an image sensor array capable of effectively reducing the fixed pattern noise caused by the amplifier and gain difference of the image sensor.

As a construction means for achieving the above object, an image sensor array according to the present invention, a photodiode, a drive transistor connected to the photodiode to operate as a source follower, and connected in series with the drive transistor to select a selection signal A plurality of image sensors including a select transistor that is turned on when applied to operate the drive transistor; And a common input terminal commonly connected to the plurality of image sensors, differentially coupled to a drive transistor and a select transistor of each image sensor, and having a switching control signal applied in synchronization with the selection signal. And a common output unit constituting an operational amplifier including the drive transistor and the select transistor of the image sensor to which the first input terminal is applied, and the common input terminal as the second input terminal.

In addition, in the image sensor array according to the present invention, the common output unit may include: a first PMOS transistor provided between each drive transistor and a power supply terminal of the plurality of image sensors; The second PMOS transistor whose gate is simultaneously connected to the gate of the first PMOS transistor and its drain; A first NMOS transistor connected in series with the drain of the second PMOS transistor; A second NMOS transistor connected in series with a drain of the first NMOS transistor and receiving a control signal (S / W signal) through a gate; A first current source commonly connected to the drain of the second NMOS transistor M7 and the select transistor of each image sensor; A third PMOS transistor having a gate connected to a contact point of the drive transistor and a first PMOS transistor, a source connected to a power supply terminal, and a gate and a drain of the first NMOS transistor connected; And a second current source provided between the drain of the third PMOS transistor and the ground, wherein the drain of the third PMOS transistor is connected to an output terminal OUT of the image sensor array.

In addition, in the image sensor array according to the present invention, the common output unit may further include a feedback terminal between the drain of the third PMOS transistor and the gate of the first NMOS transistor to adjust the gain and scale of the output signal.

Hereinafter, an image sensor array according to the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram showing the configuration of an image sensor array according to the present invention.

Referring to FIG. 4, an image sensor array according to the present invention includes a plurality of image sensors 100a and 100b for converting electrons generated at a light receiving unit into voltages through a plurality of transistors and transferring them to an output terminal, and the image sensors 100a. And a common output unit 200 which is commonly connected to the output terminal of the circuit board 100b and which is combined with a plurality of transistors of the image sensors 100a and 100b to form an operational amplifier circuit.

The plurality of image sensors 100a and 100b are commonly used CMOS image sensors (CIS), and may use not only the most basic 3TR structure but also any 4TR structure and any image sensor that improves the 3TR and 4TR structures. Do.

In more detail, each of the image sensors 100a and 100b may be configured to reset the photodiode PD in which electrons are generated in response to light, and the photodiode PD in response to a reset signal to perform the next reading process. A reset transistor M1, a drive transistor M2 that operates as a source follower to output charge generated by the photodiode PD as a voltage signal, and operates according to a selection signal to operate the drive transistor ( And a select transistor M3 for outputting the voltage generated in M2).

In addition, the image sensors 100a and 100b may amplify an electric signal stored in the photodiode PD according to a transfer signal between the photodiode PD and the drive transistor M2 in order to improve performance of the sensor. A floating diffusion provided between the transfer transistor and the drive transistor M2 to receive and store the charge accumulated in the photodiode PD in order to extend the dynamic range of the transfer transistor and / or the sensor transferred to the M2. (FD) may be further included, and other elements may be further provided. At this time, the image sensor included in the image sensor array according to the present invention must include the photodiode PD, the drive transistor M2, and the select transistor M3.

The common output unit 200 is commonly connected to the output sides of the plurality of image sensors 100a and 100b, and is used to output some CMOS transistors, that is, voltage signals provided in the image sensors 100a and 100b. In combination with the drive transistor M2 and the select transistor M3, an operational amplifier circuit is implemented.

More specifically, the common output unit 200 includes a first PMOS transistor M4 provided between the drive transistor M2 and the power supply terminal Vdd of the plurality of image sensors 100a and 100b, and a gate thereof. The second PMOS transistor M5 simultaneously connected to the gate of the first PMOS transistor M4 and its drain, and the first NMOS transistor M6 connected in series to the drain of the second PMOS transistor M5. And a second NMOS transistor M7 connected in series with a drain of the first NMOS transistor and inputting the control signal (S / W signal) to a gate, a drain of each of the second NMOS transistors M7, and each image sensor. A gate is connected to a first current source I1 commonly connected to the select transistors M3 of (100a and 100b), a contact point of the drive transistor M2 and the first PMOS transistor M4, and a source to a power supply terminal. A stage is connected and the first NMOS transistor And a third current source I2 provided between the drain and the ground of the third PMOS transistor M8 connected to the gate and the drain of the master M6, and the third PMOS transistor M8 connected to the drain. The drain of the PMOS transistor M8 is connected to the output terminal OUT of the image sensor array.

The first to third PMOS transistors M4, M5, and M8, the first and second NMOS transistors M6 and M7, and the first and second current sources I1 and I2 included in the common output unit 200 are described above. In combination with the drive transistor M2 and the select transistor M3 of each of the image sensors 100a and 100b, an operational amplifier is configured. The configured operational amplifier acts as a buffer and transfers the voltage generated from the drive transistor M2 to the output terminal OUT.

In this case, the fixed pattern noise FPN generated by the process dispersion includes the drive transistors M1 and the select transistor M3 of the image sensors 100a and 100b and the first and second of the common output unit 200. It is represented by the offset size caused by mismatch of the NMOS transistors M6 and M7, and the offset size is represented by the first to third PMOS transistors M4, M5 and M8, and the first and second NMOS transistors M6 and M6. M7), inversely proportional to the gain of the operational amplifier implemented by the first and second current sources I1 and I2, the drive transistor M2 and the select transistor M3, so that the effect of mismatch between CMOS transistors is very small. As a result, a reduction effect of the fixed pattern noise appearing at the output terminal OUT can be obtained.

This action can be more readily understood from the action of the image sensor array according to the invention which will be described below.

In the image sensor array according to the present invention, the plurality of image sensors 100a and 100b generate sensing voltages according to input signals S1 to Sn, respectively, wherein the selection of each image sensor 100a and 100b is performed. The signals S1 to Sn are applied in a predetermined order, and a sensing voltage is generated by the image sensors 100a and 100b selected at predetermined intervals. Thus, the common output unit 200 is electrically coupled with one image sensor 100a or 100b at a time.

In addition, the control signal S / W applied to the gate of the second NMOS transistor M7 of the common output unit 200 is generated when the selection signals S1 to Sn of the image sensors 100a and 100b are generated. Are simultaneously applied to turn on the second NMOS transistor M7.

For reference, the reset signals R of the plurality of image sensors 100a and 100b are simultaneously applied, and are applied after outputting all the sensing voltages of the plurality of image sensors 100a and 100b to prepare for outputting the next sensing voltage. It is to.

Therefore, in the image sensor array according to the present invention, the light incident on the photodiode PD after the reset signal R is applied and the reset transistors M1 of the respective image sensors 100a and 100b are turned on for a predetermined time. In response to the charge, charges are generated, and when the select signals S1 to Sn are applied, they are converted into a voltage form through the drive transistor M2 and output.

Therefore, when the select signal S1 is turned on, the circuits of the drive transistor M2 and the select transistor M3 of the corresponding image sensor 100a and the common output unit 200 are combined to form an operational amplifier. The charge generated by the photodiode PD of the image sensor 100a may be generated by the operation amplifier implemented as a circuit of the drive transistor M2 and the select transistor M3 of the image sensor 100a and the common output unit 200. The signal is converted into a voltage signal corresponding to the gain and transferred to the output terminal OUT.

Similarly, when the select signal Sn is turned on, a circuit of the drive transistor M2 and the select transistor M3 of the corresponding image sensor 100b and the common output unit 200 is combined to form an operational amplifier. The charge generated by the photodiode PD of the image sensor 100a may be generated by a circuit of the drive transistor M2, the select transistor M3, and the common output unit 200 of the image sensor 100b. The signal is converted into a voltage signal corresponding to the gain and transferred to the output terminal OUT.

In the above, the FPN due to the process dispersion of the different image sensors 100a and 100b includes the drive transistor M2 and the select transistor M3 and the first and second NMOS transistors M6 and M7 of the common output terminal 200. Since the offset size is a very small signal compared to the gain of the corresponding operational amplifier, the process deviation between the image sensors 100a and 100b does not significantly affect the output signal.

In addition, the image sensor array according to the present invention may minimize the difference in gain between the plurality of image sensors 100a and 100b by outputting a sensing voltage by binding all the image sensors 100a and 100b to a common buffer. Can be.

In addition, the image sensor array according to the present invention may be configured as shown in FIG.

Referring to FIG. 5, in the image sensor array according to the present invention, the common output unit 200 may further include a feedback stage 210 for feeding back an output signal to an input terminal. The feedback terminal 210 connects the output terminal (out) and the gate of the first NMOS transistor M6 corresponding to the input terminal of the operational amplifier circuit, and at this time, by adjusting the impedance value of the feedback terminal 210, the output By amplifying the signal with greater gain, or by changing the output waveform to a logarithmic scale, the dynamic range of the image sensor can be extended.

The feedback stage 210 is generally implemented as a passive element such as a resistor or a capacitor.

As described above, the common output unit 200 may further include a feedback stage 210, and thus may be extended to an amplifier or a log scale circuit as well as a simple buffer.

As described above, the present invention implements an image sensor array, by using some CMOS transistors included in multiple image sensors as components of an operational amplifier, so that fixed pattern noise due to process dispersion appears as an offset of the operational amplifier. By doing so, there is an excellent effect of removing the fixed pattern noise.

Claims (6)

A plurality of image sensors including a photodiode, a drive transistor connected to the photodiode and operating as a source follower, and a select transistor connected in series with the drive transistor and turned on when a selection signal is applied to operate the drive transistor; And A common input terminal commonly connected to the plurality of image sensors, differentially coupled to a drive transistor and a select transistor of each image sensor, and including a common input terminal to which a switching control signal in synchronization with the selection signal is applied; A common output unit constituting an operational amplifier for converting electrons generated in the photodiode into a voltage signal by outputting the drive transistor and the select transistor of the applied image sensor to the first input terminal and the common input terminal to the second input terminal. And an image sensor array. The method of claim 1, wherein the common output unit And a feedback stage for feeding back a signal outputted to the output stage to the common input stage. The method of claim 1, wherein the common output unit A first PMOS transistor provided between each drive transistor and a power supply terminal of the plurality of image sensors; The second PMOS transistor whose gate is simultaneously connected to the gate of the first PMOS transistor and its drain; A first NMOS transistor connected in series with the drain of the second PMOS transistor; A second NMOS transistor connected in series with a drain of the first NMOS transistor and receiving a control signal (S / W signal) through a gate; A first current source commonly connected to the drain of the second NMOS transistor and the select transistor of each image sensor; A third PMOS transistor having a gate connected to a contact point of the drive transistor and a first PMOS transistor, a source terminal connected to a power supply terminal, and a gate and a drain of the first NMOS transistor connected to each other; And A second current source provided between the drain and the ground of the third PMOS transistor; The drain of the third PMOS transistor is connected to the output terminal (OUT) of the image sensor array. The method of claim 3, wherein the common output unit And a feedback terminal provided between the output terminal (OUT) and the gate of the first NMOS transistor. The method of claim 1, wherein the plurality of image sensors And a reset transistor provided between a power supply terminal and the photodiode and turned on by a reset signal to restore a potential of the photodiode to a reference potential. The method of claim 5, wherein the plurality of image sensors And a transfer transistor provided between the photodiode and the gate of the drive transistor and turned on according to a transfer signal to transfer charge generated in the photodiode to the drive transistor.

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