WO2008083161A1 - Variation d'ecc page par page dans un dispositif de mémoire - Google Patents

Variation d'ecc page par page dans un dispositif de mémoire Download PDF

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Publication number
WO2008083161A1
WO2008083161A1 PCT/US2007/088830 US2007088830W WO2008083161A1 WO 2008083161 A1 WO2008083161 A1 WO 2008083161A1 US 2007088830 W US2007088830 W US 2007088830W WO 2008083161 A1 WO2008083161 A1 WO 2008083161A1
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WO
WIPO (PCT)
Prior art keywords
data
block
page
information
ecc
Prior art date
Application number
PCT/US2007/088830
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English (en)
Inventor
Nima Mokhlesi
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/618,686 external-priority patent/US7870457B2/en
Priority claimed from US11/618,694 external-priority patent/US7877665B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Publication of WO2008083161A1 publication Critical patent/WO2008083161A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Definitions

  • the present invention relates to technology for non-volatile memory.
  • Non-volatile semiconductor memory devices have become more popular for use in various electronic devices.
  • non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
  • EEPROM Electrical Erasable Programmable Read Only Memory
  • flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate.
  • the floating gate is positioned between the source and drain regions.
  • a control gate is provided over and insulated from the floating gate.
  • the threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
  • EEPROM and flash memory devices When programming an EEPROM or flash memory device, electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state.
  • Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device.
  • a multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device.
  • Shifts in the apparent charge stored on a floating gate or other charge region can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates.
  • This floating gate to floating gate coupling phenomenon is described in U.S. Patent 5,867,429, which is incorporated herein by reference in its entirety.
  • An adjacent floating gate to a target floating gate may include neighboring floating gates that are on the same bit line, neighboring floating gates on the same word line, or floating gates that are diagonal from the target floating gate because they are on both a neighboring bit line and neighboring word line.
  • Floating gate to floating gate coupling occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times.
  • a first memory cell may be programmed to add a level of charge to its floating gate that corresponds to one set of data.
  • one or more adjacent memory cells are programmed to add a level of charge to their floating gates that corresponds to a second set of data.
  • the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell.
  • the coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored.
  • ECC error correction code
  • the ECC is most commonly stored together with the sector of user data from which the ECC has been calculated.
  • the ECC is used to determine the integrity of the user data being read.
  • One or a few erroneous bits of data within a sector of data can often be corrected by use of the ECC but the existence of more errors renders the attempted data read to fail.
  • the existence of bits that are read incorrectly because of close field coupling with adjacent memory cells can cause an attempted data read to fail.
  • a method of storing memory device data overhead information in data cells in a row of cells, the row being one of a plurality of rows comprising a unit of data is disclosed.
  • the method includes storing user data attribute information in an overhead portion of a data sector in the word line adjacent to a portion of the data sector storing user data.
  • the attribute information is stored in a location normally used for ECC information and in row having greater user data integrity than others of said rows. Numerous techniques for ensuring that the row has such greater integrity are disclosed.
  • the user data attributes include block level information.
  • a method of storing overhead information in data cells organized as a plurality of pages in a block in a memory device is disclosed.
  • a subset of the plurality of pages is defined as a block of data.
  • the method includes storing user data in a portion of a first page and storing block level data attributes for the user data in a second portion of the first page.
  • the page has a higher degree of data integrity than others of said pages and the data is stored in a location normally occupied by ECC information.
  • Figure 1 is a top view of a NAND string.
  • Figure 2 is an equivalent circuit diagram of the NAND string.
  • Figure 3 is a cross sectional view of the NAND string.
  • Figure 4 is a block diagram of a non-volatile memory system.
  • Figure 5 illustrates an example of an organization of a memory array.
  • Figure 6 is a graph illustrating curves of programmed memory cell level distributions.
  • Figure 7 is a plan view of storage elements illustrating the relative effects of floating gate coupling.
  • Figure 8 is a flow chart providing one example of the read operation of the memory system.
  • Figure 9 illustrates the storage of data and overhead information in a page of data.
  • Figure 10 illustrates an alternative page of information in accordance with the present technology.
  • Figure 1 1 is a second cross-sectional view of a NAND string. DETAILED DESCRIPTION
  • FIG. 1 is a top view showing one NAND string.
  • Figure 2 is an equivalent circuit thereof.
  • the NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122.
  • Select gate 120 connects the NAND string to bit line 126.
  • Select gate 122 connects the NAND string to source line 128.
  • Select gate 120 is controlled by the applying appropriate voltages to control gate 120CG.
  • Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG.
  • Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate.
  • Transistor 100 has control gate 100CG and floating gate 100FG.
  • Transistor 102 includes control gate 102CG and floating gate 102FG.
  • Transistor 104 includes control gate 104CG and floating gate 104FG.
  • Transistor 106 includes a control gate 106CG and floating gate 106FG.
  • Control gate 100CG is connected to word line WL3
  • control gate 102CG is connected to word line WL2
  • control gate 104CG is connected to word line WL1
  • control gate 106CG is connected to word line WLO.
  • Figure 3 provides a cross-sectional view of the NAND string described above.
  • the transistors (also called cells or memory cells) of the NAND string are formed in p-well region 140.
  • Each transistor includes a stacked gate structure that consists of the control gate (100CG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG).
  • the floating gates are formed on the surface of the p-well on top of an oxide film.
  • the control gate is above the floating gate, with an oxide layer separating the control gate and floating gate. Note that Figure 3 appears to depict a control gate and floating gate for transistors 120 and 122.
  • N+ diffused layers 130, 132, 134, 136 and 138 are shared between neighboring cells whereby the cells are connected to one another in series to form a NAND string. These N+ diffused layers form the source and drain of each of the cells.
  • N+ diffused layer 130 serves as the drain of transistor 122 and the source for transistor of 106
  • N+ diffused layer 132 serves as the drain for transistor 106 and the source for transistor 104
  • N+ diffused region 134 serves as the drain for transistor 104 and the source for transistor 102
  • N+ diffused region 136 serves as the drain for transistor 102 and the source for transistor 100
  • N+ diffused layer 138 serves as the drain for transistor 100 and the source for transistor 120.
  • N+ diffused layer 126 connects to the bit line for the NAND string
  • N+ diffused layer 128 connects to a common source line for multiple NAND strings.
  • Figures 1-3 shows four memory cells in the NAND string, the use of four transistors is only provided as an example.
  • a NAND string can have less than four memory cells or more than four memory cells.
  • some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
  • FIG. 4 is a block diagram of one embodiment of a flash memory system that can be used to implement the present invention.
  • Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c-source control circuit 310 and p-well control circuit 308.
  • Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote the programming or to inhibit the programming.
  • Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages, to apply program voltages and to apply an erase voltage.
  • C- source control circuit 310 controls a common source line (labeled as "C- source” in Figure 6) connected to the memory cells.
  • P-well control circuit 308 controls the p-well voltage.
  • the data stored in the memory cells are read out by the column control circuit 304 and are output to external I/O lines via data input/output buffer 312.
  • Program data to be stored in the memory cells are input to the data input/output buffer 312 via the external I/O lines, and transferred to the column control circuit 304.
  • the external I/O lines are connected to controller 318.
  • Command data for controlling the flash memory device is input to controller 318.
  • the command data informs the flash memory of what operation is requested.
  • the input command is transferred to state machine 316, which controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308 and data input/output buffer 312.
  • State machine 316 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.
  • Controller 318 is connected or connectable with a host system such as a personal computer, a digital camera, personal digital assistant, etc. Controller 318 communicates with the host in order to receive commands from the host, receive data from the host, provide data to the host and provide status information to the host. Controller 318 converts commands from the host into command signals that can be interpreted and executed by command circuits 314, which is in communication with state machine 316. Controller 318 typically contains buffer memory for the user data being written to or read from the memory array.
  • One exemplary memory system comprises one integrated circuit that includes controller 318, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits.
  • the trend is to integrate the memory arrays and controller circuits of a system together on one or more integrated circuit chips.
  • the memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems.
  • a removable card may include the entire memory system (e.g. including the controller) or just the memory array(s) and associated peripheral circuits (with the controller being embedded in the host).
  • the controller can be embedded in the host or included within a removable memory system.
  • FIG. 5 an example structure of memory cell array 302 is described.
  • a NAND flash EEPROM is described that is partitioned into 1 ,024 blocks.
  • the data stored in each block is simultaneously erased.
  • the block is the minimum unit of cells that are simultaneously erased.
  • the bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo).
  • Figure 6 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four can be used.
  • One terminal of the NAND string is connected to corresponding bit line via a first select transistor SGD, and another terminal is connected to c-source via a second select transistor SGS.
  • the number of memory cells in a "page” that are programmed or read simultaneously may vary according to the size of data sent or requested by a host system.
  • There are several ways to program the memory cells coupled to a single word line such as (1 ) programming even bit lines and odd bit lines separately, which may comprise upper page programming and lower page programming, (2) programming all the bit lines (“all-bit-line programming"), or (3) programming all the bit lines in a left or right page separately, which may comprise right page programming and a left page programming.
  • the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells.
  • the range of possible threshold voltages of a memory cell can be divided into ranges which represent distinct memory states. For example, two ranges of threshold voltages can be used to establish two memory states that are assigned logical data "1 " and "0.”
  • a memory cell can also store multiple bits of digital data by utilizing more than two ranges of threshold voltages to represent distinct memory states.
  • the threshold voltage window can be divided into the number of desired memory states and multiple voltage breakpoint levels used to resolve the individual states.
  • Figure 6 shows an example of the effect upon a first group of memory cells, such as a word line of cells, of the later programming of a second group of memory cells, such as an adjacent word line of cells.
  • a first group of memory cells such as a word line of cells
  • second group of memory cells such as an adjacent word line of cells.
  • four distinct charge levels are defined for each storage element, thereby to store two bits of data on each storage element. Since the level of charge stored on a storage element changes the threshold voltage (Vt) of its memory cell transistor, the threshold voltage is shown on the horizontal axis of the curves of Figure 6.
  • the solid lines (45, 47, 49, 51 ) show the distributions of the number of threshold voltages of all the cells in a page immediately after being programmed, before any change is made to the adjacent pages.
  • the vertical axis is the number of cells at each threshold level, the curves having essentially a Gaussian distribution.
  • a curve 45 is the distribution of the cells in the erased state, which, in this example, is also designated as a programmed state of the bits 1 1. When a block of cells is erased, the cells are reset to the 1 1 state.
  • Each cell of a page being programmed to one of the other programmed states 01 , 00, or 10 has electrons injected onto its storage element until its threshold reaches the state corresponding respectively to the data being programmed into the cell.
  • Those cells being programmed into the 10 state are alternately pulsed with programming voltages and then verified by use of a read threshold level R-io.
  • R-io a read threshold level
  • a verify level V O o is used.
  • a verify level V O i is used.
  • the particular data bit pair assigned to each of the distributions 45, 47, 49 and 51 may be different that shown in Figure 6, and may even be rotated during operation of the memory system in order to even out wear on the array.
  • the amount of coupling can likewise be affected by the line width or spacing between adjacent elements. Hence the coupling and disturb of the cells can be reduced, and the data reliability enhanced, by increasing the spacing between certain elements or rows of elements.
  • a decision to space out certain rows may be made during array lay-out, and built into the lithography so that the pattern of which rows have greater line width or have greater spacing from other rows is repeated regularly and consistently across all the blocks. This can result in certain rows in each block having systematically greater channel lengths than other rows. Since current lithography techniques already are performed to create sub-wave length features, in order to counteract optical proximity effects, typical layout designs use layout lines of unequal thicknesses with wider select gates and other end-of-block features at the ends of each block.
  • the technology disclosed herein takes advantage of known and currently used features in lithography design to improve storage techniques.
  • Figure 7 shows an arrangement of storage elements (squares) in an array of memory cells in order to illustrate the capacitive coupling (dashed lines) between rows of them.
  • a storage element 725 of a row 730 for example, it is field coupled to storage elements in each of the adjacent rows 720 and 740.
  • the storage element 725 is most closely coupled with the storage elements 727 and 731 , because of their proximity, but also has a lesser degree of coupling with storage elements 726, 728, 732 and 730 that are further away.
  • the amount of coupling between two storage elements depends upon the distance between them, the dielectric constant of insulating material between them, whether there are any conductive surfaces between them, and the like.
  • Figure 7 illustrates only field coupling between rows of storage elements, though such coupling also exists between columns of storage elements.
  • the coupling between the rows has been found to be the cause of the apparent shift in programmed levels. For example, if data are programmed as distinct charge levels on the storage elements of the row 730, a later change in the charge levels on either or both of the adjacent rows 720 and 740 will cause a shift in the apparent charge levels that are then read from the storage elements of the row 730.
  • the amount of such a shift in the apparent charge level read from a particular storage element of the row 730 depends upon the degree of coupling with other storage elements whose charge was later changed in level and the amount of that change.
  • the later change is caused by programming data into the adjacent row, the amounts of the shifts that result are unknown unless the patterns of data programmed into each row are monitored and calculations of their effect made as part of each read operation.
  • row 720 is the last row programmed.
  • the elements in row 720 will not be affected by coupling from adjacent rows of cells.
  • the expected errors in programming in this row will be significantly reduced.
  • the present technology takes advantage of this expected superiority in data integrity for this row, and any other row in the array for which user data integrity can be expected to be greater than other rows in an array. As discussed below, this applies to cases, for example, where the average channel length is different on different word lines. CeIIs on word lines that benefit from a longer channel length are more reliable than cells on other word lines.
  • FIG. 11 a cross-sectional view of the NAND string 900 such as that described above with respect to Figure 3.
  • a plurality of cells comprising a NAND string is formed in p-well region 940.
  • a block includes word lines of stacked gate structures having control gates (900CG, 902CG, 904CG, 906CG . . . 960CG, 962CG, 980CG) and a floating gate (900FG, 902FG, 904FG, 906FG, 960FG, 962FG, 980FG).
  • control gates 900CG, 902CG, 904CG, 906CG . . . 960CG, 962CG, 980CG
  • a floating gate 900FG, 902FG, 904FG, 906FG, 960FG, 962FG, 980FG.
  • a control gate and floating gate for transistors 920 and 980.
  • the control gate and the floating gate are connected together.
  • word lines 958, 960 and 962 have a greater spacing S (S1 , S2) and/or line widths W (W1 , W2) than other word lines 906, 908, etc. (having spacing D and line width L).
  • the line widths W1 and W2, and spacings S1 and S2 may be gradually increasing toward the end of the block. As such, the expected reliability of lines 958 and 960 is greater, and such lines lend themselves to use with the technology presented herein.
  • a first step 802 is to read the user data and its stored ECC in a normal manner. This can be, for example, a page formed by a row of memory cells as heretofore described.
  • the read data is then compared with the ECC, in a step 805. If there are no errors in the data, as determined by comparison with the ECC, as indicated by the step 810, the read data is sent to the host, as shown by a step 860. This is the process that is followed for most all reads. In other cases, where one or more bit errors in the read data are present, the errors may be correctable, as determined by a step 820. If so, the read data is corrected, in a step 830, and the corrected data than sent to the host, through step 860.
  • any number of recovery techniques identified in numerous issued patents may be employed at step 825. These include those disclosed in, for example, U.S. Patent Nos. 7,046,548, 7,009,889 and 7,102,924. and U.S. Patent Publication 2005/0162913. If the data is recoverable at step 845, the data is send to the host. If not, the failed address is stored at step 850.
  • ECC is commonly calculated for each sector or other unit of data that is being stored at one time, and that ECC is stored along with the data.
  • ECC for one page of data may be stored remotely from the page.
  • Figure 9 illustrates a typical page and block example, where page attribute data is stored with the user data.
  • Figure 9 illustrates the array and data architectures of one existing commercial memory system. As illustrated in Figures 5 and 9, the existing memory array 302 is divided into a large number of blocks B. Each of these blocks, such as a block 3, is divided into a number of pages P, in this case 32 or 64 pages per block. Each page, such as the page 3, is configured in one or more sectors each storing 512 bytes of user data 902 and 16 bytes of attribute data 910. Note that up to eight sectors per word-line may be provided. Each page has the same general data structure.
  • the page attribute data includes ECC data 904 calculated from at least the user data 902, and overhead data 906.
  • the controller calculates the error-correcting code based on the data stored in the page.
  • the ECC code for the respective data area is then written to the respective page attribute area.
  • the ECC code is also read, and the reverse operation is applied to check that the data is correct.
  • an ECC algorithm may be used to correct data errors.
  • the number of errors that can be corrected depends on the correction strength of the algorithm used.
  • Simple Hamming codes provide the easiest hardware implementation, but can only correct single-bit errors.
  • Reed-Solomon codes can provide a more robust error correction and are used on many of today's controllers.
  • BCH Hocquenghem
  • space occupied by the ECC in the user attribute section of a sector is instead used for other page level or block level information.
  • This freed ECC space can be used to store block level information in one or more pages within the block for which the information is provided.
  • an exemplary data structure for a sector in a less-affected row is shown in Figure 10.
  • Sector 920 includes user data 902, which may comprise 512 bytes of user data, and a 16 byte spare data region 910.
  • Spare data region 910 includes ECC data 922 and other data 924.
  • the other data 924 now occupies some of the freed ECC data space.
  • Other data may now include block level overhead information as well as user data overhead.
  • ECC Error Correction Code
  • 6 - 8 bit of ECC correction is used per sector.
  • ECC is applied to each 512 bytes of user data in each page.
  • 26 check bits are required (1 symbol required for detection and one symbol required for correction, and 13 bits required per symbol).
  • detection and correction requires two bits, and detection of an error alone requires one bit.
  • 6 bits of correction per every 512 bytes 6 x 26 bits or 156 check bits are required; 8 bit ECC per 512 Bytes requires 206 bits of extra ECC check bits per 512 Bytes information.
  • Each user sector typically contains 512 user Bytes plus additional overhead information, part of this overhead information being the ECC check bits.
  • ECC detection may be reduced to as low as 1 bit per page, and correction to as low as 2 bits per page. It should be recognized that a reduction from 8 bit ECC to 7 bit ECC is much less drastic than a reduction from 2 bit to 1 bit ECC. Hence, ECC correction rates of 3 - 7 bits per reliable line may be used without substantially affecting the performance of the memory device. However in most cases, in order to free up a sufficient number of bits on some page, all that is required is to reduce the ECC capability by only a single bit of error correction capability in order to create a large number of freed up bits.
  • one or more word-lines may be designed with increased spacing and/or line width relative to other word lines in order to take advantage of the techniques discussed herein.
  • the same word line in each block is utilized. This uneven spacing and/or line width already exists due to lithography limitations and can simply be taken advantage of to create freed up bits by lowering ECC capability when possible.
  • the savings in space achieved by reducing the ECC resolution is used to store additional block level data in this row.
  • Such data may include, for example, block hot count, compressed block hot count, a block rewrite flag, and logical to physical translation information.
  • the block hot count reflects the number of times a particular page of data has been erased and re-written.
  • the compressed hot count is a technique (reflected in U.S. Patent No. 7,1 13,432, fully incorporated herein by reference) for recognizing the hot count in a more compact fashion.
  • the block rewrite flag is information such as that reflected in United States Patent Application Serial No.
  • any row which is less subject to adjacent cell coupling may take advantage of the technology disclosed herein.
  • any of the rows in a page may be programmed last, and such row may accommodate reducing the ECC information in such row.
  • Other rows which may be used in accordance with the technology are rows which are physically designed to be isolated from adjacent rows. For example, any row whose spacing from an adjacent row is sufficient to substantially reduce cell to cell coupling may allow for the advantages of the present technology.
  • one or more rows may be created with additional spacing and/or isolation structures from adjacent rows allowing use of the other information space for block level data.

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Abstract

Un procédé de stockage d'informations de temps-système de données de dispositif de mémoire dans des cellules de données dans une rangée de cellules, la rangée étant l'une d'une pluralité de rangées comprenant une unité de données, est décrit. Le procédé comprend le stockage d'informations d'attributs de données utilisateur comprenant un code de correction d'erreurs (922) dans une partie de temps-système d'un secteur de données dans la rangée adjacente à une partie du secteur de données stockant des données utilisateur (902). Des attributs de données de niveau de bloc sont stockés dans la partie de temps-système du secteur de données à un emplacement (924) occupé par des informations d'ECC dans les autres rangées, ladite rangée ayant une meilleure intégrité de données utilisateur et moins de bits d'ECC que les autres desdites rangées.
PCT/US2007/088830 2006-12-29 2007-12-26 Variation d'ecc page par page dans un dispositif de mémoire WO2008083161A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/618,686 US7870457B2 (en) 2006-12-29 2006-12-29 Page by page ECC variation in a memory device
US11/618,686 2006-12-29
US11/618,694 2006-12-29
US11/618,694 US7877665B2 (en) 2006-12-29 2006-12-29 Page by page ECC variation in a memory device

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TWI482014B (zh) * 2012-08-10 2015-04-21 Macronix Int Co Ltd 具有動態錯誤偵測及更正的記憶體
JP2020087491A (ja) * 2018-11-21 2020-06-04 キオクシア株式会社 半導体記憶装置

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US20060206770A1 (en) * 2003-01-28 2006-09-14 Jian Chen Non-Volatile Semiconductor Memory With Large Erase Blocks Storing Cycle Counts

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060206770A1 (en) * 2003-01-28 2006-09-14 Jian Chen Non-Volatile Semiconductor Memory With Large Erase Blocks Storing Cycle Counts

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