WO2008075315A2

WO2008075315A2 - Brazed flip-chip mounting of integrated circuits

Info

Publication number: WO2008075315A2
Application number: PCT/IB2007/055259
Authority: WO
Inventors: Christopher Wyland
Original assignee: Nxp B.V.
Priority date: 2006-12-20
Filing date: 2007-12-20
Publication date: 2008-06-26
Also published as: WO2008075315A3

Abstract

A method of flip-chip mounting a circuit to a substrate is provided by brazing together metallic elements formed on both the circuit and substrate. The brazing being achieved by initiating a chemical exothermic reaction in a multilayer stacked material disposed between the metallic elements on the circuit and substrate. Advantageously the chemical exothermic reaction provides a means of locally brazing the metallic elements without necessitating raising the circuit and substrate to a high temperature such as required in conventional flip-chip assembly with solder reflow. According to an exemplary embodiment of the invention the metallic elements are electrical conductors and an electrical trigger signal is provided via the metallic elements to initiate the chemical exothermic reaction.

Description

BRAZED FLIP-CHIP MOUNTING OF INTEGRATED CIRCUITS

FIELD OF THE INVENTION

The invention relates to integrated circuit packaging and more particularly to brazed electrical interconnections .

BACKGROUND OF THE INVENTION

"Flip-chip" is a term used to describe the multiplicity of mounting technologies that orient the face of an integrated circuit toward the interconnecting substrate. Flip-chip technology, originally developed by IBM and Delco in the 1960's, has become the preferred interconnection method for most integrated circuits. In "standard" packaging, the interconnection between the integrated circuit bare die (die) and its interconnecting substrate is made using wire. The die is attached to the interconnecting substrate face up, and then a wire is bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35 μm in diameter. In contrast with flip-chip packaging, the interconnection between the die and interconnecting substrate is made through a conductive "bump" that is placed directly on the die surface. The bumped die is then "flipped over" and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 μm high, and 100-125 μm in diameter.

Amongst the benefits of flip-chip packaging are that the parasitic electrical elements introduced by the bumps typically present one of the best interfaces from the die to the interconnecting substrate, which might be a second die, a ceramic substrate, a package, or a PCB. Additionally, power and ground connections can be placed throughout the face of the die, connections are made in a single operation, a so-called "gang" bonding technique, and bonding pads are not required to be placed at the periphery of the die - and in fact, the preferred arrangement is an array configuration over the face of the die. Array input / output connections also improves power delivery, high speed performance and provides relaxed pitch for ease of die product assembly.

The flip-chip connection is generally formed one of two ways: using solder or using conductive adhesive. By far, the most common packaging interconnect is solder which provides a hard metallic interface from the die to the interconnecting substrate. Previously, the dominant solder types were lead - tin alloys, with eutectic (63%Sn, 37%Pb) providing the lowest melting point of 183°C. However, recent demands for providing lead free solders due to environmental and health concerns that are established in documents such as the European Union directive Restriction of Hazardous Substances Directive (RoHS), have led to tin - silver alloy compositions becoming dominant, such as 97.5%Sn / 2.5%Ag with a melting point of 221⁰C. The solder bumped die is attached to the interconnecting substrate by a solder reflow process, which involves bringing the entire solder bumped die and interconnecting substrate up to above the melting point of the solder. As a result the integrated circuit must be capable of withstanding exposure to temperatures above 221°C, up from the previous 183°C. If 97.5%Sn / 2.5%Ag with a melting point of 221°C is employed for the final assembly step of a ball-grid array (BGA) package to a circuit board then a prior flip-chip solder process for the integrated circuit to the BGA package must be undertaken at a higher temperature, with sufficient margins for process variations etc, to prevent the previously soldered assembly detaching during the BGA package mounting process.

These high solder reflow temperatures place restrictions on the abovementioned materials and processing cycles, such as the final planarization and passivation layers of the integrated circuit, especially if there are multiple solder reflows from the initial bare die flip-chip to the final assembled PCB via chip-on carrier, package etc. There are advantages in manufacturing to processing such planarization and passivation layers at the lowest possible temperatures to reduce cracking, stress, delamination, and other degradations / defects being introduced into the fully processed integrated circuit die and wafer.

Additionally, the manufacturing of the integrated circuit die creates a similar cascade of acceptable temperatures, materials etc as advanced silicon integrated circuits can reach 20 or more levels with diffusions, penalizations, spin-on dielectrics, and etching. This cascade from significantly higher first level temperature processes onto the bare silicon substrate, further causes drive to lower processing temperatures as the number of levels increase, etch geometries become taller, linewidths narrower and etched features susceptible to distortion. Further, the circuit design places additional requirements on these materials and processes, which can be manifested as controlled high frequency impedances of transmission lines, leakage current limits, transistor linewidths for speed, reduced die footprint, and power dissipation.

Additionally, the use of solder materials, such as silver and tin, together with typical integrated circuit metallizations such as copper and tungsten, and those on or in packages such as gold and aluminum, results in complex metallurgical issues relating to electro-migration, etc. Simpler brazing processes, with exceptionally strong, sealed joints due to grain structure interaction, have not been feasible previously as they require processing temperatures above 450⁰C. The result is that at present, a limited number of options to eliminate the complex metallurgy in conjunction with the requirement to bring the entire integrated circuit die to temperatures over 200⁰C for solder reflow exist, one such process is an adhesive based flip-chip process.

Such adhesive flip-chip processes typically utilize anisotropic conductive materials, in either a film (ACF) or gel / liquid adhesive (ACA) form, as the electrical and mechanical joining agent. Anisotropic conductive film looks like paper and consists of thermosetting adhesive, conductive particles, and release film. However, such processes whilst offering advantageously lower processing temperatures have significant disadvantages of reduced mechanical strength and reduced reliability.

It would be advantageous therefore to provide a method of providing a brazed joint between the integrated circuit die and interconnecting substrate, without requiring the entire integrated circuit die temperature to be raised significantly. It would be further advantageous if the method allowed the same process to be employed repeatedly within an assembly, for example from die to BGA package, and BGA package to PCB,without requiring a multiplicity of materials, process conditions etc at each interface.

Further, it would be particularly advantageous if the method allowed the joining of conventional integrated circuit, package and PCB metallizations directly without organic fluxes, cleaning solvents and additional cleaning processes. Such conventional metallizations normally requiring processing at temperatures unacceptable in the post-processing of integrated circuit die, and additionally eliminated complex, expensive and automated processing equipment.

SUMMARY OF THE INVENTION

In accordance with the invention there is provided a brazed mounting for a circuit comprising a plurality of pads, at least one of which comprises a stack for forming a chemical exothermic reaction for brazing a contact on the circuit to the pad.

In accordance with another embodiment of the invention there is provided a component comprising a plurality of pads for electrical connection to an external circuit , at least one of the plurality of pads comprising a stack for forming a chemical exothermic reaction upon triggering thereof by an electrical trigger signal. In accordance with another embodiment of the invention there is provided a component mounting comprising a circuit board, the circuit board having a plurality of pads, at least one of the plurality of pads comprising a stack for forming a chemical exothermic reaction upon triggering thereof by an electrical trigger signal.

In accordance with another embodiment of the invention there is provided a method of mounting a circuit comprising providing a substrate, the substrate providing at least one of a plurality of first features, the plurality of first features forming a first part of a mechanical mount for the circuit, and providing an integrated circuit; the integrated circuit containing at least one of a plurality of second features, the plurality of second features being positioned at least in dependence upon the plurality of first features and forming a second part of the mechanical mount for the circuit; wherein brazing each of the plurality of first features to the corresponding one of the plurality of second features by a chemical exothermic reaction provides permanent mechanical mounting of the integrated circuit to the substrate.

In accordance with another embodiment of the invention there is provided an integrated circuit, the integrated circuit having a bump, the bump comprising a first metallic element of the integrated circuit, the first metallic element for providing at least one of an input signal to the integrated circuit, an output signal from the integrated circuit; and a mechanical interface for the integrated circuit. Also provided are a multilayer element, the multilayer element providing a chemical exothermic reaction upon triggering with a suitable electrical trigger signal, and a mounting substrate, the mounting substrate having a pad, the pad comprising a second metallic element of the mounting substrate, the second metallic element for providing at least one of an input coupling to a circuit, an output coupling from a circuit; and a mechanical interface for a circuit. Further alignment and mechanical interconnection is provided between the bump, multilayer element, and pad, the bump and pad being laterally aligned and mechanically in contact with the multilayer element such that initiating the chemical exothermic reaction in the multilayer element by providing the electrical trigger signal via at least one of the bump and pad for brazing the bump and pad together as a result of the chemical exothermic reaction within the multilayer element.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which: Fig. 1 illustrates a typical flip-chip integrated circuit assembly into a BGA package.

Fig. 2A illustrates a solder bumped integrated circuit die and substrate bond pad prior to assembly.

Fig. 2B illustrates a solder bumped integrated circuit die and substrate bond pad after assembly.

Fig. 3 illustrates the typical process flow and equipment requirements for a prior art solder bump reflow process.

Fig. 4A illustrates a prior art adhesive anisotropic conductive film flip-chip assembly.

Fig. 4B illustrates the adhesive anisotropic conductive film at high magnification.

Fig. 5 illustrates a multilayer exothermic film during reaction.

Fig. 6 illustrates a prior art package sealing methodology employing an exothermic film and solder alloy.

Fig. 7A illustrates a second prior art large area soldering process employing multilayer exothermic film and solder.

Fig. 7B illustrates a resulting soldered joint from a large area soldering process employing multilayer exothermic film and solder.

Fig. 8 A illustrates a first embodiment of the invention illustrating the brazing of an integrated circuit die bump to the pad of a PCB.

Fig. 8B illustrates the integrated circuit and carrier according to the first embodiment of Fig. 8 A prior to assembly.

Fig. 9A illustrates a second embodiment of the invention wherein brazing of mechanical joints is performed and adhesive anisotropic conductive film is employed within the flip-chip assembly for electrical connections.

Fig. 9B illustrates the second embodiment according to Fig. 9A in vertical cross-section. Fig. 10 illustrates a third embodiment of the invention wherein brazing of mechanical joints is performed and deformable conductive material is employed within the flip-chip assembly for electrical connections.

Fig. 1 IA illustrates a fourth embodiment of the invention wherein brazing of electrical interconnections providing power supply connections is employed with a second means of providing electrical connection for signal lines.

Fig. 1 IB illustrates a first cross-sectional view through the exemplary fourth embodiment according to Fig. 1 IA.

Fig. 11C illustrates a second cross-sectional view through the exemplary fourth embodiment according to Fig. 1 IA.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Referring to Fig. 1 illustrated is a typical flip-chip assembled BGA package 100 comprising a silicon integrated circuit 110 which is flip-chip mounted to a high density substrate 140 via an array of substrate pads 130 with solder bumps 120. The high-density substrate 140 forming the base of the BGA package 100 has its lower side populated with an array of BGA pads 150, each with a BGA ball 160.

The flip-chip interface between the high-density substrate 140 and the silicon integrated circuit 110 is filled with filler 170. Placed around the silicon integrated circuit 110 onto the filler 170 is a copper stiffener element 190 onto which the copper package lid 180 is assembled. The copper package lid 180 is also interfaced to the rear side of the silicon integrated circuit 110 by a thermally conductive adhesive attach 185. When the BGA package 100 was bonded to a circuit board (not shown for clarity) using lead-free 97.5%Sn / 2.5%Ag solder with a reflow temperature of 225°C, just slightly over the melting point of 221⁰C, and that a 10⁰C margin was provided within the design then for the silicon integrated circuit 110 to high density substrate 140 solder reflow would be performed at least at 235°C. However, a suitable 235°C melting point solder alloy (97% Sn / 3% Sb) is similarly subject to restrictions on use under RoHS due to the antimony content. Hence, a RoHS compliant process would require 95% Sn / 5% Ag solder which has a melting point of 241⁰C pushing the reflow process to approximately 245°C, now 20⁰C above the 97.5%Sn / 2.5%Ag reflow for the BGA package 100 to circuit board. Fig. 2A illustrates solder bumped integrated circuit die 200A and substrate 200B prior to assembly. Considering first, the solder bumped integrated circuit die 200A, shown is the integrated circuit 230, for example formed using silicon, indium phosphide or gallium arsenide based technologies, on which is disposed an electrical interconnection pad 232 that has been processed with a solder bump process to form a solder ball 240. The substrate 200B comprises a carrier 210 onto which has been patterned electrical interconnections 226. Atop the electrical interconnections 226 at positions corresponding to the solder bumps there is plated a pad interconnect 224. The carrier 210 in this illustrative embodiment is planarized with a dielectric 222, and the pad interconnect 224 is over plated with a wetting layer 228.

Fig. 2B illustrates the flip-chipped integrated circuit assembly 250 after the solder bumped integrated circuit die 200A and substrate 200B structures of Fig. 2A have been aligned, brought into contact and a solder reflow process completed. As shown the integrated circuit 230 and electrical interconnection pad 232 are unaffected by the solder reflow process. Equally the carrier 210, electrical interconnections 226, dielectric 222, pad interconnect 224 are unaffected by the solder reflow process. However, the reflowed solder ball 260 during the reflow process has deformed from the original solder ball 240, and is now attached to the reflowed wetting layer 238. The reflowed wetting layer 238 is now thinner than the wetting layer 228 of the substrate structure 200B prior to the solder reflow process as some of the wetting layer has intermixed with the solder of the reflowed solder ball 260.

Fig. 3 illustrates the typical process flow and equipment requirements for a prior art solder bump reflow process. Shown is an integrated circuit die 310 with solder balls 320 that has been flipped ready for the assembly process. Also shown is the substrate 340 to which the integrated circuit 310 is to be mounted together with its solder bumps 330. This assembly 300 is placed within a flux dip and flip-chip mounting workstation 370 wherein the pieceparts are dipped in flux and brought to a preliminary alignment. After flux dipping the assembly 300 is aligned into aligned kit 3000 wherein the solder balls 320 and solder bumps 340 are positioned relative to one another horizontally and laterally. As the die, package, substrate and other elements of such alignments are normally opaque such alignments sometimes requires use of X-ray inspection tools. Still within the flux dip and flip-chip mounting workstation 370 the integrated circuit die 310 and substrate 340 are brought into vertical contact as pre -reflowed assembly 350.

The pre-reflowed assembly 350 is transferred into a reflow oven 375 whereupon the pre -reflowed assembly 350 is exposed to a predetermined ramp profile of temperature versus time such that the solder balls 320 reach their melting point, wet the solder bumps 330, and then re-solidify joining the integrated circuit 310 and substrate 340 together, forming the reflowed assembly 360. This reflowed assembly 360 is then transferred to flux cleaning workstation 380 wherein residual flux is removed. Typical cleaning processes requiring organic solvents, and thorough cleaning is necessary as residual flux can cause corrosion to elements of the assembly. The reflowed assembly 360 is then moved to an under fill dispensing workstation 385 wherein an under fill material is dispensed to fill the space between the integrated circuit die 310 and substrate 340. This reflowed assembly 360 with liquid under fill is then placed within a curing oven 390, wherein it is exposed to another temperature - time cure profile to cure the under fill adhesive and yield the completed flip-chipped assembly 370.

As such the typical prior art solder reflow process for solder flip-chip requires 5 different workstations 370 through 390 to execute 6 steps. According to the design of these workstations 370 through 390 and the timing of each step it is sometimes necessary for several workstations of a single step, such as the flux dip and flip-chip mount workstation 370, for each workstation of another step, such as the reflow oven 375. The result is significant investment in capital for high volume packaging operation.

Fig. 4A illustrates a prior art adhesive anisotropic conductive film flip-chip assembly 400 and it's resultant structure 450. Shown are the flipped integrated circuit die 410, with electrical contacts 422 and 424 flipped, prior to assembly with the substrate 440 and it's electrical pads 432 and 434. Disposed between the flipped integrated circuit die 410 and substrate 440 is the anisotropic conductive film 460. For the assembly operation the entire adhesive anisotropic conductive film flip-chip assembly 400 is subjected to a combination of pressure, applied to the flipped integrated circuit die 410 and substrate 440 and temperature. Typical ACF materials require exposure to temperatures of 135°C to 150⁰C, which is still quite high, and the pressure required is 200-250 pounds per square inch.

Fig. 4B illustrates the resulting adhesive anisotropic conductive film 454 within the completed flip-chip assembly 450, at high magnification. Shown are the flipped integrated circuit 410, electrical contact 424, substrate 440, and electrical pad 434 as outlined previously in Fig. 4A. Also shown is the post-cured and compressed anisotropic conductive film 454, which contains conductive particles 456 which are normally in electrical isolation from each other except where they are contacted particles 458, which occurs only between the electrical pad 434 and electrical contact 424, where they are within a restricted portion of the adhesive anisotropic conductive film 454. In this manner the flip-chip assembly 450 is attached via the adhesive properties of the film 454, and electrically interconnected by the compressed particles 458. Typically the conductive particles 456 are silver coated glass microspheres of diameter 50μm.

Fig. 5 illustrates schematically a multilayer exothermic film during reaction. Shown is an unreacted region 500C comprising a multilayer stack of alternating layers of material A 540 and material B 550 which has been ignited at the ignition source 510. Examples of such material stacks are aluminum / nickel and titanium / boron, which when of atomic scale react under triggers such as voltage and pressure to form a region of reacted alloy material 520. Such a reaction being exothermic in forming the reacted material, and propagating away from the ignition source 510, such that during the reaction a region 500A of reacted alloy material 520 is formed, ahead of which is a reaction region 500B wherein the material reacts via intermediate compounds 530.

Fig. 6 illustrates a prior art large area package sealing methodology 600, wherein an integrated circuit die 650 is sealed within a package 640 by employing an exothermic film 632 and solder alloy performs 622, 624, 626 and 628 for the attachment of a package lid 610. Such an approach was reported by Rude et al ("Hermetic Sealing of Microelectronics Packages Using a Room

Temperature Soldering Process" IMAPS Symposium, Philadelphia, Pennsylvania, September 25- 29, 2005). As shown, the integrated circuit die 650 is mounted to a package 640 by a conventional approach. The package sealing methodology 600 relates to the attachment of the package lid 610. The upper periphery of the package 640 has a first solder perform, represented by solder alloy performs 624 and 628, atop which is placed the exothermic film 632.

Next a second solder preform, represented by solder alloy preforms 622 and 626, is stacked, followed by mounting of the package lid 610. Pressure is then applied to the assembled stack from the package lid 610 and package 640 triggering ignition of the exothermic film 632. The exothermic reaction of the exothermic film 632 is sufficient to melt the solder alloy preforms 622, 624, 626 and 628 and thereby solder the package lid 610 to the package 640. The thermal conductivity of typical low temperature co-fired ceramic packages such as employed for package 640 in the assembly of microelectronics presents a path of very low thermal conductivity to the integrated circuit die 650 such that the die typically does not experience significant thermal deviation from ambient. Fig. 7 illustrates a prior art large area soldering process employing an exothermic material being according to Makowiecki et al (U.S. Patent 5, 381, 944). Illustrated in Fig. 7 is a first workpiece 700A, such as a package body 640 of Fig. 6, and a second workpiece 700B, such as the package lid 610 of Fig. 6. Prior to soldering by the exothermic reaction, each workpiece 700A and 700B is prepared according to the following sequence: firstly the base workpieces 710 and 720 have an adhesion layer 714 deposited onto them, such as 500A of Ti; next an aluminum layer 715 is deposited, of thickness 1.75um, followed by the exothermic stack 716, which comprises alternating layers of titanium 717 and boron 718 to a thickness of a few microns; and atop the exothermic stack is a second aluminum layer 719 of 1.75um thickness.

In executing the soldering process, the two second aluminum layers 719 are brought into face-to- face contact and pressure is applied to the first workpiece 710 and second workpiece 720, respectively. The resulting ignition of the exothermic stack 716 causes the aluminum layers 715 and 719 on both workpieces 710 and 720 to melt and fuse forming a solid metallic joint.

Fig. 7B illustrates a resulting soldered joint 750 from a large area soldering process according to Subramanian et al. "Enhanced Thermal Performance by Direct Solder Attach of Silicon Dies" IMAPS ATW Symposium (October, 1 2004). Shown is a first workpiece 750, second workpiece 770, first indium solder layer 755, second indium solder layer 765 and exothermic foil 760. As shown, the second indium solder layer 765 is 120um thick, first indium solder layer 755 approximately 20um thick, and the exothermic foil 765 is approximately 80um thick, and the workpieces were between 8x8mm and 20x20mm in footprint. The large exothermic reaction results in cracking of the exothermic film 760 and indium solder flowing between, from both the first and second indium solder layers 755 and 765.

Fig. 8 illustrates a first embodiment of the invention illustrating a brazed flip-chip mounting 800. Shown is an integrated circuit die 810 with copper bumps 820 formed onto its electrical input / output pads. The integrated circuit die 810 is for attachment to a PCB 850. In corresponding positions on the PCB 850 are copper pads 840 which form the matching pattern to the electrical input / output pads of the integrated circuit die 810. Deposited onto one or another of the copper bumps 820 and copper pads 840 is an exothermic aluminum / nickel multilayer stack 830.

In this exemplary embodiment of the invention the integrated circuit die is positioned using a conventional flip-chip die tool (not shown for clarity) and held in place with nominal force. Further the PCB 850 is positioned within a prober workstation (also not shown for clarity). Ignition of the exothermic aluminum / nickel multilayer stack 830 is initiated from the prober workstation by the application of appropriate voltages from the prober. The resulting exothermic reaction is sufficient to increase the local temperature to the point that the copper pad 840 and copper bump 820 braze to one another as a copper-copper joint. It would be apparent that the exothermic reaction whilst raising the temperature locally to over 1085⁰C for the copper to melt is produced from a very small amount of exothermic material 830, which therefore does not result in a large overall thermal power load and resulting significant rise in the temperature of the integrated circuit die 810 or PCB 850.

It would be apparent to one skilled in the art that the application of appropriate voltages from the prober workstation is part of its normal mode of operation. Further, the initiation of the ignition of the exothermic material 830 is optionally performed only after the prober workstation has characterized the integrated circuit die 810 such that only known good die are brazed to a PCB 850. It would also be apparent to one skilled in the art that the localized exothermic brazing in not increasing the die temperature significantly overcomes major disadvantage of the prior art flip- chip solder approach in not requiring the entire integrated circuit die 810 temperature to be raised to over 220⁰C, nor the PCB 850 temperature. As such the approach allows a much wider choice of materials for the processing of the integrated circuit die 810 and PCB 850 as now the upper temperature limit is solely the operating environment of the resulting assembly, typically less than 125°C. Hence, lower stress materials, alternate polymers and plastics are useful in the design and assembly of both the integrated circuit die 810 and PCB 850.

Referring to Fig. 8B the brazed flip-chip mounting 800, according to the first embodiment of the invention, is shown in plan view for the PCB 850 and integrated circuit die 810 prior to flipping, alignment and brazing. As shown the PCB 850 is patterned with electrical interconnections 840, which terminate in bond pads 835. The bond pads for electrical interconnect from the PCB 850 to a package or other carrier, not shown for clarity, by flip-chip or wire bonding. Each electrical interconnection 840 is shown having a square pad in the same array format as the electrical interconnection to the die bumps 820. Each electrical interconnection 840 has formed upon this square pad a circular exothermic pad 830 for ignition to form the brazed joint between integrated circuit die 810 and PCB 850.

In this manner when the integrated circuit die 810 is flipped and aligned with the PCB 850 then the array of die bumps 820 matches one for one with the circular exothermic pads 830. In this manner with appropriate electrical probes contacting the bond pads 835 the circular exothermic pads 830 are ignitable. Triggering of the circular exothermic pads 830 is variable according to the circuit and thermal loading requirements of the integrated circuit die 810. Further, trigger timing is also variable for triggering one or more exothermic reactions simultaneously or in sequence. Exemplary triggering include, but are not limited to, one pad at a time, columns of pads, rows of pads, all pads, and predetermined subsets of the pads. Alternatively, bond pads 835 are ganged prior to the ignition and electrically isolated subsequently.

Of course, brazing of a metallic structure on an integrated circuit die to a carrier is performable without the resulting brazed junctions forming part of the electrical input / output pathways of the integrated circuit. Such an approach is outlined in Fig. 9, according to a second embodiment of the invention wherein brazing of mechanical joints is performed and adhesive anisotropic conductive film is employed within the flip-chip assembly for electrical connections.

Shown are plan views for PCB 920 and integrated circuit die 960 prior to flipping, alignment and brazing of the brazed flip-chip mounting 900 of Fig. 9B. As shown, the PCB 920 has an array of electrical interconnections 930 forming an array of pads for interconnection to the integrated circuit die 920. Also shown are four cross mounting metallizations 910 that are connected to each of four probe points 935, respectively. Atop each mounting metallization 910 is shown an exothermic film element 980.

Now referring to the integrated circuit die 960, shown are an array of die bumps 950 matching the pads on the PCB 920. Shown also is a single continuous film over the array of die bumps 950, comprising an adhesive anisotropic conductive film 970. Also shown are four mechanical mounting points 940 for the integrated circuit die 960.

In assembly the integrated circuit die 960 with adhesive anisotropic conductive film 970 is flipped, aligned and brought into contact with the PCB 920. According to this second embodiment of the invention, pressure is applied to the integrated circuit die 960 to bring the mounting metallizations 910 and exothermic film elements 980 into contact with the mechanical mounting points 940. Application of appropriate electrical trigger signal to the probe points 935 triggers the exothermic reaction within the exothermic film elements 980 and results in brazing of the die bumps 950 to the electrical interconnections 930.

As shown in Fig. 9B the resulting flip-chipped brazed mechanical assembly with adhesive film electrical interconnect is shown as assembly 900 in cross-section. As shown the integrated circuit die 960 is uppermost, and the PCB 920 lowermost. At the left and right edges the brazed mechanical joint is shown comprising mechanical mounting points 940, exothermic film element 980 and mounting metallization 910, which are in physical contact. Shown inside these are the electrical interconnections 930 and the die bumps 950 which are physically separated by the adhesive anisotropic film 970 which provides electrical interconnection only between the electrical interconnections 930 and the die bumps 950.

The metallizations on the PCB 920 and integrated circuit die 960 are shown as being of different thicknesses and designs for the mechanical mounting and electrical interconnections. Alternatively, these designs and specific thicknesses are varied according to requirements of the assembly and manufacturing processes of die, PCB, circuit and exothermic film / adhesive film.

Referring to Fig. 10 shown is an exemplary third embodiment of the invention wherein a flip- chipped brazed mechanical assembly with deformable conductive electrical interconnect is shown as assembly 1000 in cross-section. Within this exemplary embodiment of the layout of the PCB 1020 and integrated circuit die 1060 are essentially identical to those outlined in Fig. 9A. As with the prior cross-sectional view of the exemplary second embodiment of Fig. 9B the integrated circuit die 1060 is uppermost, and the PCB 1020 lowermost. At the left and right edges the brazed mechanical joint is shown comprising mechanical mounting points 1040, exothermic film element 1080 and mounting metallization 1010, which are in physical contact. Shown inside these are the electrical interconnections 1030 and the die bumps 1050 which are physically separated by a deformable conductive layer 1070, this provides electrical interconnection only between the electrical interconnections 1030 and the die bumps 1050.

Within the exemplary embodiment of Fig. 10 the deformable conductive layer allows the PCB 1020 and integrated circuit die 1060 to be brought into alignment and mechanically abutted one to another. As such the vertical movement of the PCB 1020 and integrated circuit die 1060 ceases under application of pressure when the mechanical mounting points 1040 and mounting metallization 1010 are in physical contact, one of the mechanical mounting points 1040 and mounting metallization 1010 having the exothermic film element 1080 deposited upon its upper surface prior to the flip-chip alignment process. Prior to this physical contact the deformable conductive layer 1070 makes physical contact to the electrical interconnections 1030 and die bumps 1050 and deforms to accommodate final vertical movement between these as the physical contact of the mechanical mounting points 1040 and mounting metallization 1010 is made. The metallizations on the PCB 1020 and integrated circuit die 1060 are shown as being of different thicknesses and designs for the mechanical mounting and electrical interconnections. Alternatively, these designs and specific thicknesses are varied according to requirements of the assembly and manufacturing processes of die, PCB, circuit and exothermic film. Optionally, the deformable conductive layer 1070 is an anisotropic conductive film or a soft metal such as indium.

Fig. 1 IA illustrates a fourth embodiment of the invention wherein brazing of electrical interconnections providing power supply connections is employed along with a second means of providing electrical connection for signal lines for a BGA package assembly 1100. Shown is a 1 Ox 10 array of package pads 1160 on the bottom of a BGA package (not shown for clarity) which are, of which the central four pads are to be a power supply connections Vss 1150 and the outer ring are to be ground connections 1110. The ground connections 1110 from the BGA package interconnect to a solid continuous ground plane 1130 of the PCB (not shown for clarity). Similarly the four power supply connections Vss 1150 connected to a Vss power bus 1140. Also shown are the PCB signal trace connections 1120 which provide input and output signal connections to the BGA package from the PCB.

In this exemplary embodiment the power supply connections Vss 1150 and ground connections 1110 are brazed together using an exothermic material between them, which has not been shown for clarity. This exothermic material being equivalent to the exothermic film element 1080 of Fig. 10 for example and being deposited onto the power supply connections Vss 1150 and ground connections 1110. Alternatively the exothermic material may have been deposited and locally patterned onto the PCB at the appropriate locations to a match the pattern of the power supply connections Vss 1150 and ground connections 1110. Electrical connection between the PCB signal trace connections 1120 and package pads 1160 for the input and output signal connections being implemented, for example with an electrically conductive and deformable material which has not been shown for clarity, such as deformable conductive layer 1070 of Fig. 10 or adhesive anisotropic film 970 of Fig. 7. Optionally the electrically conductive and deformable material may also be non-adhesive, may be a screen printed gel rather than a discrete film, and may be a material curing over a period post manufacture without exposure to high temperature, such as a silicone elastomer.

Now referring to Fig. 1 IB illustrated is the cross-sectional view X-X through the center of the BGA package assembly 1100, comprising the package base 1170 of the BGA package and the PCB 1180. Shown on the upper surface of the PCB 1180 are the Vss power bus 1140, ground plane 1130, and signal trace connections 1120. Shown on the lower side of the package base 1170 are package pads 1160, of which the outer pair are ground connections 1110 and inner pair are power supply connections Vss 1150.

Shown between the power supply connections Vss 1150 and Vss power bus 1140, and between the ground plane 1130 and ground connections 1110 is the exothermic material 1195 used to braze the respective connections together. Also shown between the package pads 1160 and signal trace connections 1120 is the electrically conductive and deformable material 1190.

Now referring to Fig. 11C illustrated is the second cross-sectional view Y-Y through the last row of the BGA package assembly 1100, comprising the package base 1170 of the BGA package and the PCB 1180. Shown on the upper surface of the PCB 1180 is the ground plane 1130, and shown on the lower side of the package base 1170 are ground connections 1110. Shown between the ground plane 1130 and ground connections 1110 is the exothermic material 1195 used to braze the respective connections together. In this manner the mechanical joining is made solely through electrical contacts which provide power supply connections, potentially allowing the choice of exothermic material and / or its thickness, layout and design to be broader as the finished reacted exothermic material would not need to provide good frequency performance for the signal line connections.

Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention.

Claims

CLAIMS:

1. A brazed mounting for a circuit comprising;

a plurality of pads, at least one of which comprises a stack for forming a chemical exothermic reaction for brazing a contact on the circuit to the pad.

2. A brazed mounting according to claim 1 wherein,

the circuit is an integrated circuit.

3. A brazed mounting according to claim 1 wherein, the pad and contact provide an electrical connection.

4. A brazed mounting according to claim 1 wherein, the circuit is a photonic circuit.

5. A brazed mounting according to claim 4 wherein, the pad and contact provide an electrical connection.

6. A brazed mounting according to claim 5 wherein, the electrical connection is at least one of a ground connection, a power supply connection, and a signal connection.

7. A brazed mounting according to claim 1 wherein, the plurality of pads are an array of pads, the array being at least one of a linear array, a rectangular array and a hexagonal array.

8. A brazed mounting according to claim 1 wherein the stack for forming a chemical exothermic reaction for brazing a contact on the circuit to the pad comprises layers selected for reacting upon provision of an electrical trigger signal to at least one of the pad, contact, and a substrate of the circuit.

9. A component comprising;

a plurality of pads for electrical connection to an external circuit , at least one of the plurality of pads comprising a stack for forming a chemical exothermic reaction upon triggering thereof by an electrical trigger signal.

10. A component mounting comprising; a circuit board, the circuit board having a plurality of pads, at least one of the plurality of pads comprising a stack for forming a chemical exothermic reaction upon triggering thereof by an electrical trigger signal.

11. A component mounting according to claim 10 wherein, the electrical trigger signal upon triggering the chemical exothermic reaction results in the at least one of the plurality of pads being brazed to one of a plurality of contacts.

12. A component mounting according to claim 10 wherein, the at least one of the plurality of pads is an electrical connection.

13. A component mounting according to claim 12 wherein, the electrical connection is at least one of a ground connection, a power supply connection, and a signal connection.

14. A component mounting according to claim 10 wherein, the circuit board is at least one of a printed circuit board, a flexible circuit board, a silicon substrate, a ceramic substrate, a lead- frame, and a semiconductor substrate.

15. A component mounting according to claim 10 wherein, the component comprises at least one of an integrated circuit, an opto-electronic component, a photonic circuit, a superconducting circuit, and a MEMS circuit.

16. A component mounting according to claim 14 wherein, triggering by the electrical trigger signal comprises providing the electrical trigger signal to the circuit board.

17. A component mounting according to claim 15 wherein, triggering by the electrical trigger signal comprises providing the electrical trigger signal to at least one of the component and a substrate forming part of the component.

18. A method of mounting a circuit comprising;

providing a substrate, the substrate providing at least one of a plurality of first features, the plurality of first features forming a first part of a mechanical mount for the circuit;

providing an integrated circuit; the integrated circuit containing at least one of a plurality of second features, the plurality of second features being positioned at least in dependence upon the plurality of first features and forming a second part of the mechanical mount for the circuit; wherein

brazing each of the plurality of first features to the corresponding one of the plurality of second features by a chemical exothermic reaction provides permanent mechanical mounting of the integrated circuit to the substrate.

19. A method of mounting a circuit according to claim 18 wherein, brazing by a chemical exothermic reaction comprises brazing absent any material having a melting point below 400⁰C.

20. A method of mounting a circuit according to claim 18 wherein, brazing by a chemical exothermic reaction comprises performing the brazing with the substrate and integrated circuit both being at ambient temperature.

21. A method of mounting a circuit according to claim 20 wherein, being at ambient temperature comprises being at temperatures below 100⁰C.

22. A method of mounting a circuit according to claim 18 wherein, brazing the first features and second features results in providing an electrical connection between the substrate and integrated circuit.

23. A method of mounting a circuit according to claim 18 wherein, providing the chemical exothermic reaction comprises providing at least a stack onto at least one of the plurality of first features and the plurality of second features and providing a triggering of the chemical exothermic reaction by at least one of providing a voltage and pressure.

24. A method of mounting a circuit according to claim 18 wherein, providing a voltage comprises providing a voltage to the plurality of first features at least one of simultaneously and selectively.

25. A method comprising;

providing an integrated circuit, the integrated circuit having a bump, the bump comprising a first metallic element of the integrated circuit, the first metallic element for providing at least one of an input signal to the integrated circuit, an output signal from the integrated circuit; and a mechanical interface for the integrated circuit; providing a multilayer element, the multilayer element providing a chemical exothermic reaction upon triggering with a suitable electrical trigger signal;

providing a mounting substrate, the mounting substrate having a pad, the pad comprising a second metallic element of the mounting substrate, the second metallic element for providing at least one of an input coupling to a circuit, an output coupling from a circuit; and a mechanical interface for a circuit;

providing an alignment and mechanical interconnection between the bump, multilayer element, and pad, the bump and pad being laterally aligned and mechanically in contact with the multilayer element;

initiating the chemical exothermic reaction in the multilayer element by providing the electrical trigger signal via at least one of the bump and pad for brazing the bump and pad together as a result of the chemical exothermic reaction within the multilayer element.

26. A method according to claim 25 wherein, providing the integrated circuit comprises providing a circuit manufactured using a semiconductor technology based upon at least one of silicon, silicon-germanium, gallium arsenide, indium phosphide, gallium nitride and polymers.

27. A method according to claim 25 wherein, providing the mounting substrate comprises providing at least one of a semiconductor circuit, a ceramic substrate, a polymer substrate, a printed circuit board, a metallic substrate and a package.

28. A method according to claim 25 wherein, providing at least one of the first metallic element and second metallic element comprises providing a metal, the metal being at least one of copper, gold, nickel, palladium, platinum, chromium, titanium, tungsten and aluminum.

29. A method according to claim 28 wherein, providing the metal comprises providing at least one of a deposited film and a plated film.

30. A method according to claim 28 wherein, providing the metal comprises providing the metal absent any promoter layer on top of the film, the promoter layer being at least one of a wetting layer, a solder alloy and a brazing alloy.

31. A method according to claim 25 wherein; providing the multilayer element comprises providing a structure absent at least one of a wetting layer, a solder alloy and a brazing alloy.

32. A method according to claim 25 wherein, providing the multilayer element comprises providing a multilayer metallic stack on at least one of the bump and pad.

33. A method according to claim 32 wherein, providing the multilayer metallic stack comprises providing at least one of a deposited film and a mechanically placed foil.

34. A method according to claim 25 wherein, providing the multilayer element comprises providing alternating layers of materials A and B.

35. A method according to claim 34 wherein, providing alternating layers of materials A and B comprises providing any materials amenable to at least one of mixing of neighboring atoms and changes in chemical bonding in response to the electrical trigger signal and providing an exothermic process.

36. A method according to claim 34 wherein, providing alternating layers of materials A and B comprises providing at least one of a metal, a suicide, an aluminide, a boride, a carbide, an oxide, a thermite reacting compound, an alloy, a metallic glass and a metal ceramic composite.

37. A method according to claim 36 wherein, providing a metal comprises providing at least one of rhodium, zirconium, copper, aluminum, boron, titanium, nickel, carbon, and iron.

38. A method according to claim 25 wherein, providing the multilayer element comprises providing an electrically conductive structure.

39. A method according to claim 38 wherein, providing an electrically conductive structure comprises providing a structure that is electrically conductive both before and after the exothermic reaction.

40. A method according to claim 38 wherein, providing an electrically conductive structure comprises providing a structure which is electrically conductive before the exothermic reaction.

41. A method according to claim 25 wherein, providing the electrical trigger signal comprises providing an electrical signal being at least one of an electrical signal associated with normal operation of the integrated circuit and other than normal operation of the integrated circuit.

42. A method according to claim 25 wherein, providing the electrical trigger signal comprises providing the electrical trigger signal via at least one of the mounting substrate and a substrate forming part of the integrated circuit die.

43. A method according to claim 25 wherein, providing the electrical trigger signal further comprises applying pressure to at least one of the mounting substrate and integrated circuit die.

44. A method according to claim 43 wherein, applying pressure comprises providing enough pressure to allow the electrical trigger signal to initiate the chemical exothermic reaction, the electrical trigger signal insufficient alone to initiate the chemical exothermic reaction.

45. A method according to claim 25 wherein, providing an integrated circuit comprises providing an integrated circuit having a plurality of bumps, providing a multilayer element comprises providing at least one of a single multilayer element or a plurality of multilayer elements, providing a mounting substrate comprises providing the mounting substrate having a plurality of pads providing an alignment and mechanical interconnection comprises providing an alignment and mechanical interconnection between the plurality of bumps, at least one of a single multilayer element or a plurality of multilayer elements, and pads, the plurality of bumps and pads being laterally aligned and mechanically in contact with the at least one of a single multilayer element or a plurality of multilayer elements, and providing the electrical trigger signal comprises providing the electrical signal to each of the plurality of at least one of bumps and pads at a time.