Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the processor performance state adjusts based on demand.
• CPU central processor unit
• the processor may transition to a lower performance state to conserve power.
• the processor may transition to a higher performance state and may consume more power.
• a target P-state selection is based on the combination of CPU utilization and the last selected P-state.
• TM Turbo Mode
• ACPI Advanced Configuration and Power Interface
• P-state information each selectable core frequency is represented with corresponding control, status, and latency information.
• a replacement of the highest frequency of the last selected P-state with a TM frequency may result in, an increased usage of additional processing power when not needed. Furthermore, this may result in performance degrading caused by P-state fluctuations due to unnecessary transitions to TM.
• FIG. 1 is a schematic illustration of a block diagram of computer system according to an exemplary embodiment of the present invention
• FIG. 2 is a schematic illustration of a block diagram of a portion of a processing platform according to an exemplary embodiment of the invention.
• FIG. 3 is an illustration of flowchart of a method of calculating a target P-state in
• the present invention may be used in a variety of applications. Although the present invention is not limited in this respect, the circuits and techniques disclosed herein may be used in many apparatuses such as computer systems, processors, CPU or the like. Processors intended to be included within the scope of the present invention include, by way of example only, a reduced instruction set computer (RISC), a processor that have a pipeline, a complex instruction set computer (CISC), a multi core processor, a computer platform and the like.
• RISC reduced instruction set computer
• CISC complex instruction set computer
• multi core processor a computer platform and the like.
• Some embodiments of the invention may be implemented, for example, using a machine-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine (for example, by a processor and/or by other suitable machines), cause the machine to perform a method and/or operations in accordance with embodiments of the invention.
• a machine for example, by a processor and/or by other suitable machines
• Such machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software.
• the machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory (CD-ROM), Compact Disk Recordable (CD-R), Compact Disk Rewriteable (CD-RW), optical disk, magnetic media, various types of Digital Versatile Disks (DVDs), a tape, a cassette, or the like.
• any suitable type of memory unit for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory
• the instructions may include any suitable type of code, for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, or the like, and may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, e.g., C, C++, Java, BASIC, Pascal, Fortran, Cobol, assembly language, machine code, or the like.
• code for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, or the like
• suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language e.g., C, C++, Java, BASIC, Pascal, Fortran, Cobol, assembly language, machine code, or the like.
• FIG. 1 a block diagram of a computer system 100 according to an exemplary embodiment of the invention is shown.
• computer system 100 may be a personal computer (PC), a personal digital assistant (PDA), an Internet appliance, a cellular telephone, a laptop computer, a mobile unit, a wireless communication device and/or any other computing device.
• PC personal computer
• PDA personal digital assistant
• Internet appliance a cellular telephone
• laptop computer a laptop computer
• mobile unit a mobile unit
• wireless communication device any other computing device.
• computer system 100 may include a main processing unit 110 powered by a power supply 120.
• main processing unit 110 may include a Turbo Mode (TM) capable processor 130 electrically coupled by a system interconnect 135 to a memory device 140 and one or more interface circuits 150.
• the system interconnect 135 may be an address/data bus, if desired. It should be understood that interconnects other than busses may be used to connect TM capable processor 130 to memory device 140. For example, one or more dedicated lines and/or a crossbar may be used to connect processor 130 to memory device 140.
• TM capable processor 130 may include an operating system 139 and a CPU 136 which includes one or more cores 137.
• Operating system 139 may execute an ACPI 132 and an operating system power management (OSPM) application 134, if desired.
• processor 130 may include a cache memory (not shown), such as, for example, static random access memory (SRAM) and the like, or any other type of internal integrated memory.
• Memory device 140 may include a dynamic random access memory (DRAM), a non-volatile memory, or the like. In one example, memory device 140 may store a software program which may be executed by processor 130, if desired.
• interface circuit(s) 150 may include an Ethernet interface and/or a Universal Serial Bus (USB) interface, and/or the like.
• one or more input devices 160 may be connected to interface circuits 150 for entering data and commands into the main processing unit 110.
• input devices 160 may include a keyboard, mouse, touch screen, track pad, track ball, isopoint, a voice recognition system, and/or the like.
• the output devices 170 may be operably coupled to main processing unit 110 via one or more of the interface circuits 150 and may include one or more displays, printers, speakers, and/or other output devices, if desired.
• one of the output devices may be a display.
• the display may be a cathode ray tube (CRT), a liquid crystal display (LCD), or any other type of display.
• computer system 100 may include one or more storage devices 180.
• computer system 100 may include one or more hard drives, one or more compact disk (CD) drive, one or more digital versatile disk drives (DVD), and/or other computer media input/output (I/O) devices, if desired.
• computer system 100 may exchange data with other devices via a connection to a network 190.
• the network connection may include any type of network connection, such as an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, etc.
• Network 190 may be any type of network, such as the Internet, a telephone network, a cable network, a wireless network such as, for example, a network complying IEEE standard 802.11, 1999 include one or more IEEE 802.11 related standards, IEEE 802.16 Standard for Wireless Metropolitan Area Networks and/or the like.
• TM capable processor 130 may operate in two or more operating frequencies. A selection of the operating frequency of TM capable processor 130 may be done by OSPM 134 based on TM capable processor 130 load observed over a window of time, if desired.
• ACPI 132 may provide a target P-state to OSPM 134.
• OSPM 134 may set a power consumption target point and may modify the processor operating frequency and/or voltage according to the selected entry in the target P-state.
• the target P- state that related to the processor turbo mode may be provided by a basic input output system (BIOS) 145. This, turbo related P-state may be related to the highest operating frequency of the processor in turbo mode.
• BIOS basic input output system
• OSPM 134 logic may accurately select the appropriate P-state needed to meet computer system 100 performance needs. It should be understood that ACPI 132 and/or OSPM 134 may be implemented by hardware, by software, and/or by any combination of hardware and/or software.
• portion of processing platform 200 may include an operating system 205 including an OSMP 210 and an ACPI 220, a CPU 225 which includes cores 1...N 230, and a BIOS 245 which includes a turbo mode 240 and one or more P-state tables 250.
• an actual counts counter (ACNT) 260 and maximum counts counter (MCNT) 270 may be operably coupled to each one of core 1...N 230.
• TM enabled processing platform 200 may use OSMP 210, ACPI 220, ACNT260 and MCNT 270, and P-State tables 250 to set an optimal P-state for cores 1...N 230 of processing platform 200 while the TM enabled processor is running in turbo mode 240.
• P-State tables 230 may include the below table e.g., Table 1 for each core 1...N of the processing platform 200.
• Table 1 may include a plurality of selectable P-states (e.g., PO, P1....P4).
• OSMP 210 may use a selected P-state to set an operating frequency and an operating voltage of each one of cores 1...N 230, independently.
• table 1 may include command word associated with each P-state.
• the command word may download parameters of the selected P-state (e.g., PSS Frequency, %Max Frequency, Increase Level, Decrease Level and the like to control and set CPU 225 it in the desired P-state.
• selectable P- states P1-P4 may include an actual selectable operating frequency (e.g., PSS Frequency) of CPU 225. For example, if Pl is selected the operating frequency of CPU 225 may be set to 3.000 MHz.
• PO is a turbo mode P-state and may be selected when TM enabled processor is running in turbo mode 240.
• the PSS Frequency of PO does not represent an actual selectable frequency but includes ACPI information of TM frequency (e.g. 3333 MHz) which is represented by a number which is higher then the actual selectable frequency of the core.
• TM frequency e.g. 3333 MHz
• the number of PO state is the actual highest selected frequency plus 1 (e.g. 3001 MHz).
• Writing a control word and/or a command to CPU 225 or to one of its cores (e.g., core 1...N 230) to change frequency from the Pl to PO will put CPU 225 into TM.
• writing the command word associated with 3001MHz on table 1 may set the CPU to run in a highest possible frequency e.g. 3333MHz which is different then the frequency indicated in table 1 (e.g., 3001 MHz).
• the non Turbo frequency of 3001MHz in this example, may be considered as "Guaranteed” frequency with is exposed by the CPU table while the 3333 MHz is the actual "Turbo" frequency, although the scope of the present invention is not limited in this respect.
• PO may be selected only when a core of the processing platform 200 is operating in turbo mode 250. In PO state the CPU 225 and/or at least on of its cores 1...N 230, may use its maximum performance capability and may consume maximum power.
• P-State tables may represent power consumption state of cores 1...N 230 during normal operating mode.
• Pl state represents an actual guaranteed frequency (e.g. 3000 MHz).
• the performance capability the processor In this performance power state, the performance capability the processor is limited below its maximum and consumes less than maximum power.
• P2-P4 P-states the performance capability the processor may be decreased until its minimum level (at P4) and consumes minimal power while remaining in an active state.
• table 1 may not encode the frequency directly. Instead, the table may store the multiplier setting that is multiplied by a front-side bus frequency to generate the core frequency.
• TM may only be used when the core utilization requires the need for additional processing power and since the TM frequency is not guaranteed, the OSPM 210 may increase or decrease the P-state based on the increase and decrease in the core utilization.
• ACNT 260 and MCNT 270 may be used.
• MCNT 270 may count maximum number of execute clocks at the maximum non-turbo mode core frequency and the ACNT 260 may count the number of execute clocks at actual core frequency.
• the ratio of (ACNTMCNT)* 100 may be used by OSPM 210 to accurately select the appropriate P- state needed to meet the system's performance needs. For example, if the ration is higher then 100% it may indicate that the core is in turbo mode and PO may be selected.
• OSPM 210 may command ACPI 220 to increase the frequency to the maximum operating frequency, if desired.
• the command may be store in a command register (not shown) and may include a number (e.g., 3.4, 3.2, etc). The number may represent the desired operating frequency of the core according to the selected P-State.
• FIG. 3 an illustration of flowchart of a method of calculating the target P-state in Turbo Mode capable processors according to exemplary embodiments of the invention is shown.
• the method of calculating the target P-state in TM capable processors may use a hardware coordinated feedback provided by counters (Actual Count) ACNT and (Maximum count) MCNT.
• the MCNT may count maximum number of execute clocks at the maximum non-turbo mode core frequency and the ACNT may count the number of execute clocks at actual core frequency.
• the ACNT/MCNT ratio is calculated (text block 310).
• the target P-state is calculated by multiplying the calculated effective P-state (e.g., P_State e ff ec tive) with a CPU utilization value (e.g., % Busy).
• P-state ta rget % Busy*P_State e ff ec tive (text block 320). If the target P-state is different then the current P-state (decision block 330) then OSMP may set a logical processor or a core to a new P-state and reset counters ACNT and MCNT (text block 340). If the target P-state is substantially equal to the current P-state, the current P-state may remain unchanged, although the scope of the present invention is in no way limited in this respect.
• ACNT/MCNT ratio when the processor is running in Turbo Mode ACNT/MCNT ratio may be greater than 100% and OSPM logic may select the TM P-state.
• ACPI P-state control algorithm may optimize a runtime power consumption of the TM enabled processor according to desired performance of the processor.
• An ACPI P-state control algorithm may dynamically adjust the TM enabled processor operation frequency of each core according to a software execution load of the processor.

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• 2007
  • 2007-10-30 CN CN2007800458395A patent/CN101558383B/zh not_active Expired - Fee Related
  • 2007-10-30 DE DE112007003007T patent/DE112007003007T5/de not_active Ceased
  • 2007-10-30 WO PCT/US2007/082959 patent/WO2008073597A1/en active Application Filing

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