WO2008068805A1

WO2008068805A1 - Semiconductor device, manufacturing method for semiconductor device, and designing method for multilayer wiring

Info

Publication number: WO2008068805A1
Application number: PCT/JP2006/323969
Authority: WO
Inventors: Hirosato Ochimizu; Atsuhiro Tsukune; Hiroshi Kudo
Original assignee: Fujitsu Microelectronics Limited
Priority date: 2006-11-30
Filing date: 2006-11-30
Publication date: 2008-06-12

Abstract

Intended is to enhance the mechanical strength of a multilayer wiring. In and over a multilayer wiring (40) of a circuit layout region (2) of a semiconductor device (1), dummy pattern structures (120), (130) and (140) are formed to bypass circuit wirings (55), (66), (86) and so on. In a peripheral region (3) having no wiring, on the other hand, there are formed straight dummy pattern structures (100) and (110). These dummy pattern structures (100), (110), (120), (130) and (140) are so formed in the multilayer wiring (40) as to continue over the plural layers, so that the mechanical strength in the laminating direction is enhanced.

Description

Specification

Semiconductor device, semiconductor device manufacturing method, and multilayer wiring design method

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a multilayer wiring design method.

In particular, the present invention relates to a semiconductor device using a low relative dielectric constant material for an interlayer insulating film, a manufacturing method thereof, and a multilayer wiring design method using such a material.

Background art

[0002] In recent years, in order to increase the speed of semiconductor devices such as LSI (Large Scale Integration), lowering the dielectric constant (Low-k) of the interlayer insulating film constituting the multilayer wiring has been actively promoted. . Generally, a low dielectric constant film is formed by reducing the density of the material or eliminating the polarity in the material. However, the film formed in this way has a low physical property such as Young's modulus and a low mechanical strength.

[0003] Conventionally, a CMP (Chemical Mechanical Polishing) process has been widely used for the formation of a wiring layer. In order to ensure flatness, the wiring layer includes wiring that functions electrically as a circuit, A dummy wiring that does not function as a circuit is formed. The dummy wiring plays a role of ensuring the mechanical strength of the interlayer insulating film only for ensuring the flatness as well as decreasing the mechanical strength accompanying the low-k of the interlayer insulating film. It has become to

[0004] Furthermore, when the low-k material is used for the via layer between the upper and lower wiring layers as well as the wiring layer, the mechanical strength of the via layer also becomes a problem. The mechanical strength in the vertical direction) may be reduced, and the reliability of the wiring may be impaired. Therefore, like the wiring layer, the via layer is provided with a dummy via that does not function as a circuit.

[0005] Normally, when providing dummy wirings and dummy vias in multilayer wiring, the dummy wiring positions are aligned in the vertical direction for the purpose of reinforcing the mechanical strength in the vertical direction and due to process limitations. Dummy vias are inserted between the wirings (see, for example, Patent Documents 1 and 2).

) o

Patent Document 1: JP 2006-190839 Patent Document 2: Japanese Unexamined Patent Publication No. 2006-41244

Disclosure of the invention

Problems to be solved by the invention

[0006] As described above, in multilayer wiring using a low-k material for the interlayer insulating film, dummy wiring and dummy vias (dummy patterns) are mainly used to increase the mechanical strength and improve reliability. Has come to be provided. However, in order to arrange such a dummy pattern linearly in the vertical direction as in the prior art, it is necessary to have a region where wiring that functions as a circuit is laid out over a plurality of layers.

[0007] Such a dummy pattern arrangement region is relatively easy to secure in a peripheral region of a region (circuit layout region) where circuit wiring is arranged. However, even if the vertical mechanical strength in the peripheral region is ensured in this way, it is still difficult to secure a sufficient vertical mechanical strength in the circuit layout region.

On the other hand, when a dummy pattern is linearly arranged in the vertical direction in the circuit layout area, a process such as laying out circuit wiring so as to bypass the dummy pattern arranged in such a manner becomes necessary. . If such a method is used, problems such as an increase in chip area and an increase in chip cost may occur.

[0009] The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device having high mechanical strength and high reliability, V, and multilayer wiring, and a method for manufacturing the same. It is another object of the present invention to provide a multilayer wiring design method having high mechanical strength and high reliability.

Means for solving the problem

In the present invention, in order to solve the above problems, in a semiconductor device having a multilayer wiring, the multilayer wiring has at least three wiring layers in which a wiring constituting a circuit is formed in an insulating film. And a central position of a dummy via connecting the dummy wiring formed in the nth wiring layer and the dummy wiring formed in the n + 1 wiring layer in the multilayer wiring, and formed in the n + 1 wiring layer. There is provided a semiconductor device characterized by having a portion in which the center position of a dummy via that connects the dummy wiring and the dummy wiring formed in the (n + 2) th wiring layer is different. According to such a semiconductor device, the center position of the dummy via that connects the dummy wirings of the nth wiring layer and the (n + 1) th wiring layer, the (n + 1) th wiring layer, and the (n + 2) th wiring in the multilayer wiring. The center position of the dummy via that connects the dummy wirings in the wiring layer is different from the center position of the dummy layer.o This structure connects the dummy wiring in the nth wiring layer and the dummy wiring in the n + 1 wiring layer with a dummy via. And a structure in which a dummy wiring different from that of the n + 1 wiring layer and a dummy wiring of the n + 1 wiring layer are connected by dummy vias are continuously provided over a larger number of layers. Since the dummy wiring and the dummy via are formed, the mechanical strength of the multilayer wiring is improved.

[0012] In the present invention, in the method for manufacturing a semiconductor device having a multilayer wiring, vias connecting the wiring and the upper and lower wirings are arranged for each of the wiring layers and via layers of the multilayer wiring. A step of disposing a dummy wiring and a dummy via connecting the upper and lower layers of the dummy wiring at a position excluding the wiring and the via of each layer, and the nth wiring layer of the dummy wiring and the dummy via. The center position of the dummy via disposed between the dummy wiring disposed and the one dummy wiring disposed in the (n + 1) th wiring layer, and the other dummy wirings disposed in the (n + 1) th wiring layer and the (n + 2) th The dummy vias arranged in the wiring layer are different from the center position of the dummy vias, and the one dummy wiring is in contact with the dummy wiring arranged in the n + 2 wiring layer. When the dummy via used for the above-mentioned dummy wiring is not disposed and the dummy via used for connection to the dummy wiring disposed in the nth wiring layer is not disposed in the other dummy wiring, the one dummy wiring and the dummy wiring Connecting the other dummy wirings to place a new dummy wiring; and, based on the placement of the wirings, vias, dummy wirings, new dummy wirings and dummy vias of each layer, the multilayer And a step of forming a wiring. A method of manufacturing a semiconductor device is provided.

According to such a method of manufacturing a semiconductor device, after the wiring and vias are arranged, the dummy wirings and the dummy vias are arranged, and the dummy wirings of the nth wiring layer and one dummy wiring of the n + 1 wiring layer are arranged. If there is a certain positional relationship between the dummy via to be connected and the dummy via to connect the dummy wiring of the n + 2 wiring layer to another dummy wiring of the n + 1 wiring layer, the n + 1 wiring layer A new dummy wiring is placed by linking one dummy wiring with another dummy wiring. The Based on these arrangements, multilayer wiring is formed. As a result, continuous dummy wirings and dummy vias extending over the plurality of layers are formed in the multilayer wiring, so that a semiconductor device having a multilayer wiring having high mechanical strength can be obtained.

[0014] Further, in the present invention, according to the multilayer wiring design method, for each layer to be a wiring layer and a via layer, a step of arranging a via for connecting the wiring and the upper and lower wirings; A dummy wiring and a dummy via for connecting the dummy wirings in the upper and lower layers are disposed at positions excluding the wiring and the via in each layer, and the dummy wiring and the dummy via are disposed in the nth wiring layer. The center position of the dummy via arranged between the dummy wiring and one dummy wiring arranged in the n + 1 wiring layer, and the other dummy wiring and n + 2 wiring layer arranged in the n + 1 wiring layer. A dummy wiring disposed between the dummy wiring and the dummy wiring disposed in the n + 2 wiring layer is connected to the dummy wiring. Dummy vias used for In addition, in the case where the dummy via used for connection with the dummy wiring arranged in the nth wiring layer is not arranged in the other dummy wiring, the one dummy wiring and the other dummy wiring are connected. There is provided a method for designing a multilayer wiring, characterized by comprising a step of connecting and arranging a new dummy wiring.

[0015] According to such a multilayer wiring design method, since the continuous dummy wiring and dummy vias extending over the plurality of layers are formed in the multilayer wiring, a multilayer wiring having high mechanical strength can be obtained. become.

The invention's effect

In the present invention, the semiconductor device includes a central position of a dummy via connecting the dummy wirings of the nth wiring layer and the n + 1th wiring layer in a multilayer wiring having at least three wiring layers, and the nth wiring layer. The configuration is such that the center position of the dummy via connecting the dummy wirings of the +1 wiring layer and the (n + 2) th wiring layer is different. As a result, the mechanical strength of the multilayer wiring can be improved, and a highly reliable multilayer wiring and a semiconductor device provided with such a multilayer wiring can be realized.

[0017] The above and other objects, features, and advantages of the present invention are preferred as examples of the present invention, and will become apparent from the following description in conjunction with the accompanying drawings showing embodiments. Brief Description of Drawings

FIG. 1 is a schematic cross-sectional view of a relevant part of a semiconductor device.

FIG. 2 is a schematic diagram of a semiconductor device layout.

FIG. 3 is an explanatory diagram of an arrangement process of circuit wiring and circuit vias.

FIG. 4 is an explanatory diagram of a dummy wiring arrangement process.

FIG. 5 is an explanatory diagram of a dummy via placement process.

FIG. 6 is an explanatory diagram of a dummy wiring connecting step.

FIG. 7 is a cross-sectional schematic diagram for major components showing a first-layer insulating film forming step.

FIG. 8 is a schematic cross-sectional view of a relevant part in a first layer recess forming step.

FIG. 9 is a schematic cross-sectional view of an essential part of a step of forming a noble metal layer and a metal seed layer.

FIG. 10 is a schematic sectional view showing an important part of a plating layer forming step.

FIG. 11 is a schematic sectional view showing an important part of a CMP process.

FIG. 12 is a schematic cross-sectional view of an essential part of a second layer insulating film forming step.

FIG. 13 is a schematic cross-sectional view of an essential part of a second layer recess forming step.

FIG. 14 is a schematic cross-sectional view of an essential part in a recess embedding process.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram of a semiconductor device layout.

The semiconductor device 1 includes a circuit layout region 2 including transistors and a peripheral region 3 thereof. The circuit layout area 2 is an area where, in addition to the transistors, circuit wirings and vias that are electrically connected to the transistors and constitute a circuit are arranged. The peripheral region 3 is a region where such circuit wiring and vias are not arranged. Usually, as shown in FIG. 2, the semiconductor device 1 has a plurality of circuit layout regions 2 divided into blocks for each predetermined processing function.

A semiconductor device 1 shown in FIG. 1 includes a transistor layer 10 in which a plurality of transistors formed in a circuit layout region 2 and plugs connected to these transistors are formed, and a multilayer wiring 40 stacked thereon. Has been. Here, the transistor layer 10 has n-channel and p-channel MOS transistors (nMOS, pMOS) 12 formed using a semiconductor substrate 11 such as a silicon (Si) substrate. . The MOS transistors 12 are electrically isolated from each other in the transistor layer 10 by an element isolation region 13 formed by, for example, an STI (Shallow Trench Isolation) method. Each MOS transistor 12 is formed on a well 12 a of a predetermined conductivity type separated by an element isolation region 13.

Each MOS transistor 12 has a gate insulating material such as silicon oxide (SiO 2) on a semiconductor substrate 11.

2

A gate electrode 12c using polysilicon or the like formed through the film 12b is provided. A side wall 12d such as SiO is formed on the side wall of the gate electrode 12c. Gate power

2

Impurity diffusion regions 12e including source / drain / extension regions and source / drain regions are formed in the semiconductor substrate 11 on both sides of the pole 12c. Silicide layers 12f are formed on the surface layers of the gate electrode 12c and the impurity diffusion region 12e to reduce the resistance.

An insulating film 14 such as silicon nitride (SiN) is formed on such a transistor structure, and an insulating film 15 such as SiO is further formed thereon. And in this transistor layer 10

2

A plug 16 using tungsten (W) or the like is formed through the two insulating films 14 and 15 to reach the silicide layer 12f.

As the multilayer wiring 40 stacked on the transistor layer 10, here, a multilayer wiring having a four-layer stacked structure including a first layer 50, a second layer 60, a third layer 70, and a fourth layer 80 is used. Illustrated.

The first layer 50 includes an interlayer insulating film having a three-layer structure including a cap layer 51, a low relative dielectric constant layer 52, and an etching stop layer 53. For example, the cap layer 51 is silicon carbide (SiC), the low dielectric constant layer 52 is carbon-containing silicon oxide (SiOC), and the etching stop layer 53 is SiO.

Each is composed of two. In such an interlayer insulating film, a wiring 55 for a circuit having a damascene structure and a dummy wiring 56 are formed via a barrier metal layer 54.

The wiring 55 is formed on the plug 16 of the transistor layer 10. Some of the dummy wirings 56 are arranged at positions other than the formation area of the wiring 55 in the circuit layout area 2 and the remaining wirings are left. The dummy wiring 56 is formed in the peripheral region 3.

The first layer 50 having such a configuration serves as the first wiring layer in the multilayer wiring 40.

Similar to the first layer 50, the second layer 60 includes, for example, a cap layer 61 made of SiC, a low dielectric constant layer 62 made of SiOC, and an etching stop layer 63 made of SiO.

2

It has an interlayer insulating film with a three-layer structure. In this interlayer insulating film, circuit vias 65 and wirings 66, dummy vias 67 and dummy wirings 68 are formed via a barrier metal layer 64.

A part of the wiring 66 is configured by a via 65 and a dual damascene structure, and the via 65 is connected to the wiring 55 of the first layer 50. Similarly, some of the dummy wirings 68 have a dummy via 67 and a dual damascene structure, and the dummy via 67 is connected to the dummy wiring 56 of the first layer 50.

In the second layer 60 having such a configuration, the layer in which the via 65 and the dummy via 67 are formed is the first via layer of the multilayer wiring 40, and the layer in which the wiring 66 and the dummy wiring 68 are formed is This is the second wiring layer of the multilayer wiring 40.

[0030] Similarly, the third layer 70 has a three-layer structure, for example, a cap layer 71 made of SiC, a low dielectric constant layer 72 made of SiOC, and an etching stop layer 73 made of SiO.

2

It has an inter-layer insulating film. In the interlayer insulating film, circuit vias 75 and wirings 76, dummy vias 77 and dummy wirings 78 are formed via a noria metal layer 74.

A part of the wiring 76 is configured with a via 75 and a dual damascene structure, and the via 75 is connected to the wiring 66 of the second layer 60. Similarly, some of the dummy wirings 78 are configured with dummy vias 77 and a dual damascene structure, and the dummy vias 77 are connected to the dummy wirings 68 of the second layer 60.

[0032] In the third layer 70 having such a configuration, the layer in which the via 75 and the dummy via 77 are formed is the second via layer of the multilayer wiring 40, and the layer in which the wiring 76 and the dummy wiring 78 are formed is This is the third wiring layer of the multilayer wiring 40.

Similarly, the fourth layer 80 has a three-layer structure, for example, a cap layer 81 made of SiC, a low dielectric constant layer 82 made of SiOC, and an etching stop layer 83 made of SiO. It has an inter-layer insulating film. In the interlayer insulating film, circuit vias 85 and wirings 86, dummy vias 87 and dummy wirings 88 are formed via a noria metal layer 84.

A part of the wiring 86 has a via 85 and a dual damascene structure, and the via 85 is connected to the wiring 76 of the third layer 70. Similarly, some of the dummy wirings 88 have a dummy via 87 and a dual damascene structure, and the dummy vias 87 are connected to the dummy wiring 78 of the third layer 70.

In the fourth layer 80 having such a configuration, the layer in which the via 85 and the dummy via 87 are formed is the third via layer of the multilayer wiring 40, and the layer in which the wiring 86 and the dummy wiring 88 are formed is This is the fourth wiring layer of the multilayer wiring 40.

Note that the dummy wirings 56, 68, 78, 88 and the vias 67, 77, 87 described above are circuit wiring 55 so that the required characteristics and size that the semiconductor device 1 should have are realized. , 66, 76, 86 and vias 65, 75, 85 are determined, and the areas other than the arrangement areas are arranged according to a certain rule.

In the semiconductor device 1 having the above-described configuration, it should be noted that continuous dummy pattern structures 100 and 110 that are linearly connected to all the layers of the multilayer wiring 40 are formed in the peripheral region 3. Also in the circuit layout region 2, dummy pattern structures 120, 130, and 140 that are continuous over all layers or a plurality of layers of the multilayer wiring 40 are formed. Note that the dummy pattern structure 140 is connected to a dummy via (not shown) connected to the dummy wiring 68 in the second layer 60 and a dummy wiring (not shown) in the first layer 50 connected to the dummy wiring 68 to the multilayer wiring 40. A continuous structure over all layers is realized!

Here, the dummy pattern structures 100, 110, 120, 130, and 140 formed in the circuit layout region 2 and the peripheral region 3 are compared.

First, in the dummy pattern structures 100 and 110 in the peripheral region 3, the sizes and positions of the dummy wirings 56, 68, 78, and 88 of the first to fourth wiring layers are the same and formed between them. The dummy vias 67, 77, 87 of the first to third via layers have the same center position.

[0039] In the peripheral area 3, the self-wires for the circuit 55, 66, 76, 86 and via 65, 75, 85 force S are not formed, and there is no restriction on the placement of the dummy pattern (dummy wiring and dummy via) Because, easy Such a linearly continuous dummy pattern structure 100, 110 can be disposed in

On the other hand, of the dummy pattern structures 120, 130, 140 in the circuit layout region 2, in the dummy pattern structures 120, 140, the size of the dummy wiring 78 in the third wiring layer is other dummy wirings 5, 6, 68, 88. In the dummy pattern structure 130, the dummy wiring 56 in the first wiring layer is larger in size than the other dummy wirings 68, 78, and 88.

[0041] Further, in any of the dummy pattern structures 120, 130, and 140 in the circuit layout region 2, the second via layer (third layer) between the second wiring layer and the third wiring layer in the multilayer wiring 40 is used. The center position of the dummy via 77 formed in 70) is different from the center position of the dummy via 87 formed in the third via layer (fourth layer 80) between the third wiring layer and the fourth wiring layer.

[0042] The dummy pattern structures 120, 130, and 140 in the circuit layout region 2 are formed in such an arrangement, because the arrangement of the dummy patterns (dummy wiring and dummy via) has the required characteristics of the semiconductor device 1. This is because of restrictions on wiring 55, 66, 76, 86 and vias 65, 75, 85 for circuits arranged in consideration of size. In other words, the dummy pattern structures 120, 130, and 140 in the circuit layout region 2 are formed by the wiring lines in the circuit layout region 2 and the self-layers 55, 66, 76, It can be said that a structure that is continuous in the vertical direction (stacking direction) is realized by winding 86 Nha, A, 65, 75, 85.

As described above, the dummy pattern structures 100 and 110 that are continuous in the vertical direction are formed in the peripheral region 3, and the dummy pattern structures 120, 130, and 140 that are also continuous in the vertical direction are formed in the circuit layout region 2. This makes it possible to increase the mechanical strength in the vertical direction of the circuit layout region 2 in addition to the peripheral region 3 even when a low relative dielectric constant film is used as part or all of the interlayer insulating film. .

Further, the dummy pattern structures 120, 130, 140 in the circuit layout region 2 are arranged so as to bypass the circuit wiring 55, 66, 76, 86 and the vias 65, 75, 85. Therefore, in order to realize dummy pattern structure 120, 1 30, 140 that is vertically continuous in circuit layout region 2 of multilayer wiring 40, layout of wiring 55, 66, 76, 86 and via 65, 75, 85 is provided. No need to change.

[0045] Accordingly, sufficient mechanical strength is achieved while suppressing an increase in chip area and a decrease in performance. The multilayer wiring 40 can be formed, and a small, high-performance and highly reliable semiconductor device 1 can be realized.

[0046] For the low relative dielectric constant layers 52, 62, 72, 82, in addition to SiOC, a material having a relative dielectric constant of 3.2 or less can be used. When a multilayer wiring is formed by simply using a material having such a relative dielectric constant for an interlayer insulating film, the mechanical strength in the vertical direction tends to be lowered. For this reason, by forming the dummy wiring structure 100, 110, 120, 130, 140 as described above to constitute the multilayer wiring 40, the multilayer wiring 40 can be reduced in the vertical direction while achieving low-k. Mechanical strength can be improved. As a result, a high-performance and highly reliable semiconductor device 1 can be realized.

Next, a method for forming the semiconductor device 1 having the above configuration will be described. In addition

Here, the formation process of the multilayer wiring 40 will be described, and the description of the formation process of the transistor layer 10 will be omitted.

[0048] The formation process of the multilayer wiring 40 of the semiconductor device 1 is roughly divided into a step of designing a layout of the multilayer wiring 40 and a step of actually forming the layout-designed multilayer wiring 40.

A method for designing the layout of the multilayer wiring 40 will be specifically described with reference to FIGS. In FIGS. 3 to 6, for convenience, the layout of the multilayer wiring 40 is shown in a cross-sectional view corresponding to FIG. 1. However, the actual layout work is performed by a plan view of the multilayer wiring as viewed from above.

[0050] First, circuit wiring 55, 66, 76, 86 and circuit vias 65, 75, 85 constituting the multilayer wiring 40 are arranged based on the functionally designed circuit data.

FIG. 3 is an explanatory diagram of the circuit wiring and circuit via placement process.

As shown in FIG. 3, in the first layer 50, the wiring 55 is arranged at a predetermined position in the circuit layout region 2. In the second layer 60, vias 65 and wirings 66 are arranged at predetermined positions in the circuit layout region 2, respectively. In the third layer 70, vias 75 and wirings 76 are arranged at predetermined positions in the circuit layout region 2, respectively. In the fourth layer 80, vias 85 and wirings 86 are arranged at predetermined positions in the circuit layout region 2, respectively.

[0052] The wiring 55, 66, 76, 86 for these circuits and the arrangement of the vias 65, 75, 85 are A so-called automatic wiring tool using a data can be used. Based on the input circuit data, a program describing the content of the self-placement of the circuit lines 55, 66, 76, 86 and vias 65, 75, 85 is executed on the computer. As a result, the wiring 55, 66, 76, 86 and the vias 65, 75, 85 are generated and arranged.

Subsequently, a dummy pattern is arranged in a region where the wirings 55, 66, 76, 86 and vias 65, 75, 85 on the layout thus obtained are not arranged.

FIG. 4 is an explanatory diagram of the dummy wiring arrangement process.

In the first layer 50, as shown in FIG. 4, dummy wirings 56, 56a, and 56b are arranged at predetermined positions in the circuit layout region 2 and the peripheral region 3. Similarly, dummy wirings 68 are arranged at predetermined positions in the circuit layout region 2 and the peripheral region 3 of the second layer 60, and dummy wirings are arranged at predetermined positions in the circuit layout region 2 and the peripheral region 3 of the third layer 70. Self lines 78 a, 78 b, 78 c, 78 d, 78 are placed and dummy wirings 88 are arranged at predetermined positions in the circuit layout region 2 and the peripheral region 3 of the fourth layer 80. All the dummy wirings arranged at this stage are arranged in the same shape and the same size.

[0055] Next, in the adjacent wiring layers, that is, the n-th wiring layer and the (n + 1) -th wiring layer (here, n = 1, 2, 3), the arrangement regions of the dummy wirings in the upper and lower layers are overlapped in the vertical direction, In addition, dummy vias 67, 77, 87 are arranged at positions where vias can be arranged in the design rule.

FIG. 5 is an explanatory diagram of the dummy via placement process.

In the first layer 50 and the second layer 60, dummy vias 67 are arranged between the dummy wirings 56 and 68 and between the dummy wirings 56b and 68. In the second layer 60 and the third layer 70, dummy vias 77 are arranged between the dummy wirings 68 and 78b, between the dummy wirings 68 and 78c, and between the dummy wirings 68 and 78. In the third layer 70 and the fourth layer 80, dummy vias 87 are arranged between the dummy wirings 78a and 88, between the dummy wirings 78d and 88, and between the dummy wirings 78 and 88.

[0057] It should be noted that dummy wirings 56, 56a, 56b, 68, 78a, 78b, 78c, 78d, 88 and dummy ridges 67, 77, 87 as shown in FIG. 4 and FIG. Until then, you can use a dummy pattern generation tool that uses a computer. Dummy wiring 56, 56a, 56b, 68, 78a, 78b, 78c, 78d, 88 and dummy via considering the placement area of the wiring 55, 66, 76, 86 and via 65, 75, 85 for the circuit placed earlier When a program describing the processing contents for generating and placing 67, 77, 87 dynamically is executed on the computer, The dummy wirings 56, 56a, 56b, 68, 78, 78a, 78b, 78c, 78d, 88 and the vias 6, 7, 77, 87 are generated and arranged.

[0058] As shown in FIGS. 4 and 5, dummy patterns, that is, dummy wirings 56, 56a, 56b, 68, 78, 78a, 78b, 78c, 78d, 88 and dummy vias 67, 77, 87 are arranged. In the road layout region 2, unlike the peripheral region 3, there is a portion where a dummy pattern structure that is continuous only between two adjacent wiring layers is formed.

[0059] In other words, due to the presence of the wiring 66 in the second wiring layer arranged earlier, the design rule is not formed below the dummy wirings 78a and 78d in the third wiring layer or above the dummy wiring 56a in the first wiring layer. Above, the dummy pattern is not arranged. Similarly, due to the presence of the wiring 86 in the fourth wiring layer arranged earlier, no dummy pattern is arranged above the third wiring layer dummy wirings 78b and 78c in accordance with the design rule. In addition, due to the presence of the wiring 55 of the first wiring layer arranged earlier, the dummy wiring 68 of the second wiring layer connected to the dummy wiring 78b has no dummy pattern disposed below it. It can happen.

[0060] Therefore, by connecting each dummy wiring 56a, 78a, 78b, 78c, 78d where the continuous structure of the dummy pattern is interrupted to another predetermined dummy wiring in the same wiring layer, more layers can be obtained. A continuous dummy pattern structure is formed.

FIG. 6 is an explanatory diagram of a dummy wiring connecting step.

For example, in a portion where the continuous structure of the dummy pattern shown in FIG. 5 is interrupted, dummy wirings 78c and 78d in the same third wiring layer are connected to each other, and a new dummy wiring 78 is added as shown in FIG. Deploy. As a result, a layout of the dummy pattern structure 120 that bypasses the wirings 66 and 86 can be obtained.

Similarly, the dummy wiring structure 56a in which the continuous structure of the dummy pattern shown in FIG. 5 is interrupted is in the same first wiring layer, and the dummy pattern structure that is continuous over the entire vertical layer has already been realized. A new dummy wiring 56 is arranged as shown in FIG. 6 in connection with the dummy wiring 56b. As a result, a layout of the dummy pattern structure 130 that bypasses the wiring 66 can be obtained.

[0063] Further, in the portion where the continuous structure of the dummy pattern shown in FIG. 5 is interrupted, the dummy wirings 78a and 78b in the same third wiring layer are connected to each other, and as shown in FIG. wiring Place 78. As a result, a layout of the dummy pattern structure 140 that bypasses the wirings 66 and 86 can be obtained.

[0064] Such a dummy pattern layout is performed by the following process using a computer, for example.

That is, if a dummy pattern is automatically placed using a dummy pattern generation tool as shown in FIGS. 4 and 5 for a layout designed using an automatic wiring tool as shown in FIG. As a result, the dummy selfish lines 56a, 78a, 78b, 78c, and 78d forces of the portion where the continuous structure of the dummy pattern is interrupted are extracted by the S computer.

[0065] The computer connects the dummy wirings 56a, 78a, 78b, 78c, 78d in the same layer and adjacent dummy wirings 78c, 78d and the dummy wirings 78a, 78b. Replace each with one dummy wiring 78 and rearrange them. Also, the computer converts the dummy wirings 56a, 78a, 78b, 78c, 78d out of the extracted dummy wirings 56a, 78a, 78b, 78c, 78d to the dummy wiring 56a that is adjacent to the dummy wiring 56a. Connect to the dummy wiring 56b that forms a continuous dummy pattern structure across the layers, replace them with one dummy wiring 56, and rearrange them.

By performing such processing, a layout as shown in FIG. 6 can be obtained.

A so-called dummy pattern generation tool using a computer can be used for the arrangement of the dummy wirings 56, 68, 78, and 88 and the dummy vias 67, 77, and 87 as shown in FIG. The dummy dummy lines 56a, 78a, 78b are extracted by executing on the computer a program that describes the processing contents for extracting predetermined dummy wirings 56a, 78a, 78b, 78c, 78d and performing predetermined connections to them. , 78c, 78d.

As described above, after designing the layout of the circuit layout region 2 and the peripheral region 3 of the multilayer wiring 40 as shown in FIG. 3 to FIG. 6, the first layer is based on the designed layout. 50 (first wiring layer), second layer 60 (first via layer and second wiring layer), third layer 70 (second via layer and third wiring layer), fourth layer 80 (third via layer and Create a mask to form the fourth wiring layer. Then, the multilayer wiring 40 is formed using the formed mask.

Subsequently, referring to FIGS. 7 to 14, formation of multilayer wiring 40 using the designed layout The method will be specifically described.

FIG. 7 is a schematic sectional view showing an important part of the first-layer insulating film forming step.

First, as shown in FIG. 7, in order to form the first layer 50, for example, SiC is deposited to form the cap layer 51, and SiOC is deposited on the cap layer 51. The low dielectric constant layer 52 is formed, and SiO is deposited on the low dielectric constant layer 52 to form an etching stop layer 53.

2

FIG. 8 is a schematic cross-sectional view of the relevant part in the first layer recess formation step.

Next, as shown in FIG. 8, a recess 150 for the wiring 55 and the dummy wiring 56 formed in the first layer 50 is formed by lithography and etching.

FIG. 9 is a schematic cross-sectional view of the relevant part in the process of forming the noria metal layer and the metal seed layer.

Next, as shown in FIG. 9, a barrier metal layer 54 is formed on the entire surface, and a Cu metal seed layer (not shown) is further formed thereon.

FIG. 10 is a schematic cross-sectional view of the relevant part in the plating layer forming step.

Next, as shown in FIG. 10, a Cu plating layer 151 is formed on the Cu plating seed layer by a plating method. Thus, the recesses 150 for the wiring 55 and the dummy wiring 56 shown in FIGS. 8 and 9 are filled with the Cu plating layer 151.

Next, as shown in FIG. 11, planarization processing is performed by CMP, and unnecessary wiring materials, that is, the barrier metal layer 54, the Cu plating seed layer, and the Cu plating layer 151 are polished to the etching stop layer 53. Remove. As a result, the wiring 55 and the dummy wiring 56 of the first layer 50 are simultaneously formed in the recess 150 shown in FIGS. In this CMP process, since the dummy wiring 56 is formed, the first layer 50 is formed with good flatness. Then, the second layer 60 is formed on the first layer 50 thus formed.

FIG. 12 is a schematic cross-sectional view of the relevant part in the second-layer insulating film forming step.

Similar to the first layer 50, as shown in FIG. 12, for example, a cap layer 61 is formed by depositing SiC, and a low relative dielectric constant layer 62 is formed by depositing SiOC on the cap layer 61. An etching stop layer 63 is formed by depositing SiO on the low dielectric constant layer 62.

2

FIG. 13 is a schematic cross-sectional view of the relevant part in the second layer recess forming step.

Next, as shown in FIG. 13, for via 65 and dummy via 67 formed in second layer 60. A concave portion 152 is formed by lithography and etching. Further, a recess 153 for the wiring 66 and the dummy wiring 68 formed in the second layer 60 is formed by lithography and etching. At this time, some of the recesses 152 and 153 are formed in a dual damascene structure. Thereafter, a noria metal layer 64 is formed on the entire surface, and a Cu plating seed layer (not shown) is further formed thereon.

FIG. 14 is a schematic cross-sectional view of the relevant part in the recess embedding process.

Next, a Cu plating layer is formed and polished by the CMP method, thereby forming the via 65, the wiring 66, the dummy via 67, and the dummy wiring 68 of the second layer 60.

[0077] After the second layer 60 is formed in this manner, the third layer 70 and the fourth layer 80 are formed in the same procedure as the second layer 60, whereby the above-described FIG. A multilayer wiring 40 having the configuration as shown in FIG. 6 is formed.

[0078] When the multilayer wiring obtained in this way is compared with the multilayer wiring in which only the dummy wiring is formed as a dummy pattern, in the multilayer wiring in which only the dummy wiring is formed, the ung ratio of the low dielectric constant layer is low. Due to the level of lOGPa, there was no dummy via under the dummy wiring! This resulted in a decrease in reliability due to low vertical mechanical strength.

[0079] On the other hand, when the dummy wiring and the dummy via are formed as the dummy pattern as described above, the upper and lower dummy wirings are connected by Cu having higher mechanical strength than the low relative dielectric constant layer. . Therefore, by providing such a structure in the multilayer wiring in the circuit layout region and the peripheral region of the semiconductor device, it is possible to increase the vertical mechanical strength of the multilayer wiring.

[0080] At this time, since circuit wiring and vias are not arranged in the peripheral region, it is possible to arrange a continuous structure of dummy wirings and dummy vias over all layers of the multilayer wiring, and V is sufficient for the peripheral region. Mechanical strength can be ensured.

[0081] Furthermore, in a circuit layout region where many circuit wirings and vias are arranged, dummy vias are arranged according to normal design rules, and the continuous structure of dummy wirings and dummy vias is interrupted by normal design rules. For this part, the dummy wiring of such part is connected to other dummy wirings as one dummy wiring. As a result, the number of layers formed across such a continuous structure increases, so that the circuit layout region is also filled. It is possible to ensure a sufficient mechanical strength.

Note that the increase in Cu occupancy due to the addition of dummy vias compared to multilayer wiring formed only with dummy interconnects, and further the increase in Cu occupancy due to the connection of predetermined dummy interconnects The effect on the parasitic capacitance is almost negligible and there is almost no effect on the circuit characteristics.

Therefore, by using the configuration and the forming method as described above, a multilayer wiring having a sufficient mechanical strength can be formed, and thereby a high-performance and highly reliable semiconductor device can be obtained. It can be realized.

In the above description, the interlayer insulation forming the force dual damascene structure exemplifying the case of forming the dual damascene structure of the via and the wiring in the three-layer structure of the cap layer, the low dielectric constant layer, and the etching stop layer. The film structure is not limited to this! For example, instead of the low relative dielectric constant layer, different insulating films may be used for the via layer and the wiring layer. In that case, if one or both of the via layer and the wiring layer are made of a material with low mechanical strength, the effect of arranging the dummy via as described above, and a continuous dummy pattern structure in the circuit layout region are formed. The effect by this can be obtained. The same effect can also be obtained when another insulating film such as an etching stop layer is formed between the via layer and the wiring layer. In that case, a material having a relative dielectric constant exceeding 3.2 may be formed in another insulating film provided between the via layer and the wiring layer.

In addition, the configuration of the multilayer wiring 40 and the configuration of the transistor layer 10 below the multilayer wiring 40 in the above description are not limited to the above example, and the configuration is not limited to the type of semiconductor device 1 or its requirements. It can be arbitrarily changed according to characteristics and the like.

In addition, when a dummy pattern structure that is continuous over all layers of the multilayer wiring is formed in the circuit layout region, the mechanical strength in the vertical direction can be maximized. However, even if it is not continuous across all layers, when the above-described connection process is performed to form a dummy pattern structure, a certain mechanical strength improvement effect is obtained compared to the case where the connection process is not performed. Can be obtained.

[0087] The above merely illustrates the principle of the present invention. In addition, there are many variations and changes All corresponding variations and equivalents, which are possible to those skilled in the art and the present invention is not limited to the exact configuration and application shown and described above, are defined by the appended claims and their equivalents. It is considered the scope of the present invention.

Explanation of symbols

1 Semiconductor devices

2 Circuit layout area

3 Peripheral area

10 Transistor layer

11 Semiconductor substrate

12 MOS transistor

12a uel

12b Gate insulation film

12c gate electrode

12d sidewall

12e Impurity diffusion region

12f Silicide layer

13 Element isolation region

14, 15 Insulating film

16 plug

40 multilayer wiring

50 1st layer

51, 61, 71, 81 Cap layer

52, 62, 72, 82 Low dielectric constant layer

53, 63, 73, 83 Etching stop layer

54, 64, 74, 84 Barrier metal layer

55, 66, 76, 86 Wiring

56, 56a, 56b, 68, 78, 78a, 78b, 78c, 78d, 88 Dummy wiring

60 Layer 2 , 75, 85 Via

, 77, 87 Dummy via

3rd layer

4th layer

0, 110, 120, 130, 140 Dummy no turn structure, 152, 153 Recess

1 Cu plating layer

Claims

The scope of the claims

[1] In a semiconductor device having multilayer wiring,

The multilayer wiring has at least three wiring layers in which wiring constituting a circuit is formed in an insulating film,

A center position of a dummy via connecting the dummy wiring formed in the nth wiring layer and the dummy wiring formed in the n + 1th wiring layer in the multilayer wiring, and formed in the n + 1th wiring layer A semiconductor device having a portion where a center position of a dummy via connecting a dummy wiring and a dummy wiring formed in an n + 2 wiring layer is different.

[2] Constructed by dummy wirings formed in each wiring layer of the multilayer wiring and dummy vias connecting the dummy wirings formed in each wiring layer over all layers of the multilayer wiring. 2. The semiconductor device according to claim 1, wherein a continuous dummy pattern structure is formed.

[3] A dummy wiring formed in the nth wiring layer, a dummy wiring formed in the n + 1 wiring layer, a dummy wiring formed in the n + 2 wiring layer, and the nth wiring layer Connected to the dummy wiring formed in the n + 1th wiring layer, the dummy wiring formed in the n + 1th wiring layer, and the n + 1th wiring layer. A dummy pattern structure constituted by a dummy via for connecting the dummy wiring is a wiring constituting a circuit formed in the nth wiring layer or a wiring constituting a circuit formed in the n + 2 wiring layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be detoured.

4. The semiconductor device according to claim 1, wherein the portion is provided in a circuit layout region in which wirings constituting the circuit are arranged.

[5] In the peripheral area of the circuit layout area, between all the layers of the multilayer wiring, between the dummy wiring formed in each wiring layer of the multilayer wiring and the dummy wiring formed in each wiring layer 5. The semiconductor device according to claim 4, wherein a continuous dummy pattern structure composed of dummy vias that respectively connect to each other is formed.

[6] The dummy wiring formed in the nth wiring layer and the dummy wiring formed in the n + 2 wiring layer are formed in the same size, and are more than the dummy wiring formed in the n + 1 wiring layer. small 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a small size.

[7] The semiconductor device according to [1], wherein the insulating film is made of a material having a relative dielectric constant of 3.2 or less.

8. The semiconductor device according to claim 7, wherein a layer composed of a material having a relative dielectric constant of 3.2 or more is provided below the wiring layer.

[9] In a method for manufacturing a semiconductor device having a multilayer wiring,

A step of arranging vias for connecting the wirings and the upper and lower wirings for each of the wiring layers and via layers of the multilayer wiring; and

Placing dummy vias connecting the dummy wirings and upper and lower dummy wirings at positions excluding the wiring and vias of each layer; and

Of the dummy wiring and the dummy via, a center position of a dummy via disposed between the dummy wiring disposed in the nth wiring layer and one dummy wiring disposed in the n + 1 wiring layer, and the n + When the center position of the dummy vias arranged between the other dummy wirings arranged in the first wiring layer and the dummy wiring arranged in the (n + 2) th wiring layer is different. No dummy via used for connection with the dummy wiring arranged in the n + 2 wiring layer is arranged, and the other dummy wiring is used for connection with the dummy wiring arranged in the nth wiring layer. In the case where the dummy via is not arranged, a step of connecting the one dummy wiring and the other dummy wiring to arrange a new dummy wiring, the wiring of each layer, the via, the dummy wiring, The new dummy wiring and And forming the multilayer wiring based on the arrangement of the dummy via,

A method for manufacturing a semiconductor device, comprising:

[10] If there is an isolated dummy wiring in the nth wiring layer or the n + 2 wiring layer among the arranged dummy wirings, the isolated dummy wiring is the same as that. A step of arranging a new dummy wiring in connection with the dummy wiring in the wiring layer,

10. The method of manufacturing a semiconductor device according to claim 9, wherein the multilayer wiring is formed based on an arrangement of the wiring, the via, the dummy wiring, the new dummy wiring, and the dummy via in each layer. .

[11] In the step of disposing the dummy wiring and the dummy via at a position excluding the wiring and the via in each layer,

10. The manufacturing method of a semiconductor device according to claim 9, wherein the dummy wiring and the dummy via are arranged at a position excluding the wiring and the via in each layer without changing the arrangement of the wiring and the via. Method.

[12] In the step of connecting the one dummy wiring and the other dummy wiring and arranging the new dummy wiring,

By disposing the new dummy wiring, a continuous dummy pattern structure constituted by the dummy wiring including the new dummy wiring and the dummy via is formed over all layers of the multilayer wiring. A method for manufacturing a semiconductor device according to claim 9.

[13] In the step of arranging the wiring and the via!

Arranging the wiring and the via in a circuit layout region;

In the step of connecting the one dummy wiring and the other dummy wiring to place the new dummy wiring,

10. The semiconductor device according to claim 9, wherein the new dummy wiring is arranged by connecting the one dummy wiring and the other dummy wiring arranged in the circuit layout region. Production method.

[14] In the step of arranging the dummy wiring and the dummy via,

14. The continuous dummy pattern structure constituted by the dummy wiring and the dummy via is formed in the peripheral region of the circuit layout region over all layers of the multilayer wiring. Semiconductor device manufacturing method.

[15] In the step of forming the multilayer wiring,

Regarding the formation of each layer,

Forming an insulating film;

Forming a recess at a position where the wiring, the via, the dummy wiring, the new dummy wiring or the dummy via of the formed insulating film is formed;

Depositing a wiring material on the entire surface of the insulating film in which the recess is formed; Performing a planarization process on the deposited wiring material and embedding the wiring material in the recess;

10. The method for manufacturing a semiconductor device according to claim 9, further comprising:

[16] In the multilayer wiring design method,

For each layer to be a wiring layer and a via layer, a step of arranging a via for connecting the wiring and the wiring in the upper and lower layers;

Of the dummy wiring and the dummy via, a center position of a dummy via disposed between the dummy wiring disposed in the nth wiring layer and one dummy wiring disposed in the n + 1 wiring layer, and the n + When the center position of the dummy vias arranged between the other dummy wirings arranged in the first wiring layer and the dummy wiring arranged in the (n + 2) th wiring layer is different. No dummy via used for connection with the dummy wiring arranged in the n + 2 wiring layer is arranged, and the other dummy wiring is used for connection with the dummy wiring arranged in the nth wiring layer. In the case where no dummy via is arranged, a step of connecting the one dummy wiring and the other dummy wiring to arrange a new dummy wiring is provided.

[17] In the step of disposing the dummy wiring and the dummy via at a position excluding the wiring and the via of each layer,

17. The multilayer wiring design according to claim 16, wherein the dummy wiring and the dummy via are arranged at a position excluding the wiring and the via of each layer without changing the arrangement of the wiring and the via. Method.

[18] In the step of connecting the one dummy wiring and the other dummy wiring to place the new dummy wiring,

The continuous dummy pattern structure constituted by the dummy wiring including the new dummy wiring and the dummy via is formed over all layers by arranging the new dummy wiring. A method for designing multilayer wiring as set forth in Section 16 of the scope.

[19] In the step of arranging the wiring and the via!

Arranging the wiring and the via in a circuit layout region;

17. The multilayer wiring according to claim 16, wherein the new dummy wiring is arranged by connecting the one dummy wiring and the other dummy wiring arranged in the circuit layout region. Design method.

[20] In the step of arranging the dummy wiring and the dummy via,

20. The multilayer wiring structure according to claim 19, wherein a continuous dummy pattern structure constituted by the dummy wiring and the dummy via is formed in a peripheral region of the circuit layout region over all layers. Design method.