WO2008064139A1 - Software transaction commit order and conflict management - Google Patents

Software transaction commit order and conflict management Download PDF

Info

Publication number
WO2008064139A1
WO2008064139A1 PCT/US2007/085035 US2007085035W WO2008064139A1 WO 2008064139 A1 WO2008064139 A1 WO 2008064139A1 US 2007085035 W US2007085035 W US 2007085035W WO 2008064139 A1 WO2008064139 A1 WO 2008064139A1
Authority
WO
WIPO (PCT)
Prior art keywords
commit
transaction
transactions
order
determined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/085035
Other languages
English (en)
French (fr)
Inventor
Lingli Zhang
Vinod K. Grover
Michael M. Magruder
David Detlefs
John Joseph Duffy
Goetz Graefe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Corp
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Priority to JP2009537403A priority Critical patent/JP4698757B2/ja
Priority to CN2007800428099A priority patent/CN101535950B/zh
Priority to KR1020097010737A priority patent/KR101443930B1/ko
Priority to EP07845108.5A priority patent/EP2095225B1/en
Priority to BRPI0718463-8A priority patent/BRPI0718463A2/pt
Priority to CA002664041A priority patent/CA2664041A1/en
Publication of WO2008064139A1 publication Critical patent/WO2008064139A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/466Transaction processing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00Data processing: database and file management or data structures
    • Y10S707/99931Database or file accessing
    • Y10S707/99933Query processing, i.e. searching

Definitions

  • STM Software transactional memory
  • a transaction in the context of transactional memory is a piece of code that executes a series of reads and writes to shared memory.
  • STM is used as an alternative to traditional locking mechanisms.
  • Programmers put a declarative annotation (e.g. atomic) around a code block to indicate safety properties they require and the system automatically guarantees that this block executes atomically with respect to other protected code regions.
  • the software transactional memory programming model prevents lock-based priority-inversion and deadlock problems.
  • While typical STM systems have many advantages, they still require the programmer to be careful in avoiding unintended memory access orderings.
  • the order in which transactions are committed is unconstrained. Transactions race with one another to commit, meaning that whether transaction 1 commits before transaction 2 or after is often a product of the dynamic scheduling of the program (and often by program- specific logic too).
  • their committing order can be arbitrarily decided based on one of many possible contention management policies. In both of these scenarios, no particular commit order is guaranteed; therefore the burden is on the programmer to make sure that his/her program works correctly with either order. This makes parallel programming very difficult.
  • One approach to simplifying parallel programming is to automatically parallelize sequential programs, in a manner that guarantees that the semantics of the program are unchanged. In other words, if the sequential program works correctly, so does the parallelized version.
  • Two (separate) variations of this concept to parallelize sequential programs have been termed, respectively, safe futures and speculative loop parallelization.
  • the sequential version of a program might perform "A; B" (that is, do A then do B).
  • the programmer can add an annotation (a "future") indicating that he or she thinks it might be possible to perform A and B in parallel without changing the program semantics - that A does not read any memory locations that B reads, nor vice-versa.
  • a software transactional memory system is provided with a feature to allow a pre-determined commit order to be specified for a plurality of transactions.
  • the pre-determined commit order is used at runtime to aid in determining an order in which to commit the transactions in the software transactional memory system.
  • the predetermined commit order can be either total ordering or partial ordering. In the case of total ordering, the transactions are forced to commit in a linear order. In the case of partial ordering, the transactions are allowed to commit in one of multiple acceptable scenarios.
  • a commit arbitrator keeps track of the next-to-commit value representing the transaction that should be allowed to commit next, and when a particular transaction is ready to commit, it is allowed to do so if its commit order number matches the next-to-commit value of the commit arbitrator.
  • a contention management process is invoked when a conflict occurs between a first transaction and a second transaction. The pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed.
  • Figure 1 is a diagrammatic view of a computer system of one implementation.
  • Figure 2 is a diagrammatic view of a software transactional memory application of one implementation operating on the computer system of Figure 1.
  • Figure 3 is a high-level process flow diagram for one implementation of the system of Figure 1.
  • Figure 4 is a process flow diagram for one implementation of the system of
  • Figure 1 illustrating the stages involved in using a commit arbitrator to enforce a pre-determined commit order.
  • Figure 5 is a process flow diagram for one implementation of the system of Figure 1 illustrating the stages involved in using a commit arbitrator to enforce a total ordering of a plurality of transactions.
  • Figure 6 is a process flow diagram for one implementation of the system of
  • Figure 1 illustrating the stages involved in using a commit arbitrator to enforce a partial ordering of a plurality of transactions.
  • Figure 7 is a process flow for one implementation of the system of Figure 1 that illustrates the stages involved in providing a contention management process that manages conflicts using the pre-determined commit order information.
  • Figure 8 is a process flow for one implementation of the system of Figure 1 that illustrates the stages involved in providing a contention management process that manages conflicts with nested transactions using the pre-determined commit order information.
  • Figure 9 is a logical diagram illustrating an exemplary ancestor tree with top level ancestors that have a common ancestor.
  • Figure 10 is a logical diagram illustrating an exemplary ancestor tree with top level ancestors that do not have a common ancestor.
  • Figure 11 is a process flow diagram for one implementation of the system of Figure 1 that illustrates the stages involved in reducing an amount of wasted work by using a commit arbitrator in a software transactional memory system.
  • Figure 12 is a process flow diagram for one implementation of the system of Figure 1 that illustrates the stages involved in analyzing an entire ancestor chain in a contention management process to determine the proper conflict resolution.
  • a feature is provided in the software transactional memory system to allow a pre-determined commit order to be specified for a plurality of transactions.
  • the pre-determined commit order is used to aid in determining an order in which to commit the transactions.
  • a contention management process is invoked when a conflict occurs between a first transaction and a second transaction.
  • the pre-determined commit order is then used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed.
  • an exemplary computer system to use for implementing one or more parts of the system includes a computing device, such as computing device 100.
  • computing device 100 typically includes at least one processing unit 102 and memory 104.
  • memory 104 may be volatile (such as RAM), non- volatile (such as ROM, flash memory, etc.) or some combination of the two.
  • This most basic configuration is illustrated in Figure 1 by dashed line 106.
  • device 100 may also have additional features/functionality.
  • device 100 may also include additional storage (removable and/or non-removable) including, but not limited to, magnetic or optical disks or tape.
  • Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data.
  • Memory 104, removable storage 108 and nonremovable storage 110 are all examples of computer storage media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by device 100. Any such computer storage media may be part of device 100.
  • Computing device 100 includes one or more communication connections 114 that allow computing device 100 to communicate with other computers/applications 115.
  • Device 100 may also have input device(s) 112 such as keyboard, mouse, pen, voice input device, touch input device, etc.
  • Output device(s) 111 such as a display, speakers, printer, etc. may also be included. These devices are well known in the art and need not be discussed at length here.
  • computing device 100 includes software transactional memory application 200.
  • Software transactional memory application 200 will be described in further detail in Figure 2.
  • Software transactional memory application 200 is one of the application programs that reside on computing device 100. However, it will be understood that software transactional memory application 200 can alternatively or additionally be embodied as computer-executable instructions on one or more computers and/or in different variations than shown on Figure 1. Alternatively or additionally, one or more parts of software transactional memory application 200 can be part of system memory 104, on other computers and/or applications 115, or other such variations as would occur to one in the computer software art.
  • Software transactional memory application 200 includes program logic 204, which is responsible for carrying out some or all of the techniques described herein.
  • Program logic 204 includes logic for providing a software transactional memory (STM) system 206; logic for providing a commit arbitrator that allows a pre-determined commit order to be specified, statically or dynamically, for a plurality of transactions in the STM system 208; logic for allowing the commit arbitrator to use the pre-determined commit order at runtime to aid in determining an order in which to commit the plurality of transactions in the software transactional memory system 210; logic for providing a contention management process that is invoked when a conflict occurs between a first transaction and a second transaction 212; logic for using the pre-determined commit order in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed (e.g.
  • STM software transactional memory
  • program logic 204 is operable to be called programmatically from another program, such as using a single call to a procedure in program logic 204.
  • Figure 3 is a high level process flow diagram for software transactional memory application 200.
  • the process of Figure 3 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 240 with providing a software transactional memory system (stage 242).
  • a feature is provided to allow a pre-determined commit order (e.g. a total ordering or partial ordering) to be specified for a plurality of transactions (e.g. assigned dynamically or statically) (stage 244).
  • a pre-determined commit order e.g. a total ordering or partial ordering
  • a plurality of transactions e.g. assigned dynamically or statically
  • pre-determined commit order is meant to include a specific order in which a particular group of related transactions should be committed, as determined at any point in time before the transactions start running.
  • group of transactions as used herein includes a particular set of (e.g. plurality of) transactions managed by the same commit arbitrator, as well as nested children of those transactions.
  • the pre-determined commit order is used at runtime to aid in determining an order in which to commit the plurality of transactions in the software transactional memory system (stage 246).
  • the pre-determined commit order is used to aid in resolving conflicts occurring between two or more of the plurality of transactions (stage 248).
  • the process ends at end point 250.
  • Figure 4 illustrates one implementation of the stages involved in using a commit arbitrator to enforce a pre-determined commit order.
  • the process of Figure 4 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 270 with providing one or more commit arbitrators for a software transaction memory system, the commit arbitrator being operable to allow a pre-determined commit order to be specified for a plurality of transactions (stage 272).
  • commit arbitrator as used herein is meant to include any type of program, feature, or process that is responsible for managing one or more groups of transactions that should be ordered with respect to one another.
  • the commit arbitrator tracks and updates one or more ordering values that are used to determine the proper ordering of transactions with respect to one another (stage 274).
  • a next-to-commit field can be used to represent a next transaction of a plurality of transactions that should be committed next) (stage 274).
  • a directed graph of different possible orders is tracked using the ordering values.
  • the commit arbitrator uses the pre-determined commit order to provide a commit order number for each of the plurality of transactions (stage 276).
  • the commit arbitrator allows the transaction to commit (stage 278).
  • this scenario occurs when the next-to-commit field and the commit order number for the particular transaction have the same value.
  • the commit arbitrator allows the transaction to commit and then increments the next-to- commit field to a next number in a sequence (e.g. next higher number) if the commit is successful (stage 278).
  • the particular transaction of the plurality of transactions prepares to commit, if the commit order number for the particular transaction when compared to the ordering values reveals that the commit is not proper, then the particular transaction is placed in a hold mode until it is awakened at a later point in time after a predecessor transaction commits (stage 280). In the case of total ordering, this hold mode is entered when the next-to-commit field and the order number for the particular transaction do not have the same value.
  • the system may wake a transaction after its immediate predecessor has committed, in which case it may try to commit right away. Alternatively, the system may choose to wake a transaction after some non- immediate predecessor has committed, even though its immediate predecessor may not yet have committed.
  • Figure 5 illustrates one implementation of the stages involved in using a commit arbitrator to enforce a total ordering of a plurality of transactions.
  • the process of Figure 5 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 290 with providing one or more commit arbitrators operable to allow a pre-determined total ordering to be specified for a plurality of transactions (e.g. one specifying an exact order in which the plurality of transactions should be committed) (stage 292).
  • stage 296 the commit order of the particular transaction is compared with a next-to-commit field of the commit arbitrator. In one implementation, if the system determines that enforcement of the total ordering is not necessary (e.g. such as because there is definitely no conflict), then the total ordering requirement can be broken as appropriate (stage 294), then the process ends at end point 302.
  • stage 296 If commit ordering is to be enforced, and if the commit order of the particular transaction has a same value as the next-to-commit field of the commit arbitrator (decision point 296), then the particular transaction is committed, and if the commit is successful, the next-to-commit field is incremented and the next successor is awakened, if any exist (stage 298). If the commit order of the particular transaction does not have the same value as the next-to-commit field of the commit arbitrator (decision point 296), then the particular transaction is put in a hold/sleep mode until it is awakened at a later point in time after a predecessor transaction commits (stage 300).
  • Figure 6 illustrates one implementation of the stages involved in using a commit arbitrator to enforce a partial ordering of a plurality of transactions.
  • the process of Figure 6 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 310 with providing one or more commit arbitrators operable to allow a pre-determined partial ordering to be specified for a plurality of transactions (e.g. one specifying a plurality of acceptable orders in which the plurality of transactions should be committed - e.g. in the form of a directed graph) (stage 312).
  • stage 312 When a particular transaction of the plurality of transactions reaches its commit point, to enforce the commit order, the state of the predecessor transactions (e.g.
  • one or more ordering values are consulted for the particular committing transaction (e.g. as tracked by the commit arbitrator) (stage 314). If all predecessors to the particular transaction have committed (decision point 316), then the particular transaction is committed (stage 318). If the commit is successful, one or more values tracked by the commit arbitrator are updated as appropriate, and all possible next successors are awakened, if any exist (stage 318).
  • Figure 7 illustrates one implementation of the stages involved in providing a contention management process that manages conflicts using the pre-determined commit order information.
  • the process of Figure 7 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 340 with providing a software transactional memory system that supports a pre-determined commit order for one or more groups of transactions (stage 342).
  • a contention management process is provided that is invoked when a conflict occurs between a first transaction and a second transaction (stage 344).
  • the pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed (stage 346).
  • stage 350 If the first transaction and second transaction are not part of the same transaction group (decision point 348), then a pre-determined commit order is not enforced between these two transactions (because none existed) (stage 350). In such a scenario, since the two transactions are not in a same transaction group, the ordering factor is not used to help resolve the conflict (stage 350).
  • the system compares the first order number of the first transaction and the second order number of the second transaction (stage 352).
  • the transaction with the lower order number is allowed to proceed (or with another suitable priority ordering) (stage 354).
  • the process ends at end point 356.
  • Figure 8 illustrates one implementation of the stages involved in providing a contention management process that manages conflicts with nested transactions using the pre-determined commit order information.
  • the process of Figure 8 is at least partially implemented in the operating logic of computing device 100.
  • the entire ancestor chain is considered for each transaction before committing the particular transaction, so that any ordering present in that chain is enforced.
  • the procedure begins at start point 370 with providing a contention management process that is invoked when a conflict occurs between a first transaction and a second transaction (stage 372).
  • a pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed (stage 372).
  • first and second transactions are not part of the same transaction group (decision point 376)
  • a pre-determined commit order is not enforced between those two transactions (because none existed) (stage 378) and the process ends at end point 388.
  • the system checks to see if nested transactions are involved (decision point 380). [040] If nested transactions are not involved (decision point 380), then the order number (or other ordering indicator) of the first transaction is compared with the order number (or other ordering indicator) of the second transaction (stage 384). The transaction with the lower order number is allowed to proceed (or the one determined to be next in order by using other suitable ordering criteria) (stage 386).
  • top level ancestor as used herein is meant to include the immediate children of common ancestors where common ancestors are involved, and the top level ancestor of each transaction where there is no common ancestor involved. These scenarios involving common and uncommon ancestors are illustrated in further detail in Figures 9 and 10.
  • the transaction with the lower order number is allowed to proceed (e.g. the transaction related to the ancestor that had the lower order number or other suitable criteria) (stage 386).
  • Figure 9 is a logical diagram illustrating an exemplary ancestor tree with top level ancestors that have a common ancestor.
  • transaction A is a common ancestor of D and E.
  • the order number of transactions B and C are analyzed to determine which transaction D or E should be allowed to proceed (stage 382 in Figure 8).
  • Figure 10 is a logical diagram illustrating an exemplary ancestor tree with top level ancestors that do not have common ancestors.
  • transaction A is an ancestor of transaction C.
  • Transaction D is an ancestor of transaction F.
  • the order number of transactions A and D are compared to determine which transaction C or F should be allowed to proceed (stage 382 in Figure 8).
  • Figure 11 illustrates one implementation of the stages involved in reducing the amount of wasted work by using a commit arbitrator in a software transactional memory system.
  • the process of Figure 11 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 400 with providing one or more commit arbitrators for a software transactional memory system, the commit arbitrator being operable to allow a pre-determined commit order to be specified for a plurality of transactions (stage 402).
  • the commit arbitrator is operable to put a transaction into sleep/hold mode to block that transaction from re-executing when a predecessor transaction is still executing (e.g. by analyzing the pre-determined commit order to determine the proper order (stage 404).
  • the commit arbitrator is also operable to wake up transactions that were put on hold once the predecessor transaction(s) have finished (e.g. by again analyzing the pre-determined commit order to determine the proper order) (stage 406). By providing these blocking and waking mechanisms, the commit arbitrator helps reduce the amount of work that is wasted by keeping operations from being performed that would have to be undone later (stage 408). The process ends at end point 410.
  • Figure 12 illustrates one implementation of the stages involved in analyzing an entire ancestor chain in a contention management process to determine the proper conflict resolution. In one form, the process of Figure 12 is at least partially implemented in the operating logic of computing device 100.
  • the procedure begins at start point 430 with providing a contention management process that is invoked when a conflict occurs between a first transaction and a second transaction (stage 432).
  • a pre-determined commit order is used in the contention management process to aid in determining whether the first transaction or the second transaction should win the conflict and be allowed to proceed (stage 434).
  • An entire ancestor chain of a pre-determined commit order is analyzed to help determine the proper conflict management (stage 436). For example, if there are four transactions, two parents and two children, where B is nested within A and D is nested within C. Suppose there is an ordering relationship between A and C where A should commit before C. IfB and D conflict, the contention management process should favor B because favoring D is useless given that A must commit before C. (stage 436).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Advance Control (AREA)
PCT/US2007/085035 2006-11-17 2007-11-17 Software transaction commit order and conflict management Ceased WO2008064139A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009537403A JP4698757B2 (ja) 2006-11-17 2007-11-17 ソフトウェアトランザクションのコミット順序および競合の管理
CN2007800428099A CN101535950B (zh) 2006-11-17 2007-11-17 用于事务应用排序和争用管理的方法和系统
KR1020097010737A KR101443930B1 (ko) 2006-11-17 2007-11-17 Stm 시스템에서 트랜잭션들에 순서화를 적용하는 방법, 순서화에 의한 경쟁 관리를 제공하는 방법 및 컴퓨터 판독가능 매체
EP07845108.5A EP2095225B1 (en) 2006-11-17 2007-11-17 Software transaction commit order and conflict management
BRPI0718463-8A BRPI0718463A2 (pt) 2006-11-17 2007-11-17 Ordem de comprometimento de transação de software e gerenciamento de conflito
CA002664041A CA2664041A1 (en) 2006-11-17 2007-11-17 Software transaction commit order and conflict management

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/601,541 2006-11-17
US11/601,541 US7711678B2 (en) 2006-11-17 2006-11-17 Software transaction commit order and conflict management

Publications (1)

Publication Number Publication Date
WO2008064139A1 true WO2008064139A1 (en) 2008-05-29

Family

ID=39418139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/085035 Ceased WO2008064139A1 (en) 2006-11-17 2007-11-17 Software transaction commit order and conflict management

Country Status (10)

Country Link
US (1) US7711678B2 (enExample)
EP (1) EP2095225B1 (enExample)
JP (1) JP4698757B2 (enExample)
KR (1) KR101443930B1 (enExample)
CN (1) CN101535950B (enExample)
BR (1) BRPI0718463A2 (enExample)
CA (1) CA2664041A1 (enExample)
RU (1) RU2439663C2 (enExample)
TW (1) TWI424313B (enExample)
WO (1) WO2008064139A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102272744A (zh) * 2009-01-02 2011-12-07 国际商业机器公司 用于事务存储器管理中的冲突仲裁的优先化

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232367A4 (en) * 2007-12-12 2011-03-09 Univ Washington MULTITRAITEMENT DETERMINISTIC
WO2009114645A1 (en) * 2008-03-11 2009-09-17 University Of Washington Efficient deterministic multiprocessing
US8266604B2 (en) * 2009-01-26 2012-09-11 Microsoft Corporation Transactional memory compatibility management
US8627292B2 (en) * 2009-02-13 2014-01-07 Microsoft Corporation STM with global version overflow handling
US9569254B2 (en) * 2009-07-28 2017-02-14 International Business Machines Corporation Automatic checkpointing and partial rollback in software transaction memory
US9639392B2 (en) * 2013-12-17 2017-05-02 Intel Corporation Unbounded transactional memory with forward progress guarantees using a hardware global lock
US8453120B2 (en) 2010-05-11 2013-05-28 F5 Networks, Inc. Enhanced reliability using deterministic multiprocessing-based synchronized replication
US8327185B1 (en) 2012-03-23 2012-12-04 DSSD, Inc. Method and system for multi-dimensional raid
US9870384B2 (en) * 2012-03-30 2018-01-16 International Business Machines Corporation Database system transaction management
RU2679782C2 (ru) * 2012-11-13 2019-02-12 Конинклейке Филипс Н.В. Способ и устройство для управления правом транзакции
JP6021112B2 (ja) * 2013-11-28 2016-11-02 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 複数のスレッドで順序付きトランザクションを実行する方法、並びに、当該トランザクションを実行するためのコンピュータ及びそのコンピュータ・プログラム
CN103914300B (zh) * 2014-03-24 2017-04-05 深圳天珑无线科技有限公司 一种软件开发事务的实现方法及电子设备
US20150278123A1 (en) * 2014-03-28 2015-10-01 Alex Nayshtut Low-overhead detection of unauthorized memory modification using transactional memory
US10303525B2 (en) * 2014-12-24 2019-05-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
WO2016106738A1 (zh) * 2014-12-31 2016-07-07 华为技术有限公司 事务冲突检测方法、装置及计算机系统
US10540524B2 (en) 2014-12-31 2020-01-21 Mcafee, Llc Memory access protection using processor transactional memory support
CN105045563B (zh) * 2015-06-19 2017-10-10 陕西科技大学 一种推测嵌套软件事务存储的冲突管理方法
US10318430B2 (en) 2015-06-26 2019-06-11 International Business Machines Corporation System operation queue for transaction
US10180921B2 (en) 2015-06-26 2019-01-15 International Business Machines Corporation Non-interfering transactions
US9792147B2 (en) * 2015-07-02 2017-10-17 International Business Machines Corporation Transactional storage accesses supporting differing priority levels
US9792148B2 (en) 2016-01-07 2017-10-17 International Business Machines Corporation Prioritization of transactions based on execution progress
JP6645348B2 (ja) 2016-05-06 2020-02-14 富士通株式会社 情報処理装置、情報処理プログラム、及び情報処理方法
US10466930B2 (en) * 2017-04-28 2019-11-05 EMC IP Holding Company LLC Method and system for fast ordered writes with atomic multicast
US10289491B1 (en) 2017-04-28 2019-05-14 EMC IP Holding Company LLC Method and system for implementing multi-dimensional raid in an extensible storage array to optimize performance
US10339062B2 (en) 2017-04-28 2019-07-02 EMC IP Holding Company LLC Method and system for writing data to and read data from persistent storage
US10614019B2 (en) 2017-04-28 2020-04-07 EMC IP Holding Company LLC Method and system for fast ordered writes with target collaboration
GB2570466B (en) * 2018-01-25 2020-03-04 Advanced Risc Mach Ltd Commit window move element
US11182379B2 (en) * 2018-08-24 2021-11-23 Oracle International Corporation DAG based methods and systems of transaction processing in a distributed ledger
JP7645495B2 (ja) * 2020-06-12 2025-03-14 株式会社情報科学研究所 並列分散計算システム
US11822538B2 (en) 2020-11-05 2023-11-21 Oracle International Corporation Systems and methods of transaction identification generation for transaction-based environment
KR102567658B1 (ko) * 2021-04-14 2023-08-16 주식회사 카카오뱅크 멀티 트랜잭션을 이용한 업무 컴포넌트 격리 개발 방법 및 시스템

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4884228A (en) * 1986-10-14 1989-11-28 Tektronix, Inc. Flexible instrument control system
US6011921A (en) * 1996-03-19 2000-01-04 Fujitsu Limited Intermediate communication controller that sends transmission data in a predetermined order to a corresponding slave unit upon request from a master controller
US6088705A (en) * 1997-07-02 2000-07-11 International Business Machines Corporation Method and apparatus for loading data into a database in a multiprocessor environment
EP1197876A2 (en) * 2000-10-13 2002-04-17 Miosoft Corporation Persistent data storage techniques
US6557048B1 (en) * 1999-11-01 2003-04-29 Advanced Micro Devices, Inc. Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4216871C2 (de) * 1991-05-21 2001-09-06 Digital Equipment Corp Ausführungsordnen zum Sicherstellen der Serialisierbarkeit verteilter Transaktionen
US5701480A (en) * 1991-10-17 1997-12-23 Digital Equipment Corporation Distributed multi-version commitment ordering protocols for guaranteeing serializability during transaction processing
US5241675A (en) * 1992-04-09 1993-08-31 Bell Communications Research, Inc. Method for enforcing the serialization of global multidatabase transactions through committing only on consistent subtransaction serialization by the local database managers
US5335343A (en) * 1992-07-06 1994-08-02 Digital Equipment Corporation Distributed transaction processing using two-phase commit protocol with presumed-commit without log force
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
JPH1049420A (ja) * 1996-08-02 1998-02-20 Fuji Xerox Co Ltd データベース管理方法
US6456995B1 (en) 1998-12-31 2002-09-24 International Business Machines Corporation System, method and computer program products for ordering objects corresponding to database operations that are performed on a relational database upon completion of a transaction by an object-oriented transaction system
AU6784600A (en) * 1999-08-17 2001-03-13 Progress Software, Inc. Concurrent commit lock
US20040236659A1 (en) * 1999-12-01 2004-11-25 Cazalet Edward G. Method and apparatus for an engine system supporting transactions, schedules and settlements involving fungible, ephemeral commodities including electrical power
EP1323071A2 (en) * 2000-07-28 2003-07-02 Xymphonic Systems AS Method, system and data structures for implementing nested databases
US7111023B2 (en) * 2001-05-24 2006-09-19 Oracle International Corporation Synchronous change data capture in a relational database
GB0130399D0 (en) * 2001-12-19 2002-02-06 Ibm Message ordering in a messaging system
US6754737B2 (en) * 2001-12-24 2004-06-22 Hewlett-Packard Development Company, L.P. Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect
US6785779B2 (en) * 2002-01-09 2004-08-31 International Business Machines Company Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture
US8244990B2 (en) * 2002-07-16 2012-08-14 Oracle America, Inc. Obstruction-free synchronization for shared data structures
US7103612B2 (en) * 2002-08-01 2006-09-05 Oracle International Corporation Instantiation of objects for information-sharing relationships
US7076508B2 (en) * 2002-08-12 2006-07-11 International Business Machines Corporation Method, system, and program for merging log entries from multiple recovery log files
US7089253B2 (en) * 2002-09-13 2006-08-08 Netezza Corporation Computer method and system for concurrency control using dynamic serialization ordering
US6961821B2 (en) * 2002-10-16 2005-11-01 International Business Machines Corporation Reconfigurable cache controller for nonuniform memory access computer systems
US7010645B2 (en) * 2002-12-27 2006-03-07 International Business Machines Corporation System and method for sequentially staging received data to a write cache in advance of storing the received data
US6898685B2 (en) * 2003-03-25 2005-05-24 Emc Corporation Ordering data writes from a local storage device to a remote storage device
US7136967B2 (en) * 2003-12-09 2006-11-14 International Business Machinces Corporation Multi-level cache having overlapping congruence groups of associativity sets in different cache levels
US7266571B2 (en) * 2004-07-27 2007-09-04 International Business Machines Corporation Method and system for scheduling a partial ordered transactions for event correlation
US7376675B2 (en) * 2005-02-18 2008-05-20 International Business Machines Corporation Simulating multi-user activity while maintaining original linear request order for asynchronous transactional events
US7720891B2 (en) * 2006-02-14 2010-05-18 Oracle America, Inc. Synchronized objects for software transactional memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4884228A (en) * 1986-10-14 1989-11-28 Tektronix, Inc. Flexible instrument control system
US6011921A (en) * 1996-03-19 2000-01-04 Fujitsu Limited Intermediate communication controller that sends transmission data in a predetermined order to a corresponding slave unit upon request from a master controller
US6088705A (en) * 1997-07-02 2000-07-11 International Business Machines Corporation Method and apparatus for loading data into a database in a multiprocessor environment
US6557048B1 (en) * 1999-11-01 2003-04-29 Advanced Micro Devices, Inc. Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof
EP1197876A2 (en) * 2000-10-13 2002-04-17 Miosoft Corporation Persistent data storage techniques

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of EP2095225A4 *
SHAVIT ET AL.: "Software Transactional Memory", PROCEEDINGS OF THE 14TH SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING, OTTAWA: ACM, 1995, pages 204 - 213, XP000643146 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102272744A (zh) * 2009-01-02 2011-12-07 国际商业机器公司 用于事务存储器管理中的冲突仲裁的优先化
JP2012514780A (ja) * 2009-01-02 2012-06-28 インターナショナル・ビジネス・マシーンズ・コーポレーション トランザクション・メモリ管理における競合調停のための優先順位付けのための方法、システム、およびコンピュータ・プログラム(トランザクション・メモリ管理における競合調停のための優先順位付け)

Also Published As

Publication number Publication date
CN101535950B (zh) 2012-06-20
US20080120484A1 (en) 2008-05-22
TWI424313B (zh) 2014-01-21
CA2664041A1 (en) 2008-05-29
KR20090082256A (ko) 2009-07-29
BRPI0718463A2 (pt) 2013-12-10
RU2439663C2 (ru) 2012-01-10
EP2095225A1 (en) 2009-09-02
RU2009118454A (ru) 2010-11-20
CN101535950A (zh) 2009-09-16
TW200834303A (en) 2008-08-16
US7711678B2 (en) 2010-05-04
EP2095225B1 (en) 2017-11-01
JP2010510590A (ja) 2010-04-02
EP2095225A4 (en) 2010-10-20
JP4698757B2 (ja) 2011-06-08
KR101443930B1 (ko) 2014-09-23

Similar Documents

Publication Publication Date Title
EP2095225B1 (en) Software transaction commit order and conflict management
US8010550B2 (en) Parallelizing sequential frameworks using transactions
US7860847B2 (en) Exception ordering in contention management to support speculative sequential semantics
JP5813165B2 (ja) トランザクションを用いるシーケンシャルフレームワークの並行化
Harris et al. Language support for lightweight transactions
US7908255B2 (en) Transactional memory using buffered writes and enforced serialization order
Cotard et al. Stm-hrt: A robust and wait-free stm for hard real-time multicore embedded systems
Scott et al. Essential Theory
Gudka Lock Inference for Java
Le et al. Combining Shared State with Speculative Parallelism in a Functional Language

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780042809.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07845108

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2664041

Country of ref document: CA

ENP Entry into the national phase

Ref document number: 2009537403

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2009118454

Country of ref document: RU

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020097010737

Country of ref document: KR

REEP Request for entry into the european phase

Ref document number: 2007845108

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007845108

Country of ref document: EP

ENP Entry into the national phase

Ref document number: PI0718463

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20090317