WO2008062508A1 - Système multi-processeur - Google Patents

Système multi-processeur Download PDF

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Publication number
WO2008062508A1
WO2008062508A1 PCT/JP2006/323162 JP2006323162W WO2008062508A1 WO 2008062508 A1 WO2008062508 A1 WO 2008062508A1 JP 2006323162 W JP2006323162 W JP 2006323162W WO 2008062508 A1 WO2008062508 A1 WO 2008062508A1
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WO
WIPO (PCT)
Prior art keywords
processor element
shared resource
processor
multiprocessor system
exclusive control
Prior art date
Application number
PCT/JP2006/323162
Other languages
English (en)
Japanese (ja)
Inventor
Hiromasa Takahashi
Takashi Chiba
Shunsuke Kamijo
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/323162 priority Critical patent/WO2008062508A1/fr
Publication of WO2008062508A1 publication Critical patent/WO2008062508A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Definitions

  • the present invention relates to a multiprocessor system including a plurality of processor elements, and more particularly to a technique for improving the reliability of an embedded multiprocessor system.
  • a multiprocessor system generally includes a plurality of processor elements and shared resources shared by them.
  • exclusive control that prohibits access to a shared resource from another processor element is required during a period in which a shared resource of one of a plurality of processor elements is occupied. For example, when a plurality of processor elements use a specific memory area to write and read data in a predetermined order, exclusive control is required for the use of that memory area.
  • exclusive control for example, an exclusive control table that manages the state of each shared resource is used.
  • the processor element accesses the exclusion control table and sets the lock bit of the shared resource.
  • the processor element resets the lock bit when releasing the shared resources it has occupied.
  • other processor elements use the shared resource, they refer to the lock bit of the shared resource. At this time, if the lock bit is set, the processor element cannot use the shared resource.
  • Patent Document 1 describes a configuration for solving this problem in a large-scale server system.
  • a processor element uses a shared resource
  • the OS that receives the use request refers to the shared resource management table and checks whether the requested shared resource is being used by another processor element. If the shared resource is not being used by another processor element, the use permission is granted to the processor element that issued the use request.
  • the OS detects that a certain shared resource is continuously occupied by a single processor element for a predetermined time or longer, the OS forcibly releases the occupied state.
  • An embedded system is an information processing system built in a target device to be controlled, and controls the operation of the device using one or more processors.
  • multi-processor configurations are being introduced in embedded systems that require high processing power, while these systems require high reliability (for example, in automobiles and aircraft). Many control systems are incorporated.
  • the embedded system controls the operation of the device, it is usually required to have real-time characteristics. That is, the embedded system is required to have a high speed response compared to the server system.
  • the processing capacity of processor elements used in embedded systems is usually about a fraction of the processor elements used in server systems. For this reason, if the amount of processing related to exclusive control monitoring increases in an embedded system, the responsiveness of the original process (ie, application execution) may be degraded. That is, in an embedded system, it is preferable to reduce the amount of processing related to exclusive control monitoring as much as possible.
  • Patent Document 1 Japanese Patent Laid-Open No. 6-19858
  • An object of the present invention is to improve the reliability of exclusive control of shared resources in a multiprocessor system.
  • the multiprocessor system of the present invention includes a plurality of processor elements, a shared resource used by the plurality of processor elements, and a management unit that manages the state of the shared resource.
  • Each processor element includes a reference means for referring to the management means when trying to use the shared resource, a clocking means for performing a clocking operation when the shared resource is locked by another processor element, and the clocking Resetting means for releasing the lock by resetting the management means when the time counted by the means matches or exceeds a predetermined threshold value.
  • the processor element checks the state of the shared resource with reference to the management means. At this time, if it is detected that the shared resource is locked, the processor element starts timing. When the threshold time elapses without releasing the shared resource, the processor element resets the exclusive control information in the management means. The reset corresponds to, for example, an operation of writing information indicating that the shared resource is not locked to the management unit.
  • FIG. 1 is a diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.
  • FIG. 2 is an example of an exclusive control table.
  • FIG. 3 is a diagram showing a configuration of a counter unit.
  • FIG. 4 is a flowchart showing an exclusive control sequence.
  • FIG. 5 is a time chart showing the operation of the multiprocessor system.
  • FIG. 6 is a diagram showing a configuration of a multiprocessor system according to another embodiment.
  • FIG. 7 is a diagram showing a configuration of a counter unit according to another embodiment.
  • FIG. 1 is a diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.
  • the number of force processor elements indicating a configuration incorporating four processor elements (PEO to PE3) is not particularly limited. That is, the present invention can be applied to a multiprocessor system provided with two or more processor elements.
  • the multiprocessor system of the embodiment is not particularly limited.
  • the multiprocessor system is used by being incorporated in a device to be controlled (for example, an aircraft, an automobile, etc.).
  • the device to be controlled includes a plurality of device elements.
  • the operation of each device element is controlled by the multiprocessor system of the embodiment executing a plurality of application programs in parallel.
  • Each processor element PEO to PE3 includes a processor core that executes a given program.
  • the program executed by each processor element PEO to PE3 is, for example, an application program for controlling the operation of the control target device.
  • Each processor element PEO to PE3 includes a counter 1 described later.
  • the processor elements PEO to PE3 are each connected to the memory bus 10.
  • a memory 20 is connected to the memory bus 10.
  • the memory 20 is a storage device used by the processor elements PEO to PE3.
  • a shared area 21 is provided in the memory 20.
  • the shared area 21 is an area in which writing Z reading power by the processor elements PEO to PE3 is exclusively performed. For example, after the processor element PEO has written data to the shared area 21, another processor element In order to guarantee the procedure in which the processor refers to the data written in the shared area 21, the period until the data writing to the shared area 21 by the processor element PEO is completed is shared by other processor elements. Access to area 21 must be prohibited. At this time, the processor element PEO occupies the shared area 21. In the following, the fact that one processor element occupies the shared area 21 is referred to as “lock”.
  • the exclusive control table 22 is provided in the memory 20 and manages the state of shared resources of the multiprocessor system.
  • the shared resource means a resource shared by the processor elements PEO to PE3 while executing exclusive control.
  • the shared area 21 is one of shared resources.
  • the memory bus 10 may also be controlled as a shared resource.
  • the exclusive control table 22 includes an entry number, a lock bit, and a PE identifier (PE-ID).
  • the entry number identifies the shared resource. It is assumed that the entry number is determined in advance and written in the exclusive control table 22.
  • the lock bit indicates whether or not the corresponding shared resource is locked. For example, “1” represents a locked state, and “0” represents an unlocked state.
  • the lock bit is basically updated by the processor element that uses the corresponding shared resource. However, as described in detail later, the lock bit may be updated by other processor elements.
  • the PE identifier represents the processor element that occupies the corresponding shared resource. This PE identifier is basically updated with the lock bit.
  • the processor element PEO issues an exclusive control instruction to lock the shared area 21, if the lock bit of the shared area 21 is “1” in the exclusive control table 22, the shared area 21 Judged to be locked by the processor element. In this case, the processor element PEO cannot use the shared area 21.
  • the lock bit of the shared area 21 in the exclusive control table 22 is “0”, the shared area 21 is not locked, so that the processor element PE0 can lock the shared area 21.
  • “1” is written in the lock bit corresponding to the shared area 21, and the PE identifier for identifying the processor element PE0 (ie, “PE0”) is written.
  • the processor element PE1 intends to use the shared area 21.
  • the processor element PE1 issues an exclusive control instruction for locking the shared area 21.
  • the shared area 21 is locked by the processor element PE 0, and “1” is written in the lock bit of the shared area 21 in the exclusive control table 22. Therefore, the exclusive control instruction of the processor element PE1 fails to acquire the lock. In other words, the processor element PE1 cannot use the shared area 21.
  • the processor element PE1 periodically issues exclusive control instructions until the shared area 21 is released.
  • the processor element PEO When the processing using the shared area 21 is completed, the processor element PEO writes “0” in the lock bit of the shared area 21 in the exclusive control table 22. At this time, the PE identifier is deleted. As a result, the shared area 21 is released. Therefore, the shared area 21 can be used by other processor elements thereafter.
  • FIG. 3 is a diagram showing a configuration of the counter unit 1 included in each processor element.
  • the configuration of the counter unit 1 included in each processor element PEO to PE3 is the same.
  • the counter 31 starts a count-up operation when a predetermined value (for example, “1”) is written in the start register 32.
  • the count value of the counter 31 is incremented by the clock signal. Therefore, the counter 31 measures the elapsed time even when the count-up operation is started.
  • the counter 31 is reset when a predetermined value (for example, “1”) is written in the clear register 33.
  • the threshold value register 34 holds a predetermined threshold value.
  • the comparator 35 compares the count value of the counter 31 with the threshold value held in the threshold value register 34. When the count value exceeds the threshold value (or when the count value matches the threshold value), the comparator 35 generates a failure detection signal indicating that a failure in the exclusive control of the shared resource is detected.
  • the interrupt vector register 36 holds an interrupt number corresponding to a failure in exclusive control. When a failure detection signal is generated by the comparator 35, a failure detection interrupt to the processor core is generated according to the interrupt number held in the interrupt vector register 36.
  • the PE identifier (PE—ID) from which the entry power corresponding to the exclusive control table 22 is also read is written.
  • the entry number as well as the PE identifier may be written to the ID register 37.
  • the status register 38 is written with status information indicating whether the counter 31 is counting or not. The status information is determined according to the combination of values written to the start register 32 and the clear register 33.
  • FIG. 4 is a flowchart showing an exclusive control sequence. The processing in this flowchart is executed by a processor element that intends to use a shared resource.
  • step S1 an exclusive control command for locking a shared resource to be used (for example, shared area 21) is issued.
  • This instruction is, for example, “Compare & swap” described above, and is issued by the processor core.
  • the lock bit is read from the corresponding entry in the exclusive control table 22.
  • step S2 it is checked whether or not the shared resource has been successfully locked.
  • the counter 31 is reset in step S21.
  • step S21 corresponds to a process of writing “1” to the clear register 33.
  • step S21 normal operations related to exclusive control of shared resources are executed.
  • This operation includes a procedure for rewriting the corresponding lock bit in the exclusive control table 22 from “0” to “1”. As a result, the shared resource is locked by this processor element, and no other processor element can use this shared resource.
  • step S3 If the lock bit read from the exclusive control table 22 is “1”, the shared resource is being used by another processor element, and the processor element cannot use the shared resource. In this case, status information representing the state of the counter 31 is checked by referring to the status register 38 in step S3. If the status information is “0” (step S3: No), it is determined that the counter 31 has performed a counting operation! Subsequently, in step S4, the PE identifier for identifying the processor element using the shared resource is read from the exclusive control table 22.
  • step S 5 the counter register 31 is instructed to start counting by writing “1” to the start register 32.
  • step S6 the PE identifier read from the exclusive control table 22 is written into the ID register 37.
  • step S2 When the shared resource lock has failed (step S2: No), if the counter 31 has already started counting (step S3: Yes), the processing from step S11 onward is executed. .
  • step S 11 the PE identifier for identifying the processor element using the shared resource is read from the exclusive control table 22. Subsequently, in step S12, the PE identifier read in step S11 is compared with the PE identifier written in the ID register 37. If they match each other, it is determined that the shared resource is continuously used by the same processor element, and the process proceeds to step S14. When the two PE identifiers do not match each other, it is determined that the processor element that locks the shared resource has changed, and after resetting the counter 31 in step S13, steps S5 and S6 are executed.
  • step S14 it is checked whether or not the count value of the counter 31 exceeds the threshold value.
  • the threshold value is held in the threshold value register 34. Further, the process of step S14 is executed by the comparator 35. If the count value of the counter 31 has not reached the threshold value, the process returns to step S1. On the other hand, if the count value exceeds the threshold value, a fault detection interrupt is executed in step S15. The failure detection interrupt signal is given to the processor core according to the interrupt number held in the interrupt vector register 36.
  • step S16 the lock bit of the corresponding entry in the exclusive control table 22 is forcibly reset. That is, “0” is written in the lock bit. As a result, any processor element can use this shared resource thereafter.
  • step 7 the ID register 37 is referred to, and the processor element that continuously occupied the shared resource due to the failure is detected, and the recovery process is executed.
  • the recovery process is a process for notifying other processor elements of the occurrence of a failure, a process for disconnecting a failed processor element from a multiprocessor system, and an application executed by a failed processor element. Including the process assigned to.
  • the threshold value represents a time for determining a failure of the processor element. For this reason, the threshold time is sufficiently longer than the time required for a processor element to occupy a shared resource and execute one process. However, if the threshold time is set too long, the responsiveness for failure recovery decreases. Therefore, the threshold time must be set appropriately according to the target device controlled by the multiprocessor system.
  • FIG. 5 is a time chart showing the operation of the multiprocessor system shown in FIG.
  • the processor element PEO has locked the shared area 21 shown in FIG. That is, in the exclusive control table 22, “1” is set in the lock bit of the shared area 21, and “PEO” is written as the PE identifier. (Sequence 1 in Figure 1)
  • processor element PE1 attempts to use shared area 21.
  • the processor element PE1 issues an exclusive control instruction and refers to the exclusive control table 22 (sequence 2 in FIG. 1).
  • the processor element PE 1 cannot use the shared area 21 (lock failure). Due to this lock failure, the following operations are performed in processor element PE1.
  • the processor element PE1 In order to use the shared area 21, the processor element PE1 repeatedly issues an exclusive control instruction. However, since the lock bit of the shared area 21 remains “1”, the processor element PE1 cannot use the shared area 21. On the other hand, the counter 31 of the processor element PE1 continues counting. When the processor element PE1 issues an exclusive control instruction, the count value of the counter 31 reaches the threshold value (here, “8”). Then, the following operations are performed on the processor element PE1!
  • the processor element that subsequently accesses the shared resource detects the failure and releases the lock. In other words, it is not necessary to constantly monitor the status of each shared resource (used Z unused). When a certain processor element tries to use a shared resource, the status of the shared resource is checked. Therefore, the load required to monitor exclusive control is small for the entire multiprocessor system.
  • the function of detecting a lock abnormality caused by a failure of another processor element is mainly provided by the counter unit 1.
  • the counter unit 1 is a hardware circuit built in each processor element. Therefore, the burden on the processor core of each processor element is small. In other words, even if a processor element having a processor core with a small processing capacity is mounted, the effect on the operation of the processor core is small. Furthermore, since the above functions are not executed by the OS itself, the responsiveness is good.
  • FIG. 6 is a diagram showing a configuration of a multiprocessor system according to another embodiment of the present invention.
  • the processor elements PE0 to PE3, the memory bus 10, the memory 20, and the shared area 21 are as described with reference to FIG.
  • the counter unit 2 included in each processor element is different from the counter unit 1 shown in FIG.
  • the memory bus 10 is exclusively used.
  • each of the processor elements PEO to PE3 accesses the memory 10 via the memory controller 41.
  • the memory controller 41 manages the state of the memory bus 10.
  • the status of the memory bus 10 is notified to each of the processor elements PEO to PE3 by transmitting a bus lock status signal via the status notification bus 42.
  • the basic sequence of exclusive control of the memory bus 10 is as follows. For example, when the processor element PE0 needs to occupy the memory bus 10, first, the bus lock status signal notified via the status notification bus 42 is checked. If this signal is a value other than “000”, the processor element PE0 waits. When the bus lock state signal becomes “000”, the processor element PE0 turns on the bus lock request signal. The memory controller 41 that has received the bus lock request signal from the processor element PE0 transmits “100” as the bus lock state signal when permitting the request. As a result, the other processor elements PE1 to PE3 cannot use the memory bus 10, and the processor element PE0 occupies the memory bus 10.
  • the processor element PE0 turns off the no-lock request signal. Then, the memory controller 41 transmits “000” as a bus lock state signal. As a result, the memory bus 10 is released.
  • each processor element includes a counter unit 2.
  • FIG. 7 is a diagram showing a configuration of the counter unit 2 of another embodiment.
  • the selector 51 normally selects and outputs a signal generated by the processor core, and the comparator 54 also outputs “0” when a negate signal is given.
  • the output signal of the selector 51 is transmitted to the memory controller 41 as a bus lock request signal.
  • the decoder 52 decodes the bus lock state signal transmitted from the memory controller 41. At this time, the decoder 52 outputs “1” when it receives a bus lock state signal indicating that the memory bus 10 is locked by the processor element, and outputs “0” otherwise. For example, in the processor element PEO, “1” is output when the bus lock state signal is “100”, and “0” is output otherwise.
  • the decoding result of the decoder 52 is given to the counter 53 as a counter control signal.
  • the counter 53 starts the count operation when “1” is given as the counter control signal, and clears the count value when “0” is given.
  • the comparator 54 compares the count value of the counter 53 with the threshold value stored in the threshold value register 55. When the count value of the counter 53 exceeds the threshold value (or when the count value matches the threshold value), the comparator 53 outputs a negate signal. The negate signal is supplied to the selector 51 and also to the processor core as an interrupt signal.
  • a method of exclusive control using the counter unit 2 having the above configuration is as follows. Here, the operation of the processor element PEO is explained.
  • the processor element PEO When using the memory bus 10, the processor element PEO turns on the no-lock request signal. When this request is granted by the memory controller 41, the bus lock status signal becomes “100”.
  • the decoder 52 decodes the bus lock state signal and outputs “1” as a counter control signal. Then, the counter 53 starts counting operation. During the period when the bus lock status signal is “100”, other processor elements cannot use the memory bus 10.
  • the processor element PE0 When the processor element PE0 finishes occupying the memory bus 10, the processor element PE0 turns off the no-lock request signal. In this case, the bus lock state signal is “000”. Then, the decoder 52 outputs “0” as the counter control signal, and the counter 53 resets the count value and stops the count operation. Note that any processor element can use the memory bus 10 while the bus lock state signal is “000”. [0049] In a situation where the memory bus 10 is occupied by the processor element PEO !, if the processor core of the processor element PEO fails, the bus lock status signal remains "100". Then, since the counter 53 continues the count operation, the count value eventually exceeds the threshold value. When this count value exceeds the threshold value, a negate signal is generated, and the selector 51 selects “0” and outputs it. Then, the memory controller 41 releases the memory bus 10. In addition, an interrupt is generated for the processor core and the recovery program is started.
  • the counter of the processor element A procedure is performed for unit 2 to detect a failure and release shared resources.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
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  • Hardware Redundancy (AREA)

Abstract

La présente invention concerne une zone partagée (21) par une pluralité d'éléments de processeur (PE0 à PE3). Si un certain élément de processeur (PE0) prend la zone partagée (21), les informations l'exprimant sont écrites sur une table de commande exclusive (22). Un autre élément de processeur (PE1) se rapporte à la table de commande exclusive (22) lorsqu'il utilise les données partagées (21). Si la zone partagée est verrouillée, une unité de compteur (1) de l'autre élément de processeur (PE1) démarre une opération de comptage. Lorsque la zone partagée (21) est toujours verrouillée, même si la valeur de compte dépasse une valeur seuil, l'autre élément de processeur (PE1) réinitialise la table de commande exclusive (22).
PCT/JP2006/323162 2006-11-21 2006-11-21 Système multi-processeur WO2008062508A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108897248A (zh) * 2018-06-07 2018-11-27 浙江国自机器人技术有限公司 一种多cpu控制器和移动机器人

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175064A (ja) * 1987-12-28 1989-07-11 Fanuc Ltd バスエラー検出回路
JPH02108149A (ja) * 1988-10-18 1990-04-20 Oki Electric Ind Co Ltd マルチプロセッサの排他制御機構
JPH06149765A (ja) * 1992-11-12 1994-05-31 Fujitsu Ltd 共有メモリ排他制御自動解除方式
JP2001142861A (ja) * 1999-11-15 2001-05-25 Mitsubishi Electric Corp マルチプロセッサシステム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175064A (ja) * 1987-12-28 1989-07-11 Fanuc Ltd バスエラー検出回路
JPH02108149A (ja) * 1988-10-18 1990-04-20 Oki Electric Ind Co Ltd マルチプロセッサの排他制御機構
JPH06149765A (ja) * 1992-11-12 1994-05-31 Fujitsu Ltd 共有メモリ排他制御自動解除方式
JP2001142861A (ja) * 1999-11-15 2001-05-25 Mitsubishi Electric Corp マルチプロセッサシステム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108897248A (zh) * 2018-06-07 2018-11-27 浙江国自机器人技术有限公司 一种多cpu控制器和移动机器人

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