WO2008056351A1 - Programmation d'une mémoire flash nand avec perturbation de programme réduite - Google Patents

Programmation d'une mémoire flash nand avec perturbation de programme réduite Download PDF

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Publication number
WO2008056351A1
WO2008056351A1 PCT/IL2007/001344 IL2007001344W WO2008056351A1 WO 2008056351 A1 WO2008056351 A1 WO 2008056351A1 IL 2007001344 W IL2007001344 W IL 2007001344W WO 2008056351 A1 WO2008056351 A1 WO 2008056351A1
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WIPO (PCT)
Prior art keywords
cells
bits
pluralities
voltage
storing
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PCT/IL2007/001344
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English (en)
Inventor
Mark Shlick
Mark Murin
Original Assignee
Sandisk Il Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/806,111 external-priority patent/US8059456B2/en
Application filed by Sandisk Il Ltd. filed Critical Sandisk Il Ltd.
Priority to CN200780041450.3A priority Critical patent/CN101573763B/zh
Publication of WO2008056351A1 publication Critical patent/WO2008056351A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices

Definitions

  • the present invention relates to programming flash memories and, more particularly, to a method of programming a flash memory such as a NAND flash memory with reduced program disturb.
  • Flash memory devices are used in various applications to store digital information.
  • a basic flash cell consists of a transistor with a floating gate positioned between the channel and the transistor's control gate.
  • the threshold voltage of the transistor is defined as the lowest voltage that, when applied to the control gate of the transistor, changes the channel state from a non-conducting state to a conducting state. This voltage is affected by the amount of negative charge trapped in the floating gate: the more charge, the higher the threshold voltage of the cell.
  • SLC Single Level Cell
  • SLC Single Level Cell
  • SLC Single Level Cell
  • the cell state can be represented by the cell's threshold voltage, in this case using two voltage levels, "1" state voltage and "0" state voltage.
  • MLC Multi Level Cell
  • N bits per cell can be represented using 2 voltage levels.
  • Using high number of bits per cell allows producing Flash devices with high data density and thus reduces the overall cost per Flash device.
  • a NAND Flash device consists of arrays of cells, called blocks.
  • a block is built as a matrix in which the rows are word lines (WL) that connect the control gates of the cells, and each column is a chain of floating gate cells that are connected to a corresponding bit line (BL) on one side of the chain via a first select gate SGD, and on the other side of the chain to a common source line via a second select gate SGS.
  • the SGD gates are connected to form a SGD line and the SGS gates are connected to form a SGS line, similar to the manner in which the control gates are connected to from the WL.
  • An example of one block of a NAND Flash array with 8 WL's and 4256 BL's is shown in Figure 1.
  • a physical page of such a memory includes the cells that have their transistor gates connected to the same WL.
  • Each page in the example shown in Figure 1 includes 4256 cells, so the block shown in Figure 1 includes 8 pages of 4256 cells each, for a total of 34,048 cells.
  • an erase operation of a NAND block the whole block is erased as described below, and program and read operations on NAND cells are done on a per-page basis.
  • a block of cells is defined as the smallest chunk of cells that are erased simultaneously, and a page of cells is defined as the smallest chunk of cells that are written (programmed) simultaneously.
  • programming the cell.
  • Writing and “programming” are used interchangeably herein.
  • An erase operation involves applying a high voltage between the C-p-well (an area in the silicon structure of the Flash device that is located under the cells and that is common to all the cells) and all the WL's of the selected block, with the WL's being held at 0 voltage. This high voltage causes the affected floating gates to discharge any charge that was trapped in the floating gate by a previous programming operation, thus bringing the cells to the erased state.
  • a programming operation involves applying a high voltage to the selected WL and applying a lower voltage to other WL's so as to bring the other WL's to a conducting state.
  • the BL' s of the cells that are to be programmed are kept at 0 voltage so the cells are put under stress caused by the high voltage of the selected WL and 0 voltage of the BL' s.
  • the BL' s of the cells that are not intended to be programmed are connected to a voltage level such that the stress caused by the difference between the BL' s and the voltage applied to the WL is not enough to cause a change in the floating gate charges of the cells.
  • the programming process is made up of a series of programming pulses, interleaved with verification operations in which each cell's target threshold voltage is applied to the cell gate to check if more charge should be trapped in the floating gate. If more charge needs to be trapped in any cell's floating gate, another programming pulse is applied with a slightly higher amplitude or longer duration than the preceding programming pulse. If the cell has reached its target threshold voltage, its further programming is inhibited by applying an appropriate voltage level to its BL, similar to the cells that are not intended to be programmed.
  • a read or verify process involves applying one or more reference voltage levels to a cell gate and checking whether the cell is conductive. This reference voltage is applied to the selected WL.
  • the other WL's are connected to a read pass voltage that makes the other cells conductive, and the cell's chain's SGS line is held at conducting state to connect the chain to the C-source line, which is kept at 0 voltage.
  • the BL is precharged with some voltage, and if the reference voltage applied to the selected WL is higher than the tested cell's threshold voltage, then the tested cell becomes conducting, which makes the whole chain conducting, and the precharged BL voltage decreases.
  • test voltage applied to the tested cell is lower than the tested cell's threshold voltage, then the tested cell prevents conducting through the chain of cells and the voltage applied to the BL stays at its precharged level.
  • Sense amplifiers connected to the BL's make the decision about the cell's state.
  • a reference voltage that is used to verify the correct programming of one or more memory cells is termed a "verify voltage" herein.
  • the read operation of a SLC device uses one reference voltage level that is between the "0" and "1" voltage levels.
  • the read operation in a MLC device with 4 cell states uses 3 reference voltage levels, and a device that stores N bits per cell, that are represented by 2 states, needs 2 ⁇ -1 reference voltage levels for read operations.
  • Phenomena related to the Flash programming operation such as cross coupling and program disturb, cause the actual threshold voltage distributions of a population of flash cells to take the form of 2 voltage groups for an JV-bits-per-cell device.
  • An example of threshold voltage distributions in a device with 8 nominal threshold voltage levels is shown in Figure 2.
  • the corresponding reference voltages for reading the cells of such a device should be between the voltage groups: V R I, V R2 , V R3 , V R4 , V RS , V R6 and VR 7 as shown in Figure 2.
  • the threshold voltage level groups should be separated for reliable read operation, and using a high number of voltage levels implies a larger difference between the lowest voltage level and the highest voltage level.
  • High voltage levels require using a high programming pulse voltage applied to the WL during the programming operation, and this increases a program disturb effect as shown below.
  • a program operation puts a stress on the cells to be programmed, by applying a high voltage to the selected WL and 0 voltage to the selected BL, with the unselected WL' s kept at conducting voltage and unselected BL's kept at some voltage that is lower than the programming voltage. Although all the gates of the selected page are connected to the high voltage applied to the selected WL, the programming stress is applied only to the cells at the intersections of the selected WL and the selected BL' s, as the difference between the WL voltage and unselected BL' s is lower than the difference between the WL voltage and the selected BL' s.
  • the following example illustrates the program disturb effect in a simplified situation in which the data to be programmed to a flash memory are to be represented by 8 voltage levels, #0 through #7.
  • Different programming techniques exist, but they usually use a sequential increase of the programming voltage to program the different voltage levels, so this example assumes programming level #1, then #2, and so on till #7.
  • This example also assumes that the cells to be programmed to the level #N are first programmed to levels # 1 through #(N-l) and then using higher programming voltages these cells are programmed to level #N.
  • the example assumes that the user data are represented by all 8 voltage levels and the user data are evenly distributed among these 8 levels.
  • the programming starts with all cells in the erased state, as shown in Figure 3.
  • the voltage distribution after programming the level #1 is shown in Figure 4, where the level #1 includes the cells that are to be programmed to level #1 and also the cells that are to be programmed to levels #2 through #7.
  • the BL's of the cells that are to be programmed to level #1 are put in an inhibit state after these cells reach their target charge in their floating gates.
  • Figure 5 shows the voltage distribution after programming to level #2, where the level #2 includes the cells that are to be programmed to level #2 and also the cells that are to be programmed to levels #3 through #7.
  • the voltage distribution after programming level #7 is shown in Figure 6, where the widening and shifting of the low level distributions, such as distributions #0 and #1, is caused mainly by the program disturb phenomenon when programming high levels such as levels #6 and #7. It can be seen that some of the level #1 cells have become level #2 cells, so when the data are read from the flash they will be read with errors.
  • Various techniques try to adjust the voltage levels being programmed so the final voltage distribution is narrow and in the right place, but the fact that the program disturb effect depends on the data content that is programmed makes it difficult to design a proper technique that works for all data patterns.
  • the location of the level #1 could be set to a lower voltage first, so the program disturb caused by the programming the levels #6 and #7 would bring the #1 distribution to the right position, but this technique would fail for a page that does not include data represented by levels #6 and #7, as in this case the program disturb effect caused by the lower levels is much smaller, and some of the #1 cells would be read as #0 cells.
  • the present invention is a technique for multiple-bits-per-cell Flash device programming that reduces the program disturb effect.
  • a method of storing data in a memory device including the steps of: (a) receiving, from a host of the memory device, at least two pluralities of bits to store in a plurality of cells of a nonvolatile memory of the memory device; (b) storing the at least two pluralities of bits in a volatile memory of the memory device; and (c) subsequent to the storing of the at least two pluralities of bits in the volatile memory, storing the at least two pluralities of bits in the plurality of cells, by steps including: (i) raising a threshold voltage of a first at least one of the cells to a first value that is greater than a verify voltage; and (ii) while the threshold voltage of each first at least one cell remains substantially at the first value, raising a threshold voltage of a second at least one of the cells to a second value that is less than the verify voltage; wherein at least one bit of each of
  • a memory device including: (a) a nonvolatile memory that includes a plurality of cells; (b) a volatile memory; and (c) a controller operative, in response to receiving, from a host of the memory device, at least two pluralities of bits to store in the memory device: (i) to store the at least two pluralities of bits in the volatile memory, and (ii) subsequent to the storing of the at least two pluralities of bits in the volatile memory: to store the at least two pluralities of bits in the plurality of cells by steps including: (A) raising a threshold voltage of a first at least one of the cells to a first value that is greater than a verify voltage, and (B) while the threshold voltage of each first at least one cell remains substantially at the first value, raising a threshold voltage of a second at least one of the cells to a second value that is less than the verify voltage, wherein at least one bit of each of the pluralities of bits is stored in at least one of the cells.
  • a method of storing data including: (a) storing at least two pluralities of bits in a volatile memory of a memory device; and (b) subsequent to the storing of the two pluralities of bits in the volatile memory, storing the at least two pluralities of bits in a plurality of cells of a nonvolatile memory of the memory device by steps including: (i) raising a threshold voltage of a first at least one of the cells to a first value that is greater than a verify voltage, and (ii) while the threshold voltage of each first at least one cell remains substantially at the first value, raising a threshold voltage of a second at least one of the cells to a second value that is less than the verify voltage; wherein at least one bit of each of the pluralities of bits is stored in at least one of the cells.
  • a system including: (a) a memory device including: (i) a volatile memory, and (ii) a first nonvolatile memory including a plurality of cells; (b) a second nonvolatile memory wherein is stored code of a software driver for the first nonvolatile memory, the code including code for storing at least two pluralities of bits in the first nonvolatile memory by steps including: (i) storing the at least two pluralities of bits in the volatile memory, and (ii) subsequent to the storing of the at least two pluralities of bits in the volatile memory, storing the at least two pluralities of bits in the plurality of cells by steps including: (A) raising a threshold voltage of a first at least one of the cells to a first value that is greater than a verify voltage, and (B) while the threshold voltage of each first at least one cell remains substantially at the first value, raising a threshold voltage of a second at least one of the cells to a second value that is less than the verify voltage, wherein at least
  • the first basic method of the present invention is a method of storing data in a memory device.
  • the memory device receives, from a host thereof, two or more pluralities of bits to store in cells of a nonvolatile memory of the memory device.
  • the pluralities of bits are stored in a volatile memory of the memory device.
  • the pluralities of bits are stored in a plurality of cells of the nonvolatile memory.
  • Storing the bits in the cells of the nonvolatile memory includes raising a threshold voltage of each of a first one or more of the cells to a first value that is greater than a verify voltage and then, while the threshold voltage(s) of the first cell(s) remain(s) substantially at the first value(s), raising a threshold voltage of each of a second one or more of the cells to a second value that is less than the verify voltage. That the threshold voltage of a cell remains "substantially" at a certain value means that any changes to the threshold voltage are sufficiently minor that the threshold voltage remains within a single threshold voltage level group. At least one bit of each plurality of bits is stored in at least one of the cells. The latter limitation distinguishes the present invention from prior art memory devices that use write caching.
  • a first plurality of bits is stored in a first volatile memory prior to being transferred to a first plurality of cells of a nonvolatile memory; and if a second plurality of bits to be stored in a second plurality of the cells arrives before the first plurality of bits have been transferred to the first plurality of cells, the second plurality of bits is stored in a second volatile memory pending the completion of the transfer of the first plurality of bits.
  • the second basic method of the present invention is similar to the first basic method, but lacks the step of receiving the pluralities of bits from a host of the memory device, so that this basic method is amenable to being implemented by the host of the memory device as well as by the memory device itself.
  • two or more pluralities of bits are stored in a volatile memory of the memory device. Subsequently, the pluralities of bits are stored in a plurality of cells of a nonvolatile memory of the memory device, in the same manner as in the first basic method.
  • each plurality of bits is stored in each one of the cells.
  • the cells share a common wordline of the nonvolatile memory.
  • each plurality of bits is sent by the host in a separate respective command.
  • the host sends two pluralities of bits to the memory device by sending a sequence of the form "programming prefix opcode, address page-1, data page-1, dummy programming suffix opcode, address page-2, data page-2, programming suffix opcode"
  • the two pluralities of bits are considered to be sent by two commands because the dummy programming suffix opcode separates the fields that define the first plurality of bits (address page-1, data page-1) from the fields that define the second plurality of bits (address page-2, data page-2).
  • the storing of the two or more pluralities of bits in the cells results in a respective bit pattern being stored in each of the one or more cells wherein are stored at least one bit from each plurality of bits.
  • the storing of the two or more pluralities of bits in the cells results in only a portion of a respective bit pattern being stored in each of the one or more cells wherein are stored at least one bit from each plurality of bits.
  • the scope of the present invention also includes a memory device that includes nonvolatile memory with a plurality of cells , a volatile memory and a controller for programming the cells, in response to receiving two or more pluralities of bits from a host, using the first method of the present invention.
  • the cells are NAND flash cells.
  • the scope of the present invention also includes a system that includes a memory device with a volatile memory and a first nonvolatile memory that includes a plurality of cells, and that also includes a second nonvolatile memory wherein is stored code of a software driver that implements the second method of the present invention, and that also includes a processor for executing the code.
  • the first nonvolatile memory is a NAND flash memory.
  • the "pluralities" of bits are "logical pages" of bits.
  • a logical page of bits is understood herein to mean a group of bits equal in number to the number of cells in a physical page, so that a physical page of iV-bit-per-cell cells can store up to N logical pages.
  • Flash memory devices typically are configured to receive one logical page of bits at a time from their hosts.
  • the device stores the logical pages in its flash memory as the logical pages arrive.
  • the device accumulates logical pages in a local nonvolatile memory such as a RAM or a set of registers until at least two logical pages' worth of bits have been accumulated (almost always until a full physical page's worth of bits have been accumulated) and then programs a physical page of its flash memory to store all the accumulated bits.
  • the present invention is directed at the second class of MLC flash memory devices.
  • FIG. 1 is a schematic diagram of a NAND flash cell block
  • FIGs. 2-6 illustrate programming the cells of a NAND word line according to the prior art
  • FIGs. 7-11 illustrate programming the cells of a NAND word line according to the present invention
  • FIG. 12 is a high-level block diagram of a memory device of the present invention
  • FIG. 13 is a partial high-level block diagram of a data storage system of the present invention.
  • the main idea of the present invention is to split the programming operation into two or more phases, in which programming the high voltage levels is followed by programming the low voltage levels.
  • the program disturb effect is very dependent on the difference of the voltage levels, so the highest shift of voltage distribution is when programming the highest voltage level and the lower voltage levels are most affected.
  • the program disturb associated with the first phase of programming the high levels affects mostly the cells that are in the erased state. Usually the final voltage levels include the erased state, so its distribution widening is taken into account when setting the reference levels.
  • the first phase of the programming uses high voltages to program the levels #4 through #7.
  • the cells' voltage distribution after programming the level #4 is shown in Figure 8.
  • the cells now at level #4 are the cells that are to be programmed to level #4 and higher, in this example levels #5, #6 and #7.
  • the distribution after programming levels #4 through #7 is shown in Figure 9. Applying high voltages for programming levels #6 and #7 has caused the cell distribution of the erased state to become wider due to program disturb effect as shown in Figure 9.
  • the second phase of the programming operation uses only lower programming voltages, as this phase programs only levels #1 to #3, so the program disturb effect on the lower levels is minimized.
  • the voltage distribution after programming the level #1 is shown in Figure 10
  • the distribution after programming levels #2 and #3 is shown in Figure 11.
  • the lower levels such as levels #1 and #2, are programmed after the programming of the high levels, such as levels #6 and #7, so the low level cell have not been affected by the program disturb effect. Furthermore, the second phase made only a small change to the width of the level #0 distribution, which is not perceptibly wider in Figure 11 than in Figure 9.
  • the essence of the present invention is that while writing a physical page of cells, the cells of the page that are to be set to high threshold voltages are programmed before programming the cells of the page that are to be set to low threshold voltages.
  • This ordering of the programming of cells according to their target states is innovative and counter to the common art in which the programming progresses from low threshold states to high threshold states. It is this non-standard ordering that provides the benefit of reduction in program-disturb effects.
  • the above example is a case in which all data bits sharing an MLC cell are simultaneously written into the cell. In other words, there is no stable state in which the cell stores less than its maximum bits capacity. In some devices the bits of a cell are written into the cell one by one, so that there are situations when some of the bits are already stored while other bits are still to be stored.
  • One common example in which such approach is preferable is when the user of the flash device provides the bits to be written sporadically, with long time intervals between the provision of successive groups of bits, so that it is advantageous to be able to store into the cell whatever bits are already available.
  • the first method of simultaneously writing all bits is called “simultaneous writing” or “simultaneous programming", while if at least one bit is stored in the cell sequentially to at least one other bit, the method is called “sequential writing” or “sequential programming”.
  • the methods of the present invention are applicable both to simultaneous writing methods and separately to each one of the stages of sequential writing methods where each stage of the sequential writing is itself written using simultaneous writing in case two or more bits are stored per cell in that stage.
  • the bits are stored simultaneously, as illustrated in Figures 7 through 11.
  • the cells that need to be programmed to store "011" are programmed to level #4; the cells that need to be programmed to store "010” are programmed to level #5; the cells that need to be programmed to store "001" are programmed to level #6; and the cells that need to be programmed to store "000” bits are programmed to level #7.
  • the unprogrammed cells that need to be programmed to store "110" are programmed to level #1; the unprogrammed cells that need to be programmed to store "101" are programmed to level #2; and the unprogrammed cells that need to be programmed to store "100” are programmed to level #3.
  • Gray code bit assignment may be used to reduce the number of bit errors in case of incorrect reading due to threshold distribution shifts:
  • the cells that need to be programmed to store "001" are programmed to level #4; the cells that need to be programmed to store "000” are programmed to level #5; the cells that need to be programmed to store "010” bits are programmed to level #6; and the cells that need to be programmed to store "011” are programmed to level #7.
  • the unprogrammed cells that need to be programmed to store "110” are programmed to level #1; the unprogrammed cells that need to be programmed to store "100” bits are programmed to level #2; and the unprogrammed cells that need to be programmed to store "101" are programmed to level
  • FIG 12 is a high-level block diagram of a flash memory device 10 of the present invention, coupled to a host 20.
  • Figure 2 is adapted from Ban, US Patent No. 5,404,485, which patent is incorporated by reference for all purposes as if fully set forth herein.
  • Flash memory device 10 includes a NAND flash memory 14 that includes blocks of cells such as the block illustrated in Figure 1, a controller 12 and a random access memory (RAM) 16.
  • controller 12 upon receiving two or more pluralities of bits from host 20 to store in a wordline of flash memory 14, controller 12 first stores the bits in RAM 16. Then controller 12 transfers the bits to the target wordline of flash memory 14. In the first programming phase, the threshold voltages of some of the cells of the wordline are raised to values above a verify voltage that distinguishes cells that store most significant "0" bits from cells that store most significant "1" bits. In the second programming phase, the threshold voltages of many of the remaining cells are raised to values below this verify voltage. Each of the cells of the wordline stores one bit from each of the pluralities received from host 20.
  • Figure 13 is a high-level partial block diagram of an alternative data storage system
  • Data storage system 40 includes a processor 42 and four memory devices: a RAM 44, a boot ROM 46, a mass storage device (hard disk) 48 and a flash memory device 30, all communicating via a common bus 50.
  • flash memory device 30 includes a NAND flash memory 32 that includes blocks of cells such as the block illustrated in Figure 1, and also an internal RAM 36.
  • flash memory device 30 lacks its own controller.
  • processor 42 emulates controller 12 by executing a software driver 52 that implements the methodology of US 5,404,485 and US 5,937,425 and that also implements the multi-bit programming methodology of the present invention.
  • software driver 52 includes a write function that, when invoked by an application executed by processor 42 to write a wordline' s worth of data bits to a wordline of flash memory 32, first stores all the bits in RAM 36 and then transfers the bits to the target wordline of flash memory 32 as described above for flash memory device 10.
  • the code of software driver 52 is stored in mass storage device 48 and is loaded into RAM 44 for execution.
  • Flash memory device 30 also includes a bus interface 34 to enable processor 42 to communicate with flash memory 32 and RAM 36.

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Abstract

L'invention concerne un dispositif mémoire qui, lorsqu'il reçoit au moins deux ensembles de bits à partir d'un hôte pour les stocker dans une mémoire non volatile, stocke tout d'abord les bits dans une mémoire volatile. Ensuite, lors du stockage des bits dans la mémoire non volatile, le dispositif élève les tensions de seuil de certaines cellules de la mémoire volatile à des valeurs supérieures à celles d'une tension de vérification. Pendant que ces tensions de seuil restent sensiblement à ces niveaux, le dispositif élève les tensions de seuil d'autres cellules de la mémoire volatile à des valeurs inférieures à celles de la tension de vérification. À la fin, chaque cellule stocke un ou plusieurs bits de chaque pluralité de bits. De préférence, toutes les cellules partagent une ligne de mots commune. Un dispositif de stockage de données fonctionne de façon analogue par rapport au stockage des pluralités de bits générés par une application s'exécutant sur le système.
PCT/IL2007/001344 2006-11-07 2007-11-04 Programmation d'une mémoire flash nand avec perturbation de programme réduite WO2008056351A1 (fr)

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US60/864,607 2006-11-07
US80610807A 2007-05-30 2007-05-30
US11/806,111 US8059456B2 (en) 2006-11-07 2007-05-30 Programming a NAND flash memory with reduced program disturb
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046935A (en) * 1996-03-18 2000-04-04 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US20020080660A1 (en) * 2000-12-26 2002-06-27 Hitachi, Ltd. Semiconductor device and data processing system
US20020191459A1 (en) * 1998-02-16 2002-12-19 Tetsuya Tsujikawa Non-volatile memory device
US20040052114A1 (en) * 1999-10-25 2004-03-18 Naoki Kobayashi Programming method of nonvolatile semiconductor memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046935A (en) * 1996-03-18 2000-04-04 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US20020191459A1 (en) * 1998-02-16 2002-12-19 Tetsuya Tsujikawa Non-volatile memory device
US20040052114A1 (en) * 1999-10-25 2004-03-18 Naoki Kobayashi Programming method of nonvolatile semiconductor memory device
US20020080660A1 (en) * 2000-12-26 2002-06-27 Hitachi, Ltd. Semiconductor device and data processing system

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