WO2008051835A1 - Dispositif de mémoire et procédé pour protéger des cellules de mémoire pendant la programmation - Google Patents

Dispositif de mémoire et procédé pour protéger des cellules de mémoire pendant la programmation Download PDF

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Publication number
WO2008051835A1
WO2008051835A1 PCT/US2007/081916 US2007081916W WO2008051835A1 WO 2008051835 A1 WO2008051835 A1 WO 2008051835A1 US 2007081916 W US2007081916 W US 2007081916W WO 2008051835 A1 WO2008051835 A1 WO 2008051835A1
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WO
WIPO (PCT)
Prior art keywords
current
memory
recited
memory element
program
Prior art date
Application number
PCT/US2007/081916
Other languages
English (en)
Inventor
Luca G. Fasoli
Tyler Thorp
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/552,441 external-priority patent/US7589989B2/en
Priority claimed from US11/552,426 external-priority patent/US7391638B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Publication of WO2008051835A1 publication Critical patent/WO2008051835A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5624—Concurrent multilevel programming and programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure

Definitions

  • the invention relates to memory devices and, more particularly, to programming non-volatile memory devices.
  • Memory devices that provide persistent data storage use non-volatile memory cells.
  • the memory devices can typically be implemented by semiconductor chips.
  • the semiconductor chips can be used internal to electronic systems or can be used within memory cards that can be removably attached to electronic systems.
  • Memory cards are commonly used to store digital data for use with various products (e.g., electronic products).
  • Memory cards often use Flash type or EEPROM type memory cells to store the data.
  • Memory cards have a relatively small form factor and have been used to store digital data for electronic products (e.g., portable consumer electronic products).
  • a major supplier of memory cards is SanDisk Corporation of Sunnyvale, CA.
  • One method applies a programming pulse of a sufficiently long duration to program a memory cell. In order to guarantee that every memory cell is able to be programmed using this method, programming time and power are set for worst- case conditions. Accordingly, this "over-provisioning" approach can result in excessive average programming time and power.
  • a series of short, high-voltage programming pulses is applied to a memory cell. After each programming pulse, a nominal-voltage reading pulse is applied to determine whether the memory cell is in a programmed state. If the memory cell is in a programmed state, no further programming pulses are applied.
  • a method for programming non-volatile memory cells made use of detection circuits. While a particular memory cell is being programmed, a detection circuit determines whether the memory cell is in a programmed state. Once the memory cell is detected to have reached the programmed state, the programming of the memory cell is terminated. Additional details on this method for programming are provided in U.S. Patent No. 6,574,145.
  • the memory cells can be subjected to high voltages and high power which are problematic when the memory cells become programmed and the programming voltage has not yet been removed. Although the programming voltage will be removed in due time after a memory cell has been programmed, the excessive power can cause damage to the already programmed memory cell.
  • the invention relates to improved circuitry and methods for programming memory cells of a memory device.
  • the improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved.
  • the improved circuitry and methods are particularly useful for programming non-volatile memory cells.
  • the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.
  • the invention can be particularly useful for use with two-terminal memory cells.
  • one embodiment of the invention includes at least: a non-volatile memory element; a current monitor configured to monitor a program current flowing through the non-volatile memory element; and a current limiter configured to restrict the current flowing through the non-volatile memory element.
  • another embodiment of the invention includes at least: a memory array including a plurality of layers of memory cells stacked vertically above one another in a single chip; a detection circuit operative to detect, while a memory cell of the memory array is being programmed, when the memory cell is in a programmed state; and a memory cell protection circuit operative to protect the memory cell of the memory array against excessive electrical energy at least while the memory cell is being programmed.
  • one embodiment of the invention includes at least: a first field-effect transistor having first, second and third terminals, the first terminal connected to a first potential; a second field-effect transistor having first, second and third terminals, the first terminal connected to the second terminal of the first field-effect transistor, and the second terminal connected to a bitline; a memory element connected to a wordline and to the bitline; a third field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a first node, and the third terminal connected to the third terminal of the first field- effect transistor; a fourth field-effect transistor having first, second and third terminals, the first terminal connected to the first node, the second terminal connected to a second potential; a fifth field-effect transistor having first, second and third terminals, the first terminal connected to a first current source, the second terminal connected to the second potential, and the third terminal is connected to
  • one embodiment of the invention includes at least: a data acquisition device; and a data storage device removably coupled to the data acquisition device.
  • the data storage device stores data acquired by the data acquisition device.
  • the data storage device includes at least: an array of data storage elements; a detection circuit operative to detect, while a data storage element of the array is being programmed, when the data storage element is in a programmed state; and a protection circuit operative to protect the data storage element of the array against excessive electrical energy at least while the memory cell is being programmed.
  • one embodiment of the invention includes at least the acts of: activating programming of a non-volatile memory element; limiting a program current being used to program the nonvolatile memory element so as to not exceed a maximum current; and deactivating the programming of the non-volatile memory element when the program current reaches a predetermined level.
  • one embodiment of the invention includes at least the acts of: coupling a program current to the non-volatile memory element to program the non-volatile memory element; monitoring program current flowing through the non-volatile memory element; and limiting current flowing through the non-volatile memory element to a current limit level, the current limit level being set higher than the program current.
  • FIG. 1 is a block diagram of a memory device according to one embodiment of the invention.
  • FIG. 2 is a flow diagram of a memory programming process according to one embodiment of the invention.
  • FIG. 3 is a schematic diagram of a memory device according to one embodiment of the invention.
  • FIG. 4 is a schematic diagram of a memory device according to another embodiment of the invention.
  • FIG. 5 is a schematic diagram of a memory device according to another embodiment of the invention.
  • FIG. 6 is a schematic diagram of a memory device according to another embodiment of the invention.
  • FIG. 7 is a schematic diagram of a memory device according to another embodiment of the invention.
  • the invention relates to improved circuitry and methods for programming memory cells of a memory device.
  • the improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved.
  • the improved circuitry and methods are particularly useful for programming non-volatile memory cells.
  • the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.
  • the invention can be particularly useful for use with two-terminal memory cells.
  • FIG. 1 is a block diagram of a memory device 100 according to one embodiment of the invention.
  • the memory device 100 includes a memory element 102.
  • the memory element 102 is, for example, a non-volatile memory element.
  • One implementation for a non-volatile memory element is a diode or antifuse type memory element.
  • the memory element 102 is typically part of a memory array.
  • the various memory elements within the memory array can be accessed by way of bitlines 104 and wordlines 106.
  • the memory element 102 is shown as being coupled between a bitline 104 and a wordline 106.
  • a voltage is applied across the memory element 102 to invoke a physical characteristic change in the memory element 102.
  • the programming of the memory element 102 is referred to as "popping" or "blowing" the antifuse.
  • the memory device 100 includes a programming switch 108.
  • the programming switch 108 couples to a voltage potential (Vp) used for programming.
  • Vp voltage potential
  • a program current (Ipmg) is supplied from the voltage potential (Vp) to a current monitor 1 12.
  • the current monitor 1 12 monitors the program current (Ipmg) that flows through the memory element 102.
  • the amount of current flowing through the memory element 102 provides an indication of whether or not the memory element 102 has been programmed.
  • the current monitor 1 12 monitors the level of the program current (Ipmg).
  • the monitored current level detected by the current monitor 1 12 is supplied to the program control circuit 1 10.
  • the program control circuit 1 10 based on the monitored current level determines whether the memory element 102 has been completely programmed.
  • the program control circuit 1 10 can signal the programming switch 108 to deactivate the programming.
  • the program control circuit 1 10 can impose a delay prior to deactivating the programming.
  • the memory device 100 also includes a current limiter 1 14.
  • the current limiter 1 14 operates to limit the maximum amount of current that is permitted to be used when programming the memory element 102. In other words, the current limiter 1 14 prevents the program current (Ipmg) from exceeding a maximum current level. The current limiter 1 14 thus protects the memory element 102 from damage during or after programming of the memory element 102.
  • a current limiter can also protect a memory element when not being programmed.
  • a pre-charging is performed in advance of programming to improve the programming.
  • the protection for the memory cells can also be used to protect the memory elements during pre- charging.
  • the programming of the memory cells can be efficient with regard to programming time and power. For example, a memory cell can be pre-charged rapidly since the current used for pre-charge can be set to the maximum level that the memory cell can withstand. Additionally, in programming a memory cell, programming occurs only for as long as it is needed. That is, unlike a fixed program duration, once a memory cell becomes programmed, its programming can be stopped. Further, programming bandwidth (the number of memory cells that can be programmed per unit time) can be high. In one embodiment, a plurality of memory cells along a wordline can be programmed simultaneously.
  • the memory element being programmed can relate to a non-volatile memory cell (i.e., a memory cell whose data is not lost or altered when electrical power is removed).
  • a non-volatile memory cell i.e., a memory cell whose data is not lost or altered when electrical power is removed.
  • the memory cell is part of a three-dimensional memory array, which can provide economies in terms of reduced size and associated reductions in manufacturing cost.
  • the memory array can include a vertical array of layers as memory cells.
  • the memory array can be part of a compact, modular memory device used with portable consumer electronic products.
  • the memory cell is field-programmable.
  • a field- programmable memory cell is a memory cell that is fabricated in an initial, un- programmed digital state and can be switched to an alternative, programmed digital state at a time after fabrication.
  • the memory cell is a write-once memory cell comprising an antifuse and a diode, for example as described in U.S. Patent No. 6,034,882 and U.S. Patent No. 6,515,888, both of which are hereby incorporated by reference.
  • the antifuse In its un-programmed state, the antifuse is intact, and the memory cell holds a Logic 1.
  • suitable voltages are applied to the appropriate wordline and bitline, the antifuse of the memory cell is blown, and the diode is connected between the wordline and the bitline. This places the memory cell in a programmed (Logic 0) state.
  • the un-programmed state of the memory cell can be Logic 0, and the programmed state can be Logic 1 .
  • Memory cells that support multiple programmed states can also be used. If the memory is of the write-once type, the initial, un-programmed digital state cannot be restored once the memory cell is switched to the programmed digital state. Instead of being write-once, the memory cell can be write-many (re-writeable). Unlike the digital state of a write-once memory cell, the digital state of a write-many memory cell can be switched between "un-programmed" and "programmed” digital states.
  • the un-programmed digital state refers to the digital state of the memory cell before a programming operation. Accordingly, the un-programmed digital state can refer to either Logic 0 or Logic 1 (in a two-state memory cell) and does not necessarily refer to the digital state in which that memory cell was fabricated.
  • FIG. 2 is a flow diagram of a memory programming process 200 according to one embodiment of the invention.
  • the memory programming process 200 is, for example, associated with programming a memory element, such as a memory element within a memory array provided within a memory device.
  • the memory programming process 200 initially activates 202 programming of a memory element.
  • the memory element is one of a plurality of memory elements provided within a memory device.
  • the memory element to be programmed can pertain to the memory element 102 of the memory device 100 illustrated in FIG. 1 .
  • a decision 204 determines whether a program current (programming current) is greater than or equal to a maximum current. When the decision 204 determines that the program current is greater than or equal to the maximum current, the program current is limited 206 to the maximum current. Following the block 206, or following the decision 204 when the program current is not greater than or equal to the maximum current, a decision 208 determines whether the program current is greater than or equal to a sense current. The sense current is an amount of current used to sense whether the programming element has been programmed. When the decision 208 determines that the program current is not greater than or equal to the sense current, then the memory programming process 200 returns to repeat the decision 204 and subsequent blocks so that the programming of the memory element can continue.
  • the memory element is protected from damage by the block 206 which prevents the program current from exceeding the maximum current.
  • the decision 208 determines that the program current is greater than the sense current, then programming of the memory element is deactivated 210.
  • the programming of the memory element is deactivated 210 because the memory element has been programmed. In other words, when the program current reaches the level of the sense current, then the memory element is programmed. Following the block 210, the memory programming process 200 ends.
  • FIG. 3 is a schematic diagram of a memory device 300 according to one embodiment of the invention.
  • the memory device 300 includes a memory element 302. As depicted in FIG. 3, the memory element 302 is being programmed (written).
  • the memory element 302 is coupled between a bitline 304 and a wordline 306, which enables selection of the memory element 302 from a plurality of memory elements in the memory device 300.
  • the memory element 302 is programmed by supplying a programming voltage across the memory element 302 which induces a program current (Ipmg) through the memory element 302.
  • the program current (Ipmg) is supplied by a field-effect transistor (FET) 308.
  • the program current (Ipmg) is also limited by a FET 310.
  • the FET 310 is controlled by a node 312.
  • the node 312 is provided between a FET 314 and a current source (Imax) 316.
  • Imax current source
  • the program current (Ipmg) exceeds the maximum current (Imax)
  • the node 312 is pulled high by the FET 314.
  • the FET 312 operates to restrict or stop the program current (Ipmg) from reaching the memory element 302.
  • the memory device 300 also includes a FET 318 that couples between the programming potential (Vp) and a node 320.
  • the node 320 is also coupled to ground by way of a sense current source (Is) 322.
  • Is sense current source
  • the program control circuit 324 can cause a FET 326 to turn off the FET 308, thereby ceasing programming of the memory element 302.
  • the program control circuit 324 can cause a FET 328 to turn off, thereby disconnecting the gate of the FET 308 from the drain of the FET 308.
  • the program control circuit 324 can turn off the FET 328 via an inverter 330.
  • the program control circuit 324 can induce a delay and thus need not be immediately responsive to a change in voltage level of the second node 320.
  • FIG. 4 is a schematic diagram of a memory device 400 according to another embodiment of the invention.
  • the memory device 400 illustrated in FIG. 4 is generally similar to the memory device 300 illustrated in FIG. 3. However, the memory device 400 includes additional implementation details that can be provided in accordance with one embodiment of the invention.
  • the memory device 400 includes a memory element 402.
  • the memory element 402 is coupled between a bitline 404 and a wordline 406.
  • the memory device 400 operates, in one mode, to program the memory element 402 by applying a voltage across the memory element 402.
  • the result of the voltage across the memory element 402 is to effectuate programming of the memory element.
  • the program current (Ipmg) passing through the memory element 402 increases. At some point, the level of the program current (Ipmg) can signal that the memory element 402 has been adequately programmed.
  • the memory device 400 includes a first FET 408 that couples to a voltage potential (Vp) suitable for programming.
  • the first FET 408 is utilized to provide the program current (Ipmg) that is used to program the memory element 402.
  • a second FET 410 couples between the first FET 408 and the memory element 402.
  • the second FET 410 is utilized to limit the amount of current that can flow through to the memory element 402. In other words, the FET 410 is controlled to limit the program current (Ipmg) to a maximum level.
  • a third FET 412 is also provided to bias a gate terminal of the FET 408.
  • a source terminal of the FET 408 is coupled to the voltage potential (Vp) and a drain terminal of the FET 408 is coupled to a drain terminal of the FET 410 at a node 413.
  • a source terminal of the FET 410 is coupled to the memory element 402 by way of the bitline 404.
  • a drain terminal of the FET 412 is coupled to the voltage potential (Vp), a gate terminal of the FET 412 is connected to the node 413, and a source terminal of the FET 412 is coupled to the gate terminal of the FET 408 as well as to a bias current source (Ibias) 414.
  • the memory device 400 also includes a FET 415, a node 416, and FETs 418 and 420.
  • the FET 415 has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET 408, and a drain terminal connected to the node 416.
  • the gate terminal of the FET 410 also connects to the node 416.
  • the FETs 418 and 420 are connected to form a current mirror circuit for a maximum reference current (Imax).
  • the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET 408 is mirrored to the FET 415.
  • This program current (Ipmg) is compared to a maximum current (Imax) at the node 416. If the program current exceeds the maximum current, the node 416 is pulled high so as to restrict or prevent the program current (Ipmg) from being provided to the memory element 402.
  • the memory device 400 also includes a FET 422, a node 424, and FETs 426 and 428.
  • the FET 422 has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET 408 and a drain terminal connected to a node 424.
  • the FETs 426 and 428 provide a current mirror circuit for a sense reference current (Is).
  • a drain terminal of the FET 426 is coupled to the node 424.
  • the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET 408 is mirrored to the FET 422.
  • the node 424 can determine whether the program current (Ipmg) exceeds the sense reference current (Is).
  • the program control circuit 430 When the program current (Ipmg) exceeds the sense reference current (Is), the node 424 is pulled high. When the node 424 is pulled high, a program control circuit 430 understands that the programming of the memory element 402 has been completed. At this point, either immediately or following a predetermined delay, the program control circuit 430 can instruct a FET 432 to disable further programming of the memory element 402.
  • the FET 432 has its source terminal connected to the voltage potential (Vp) and a drain terminal connected to the gate terminal of the FET 408. Further, the gate terminal of the FET 432 is connected to the program control circuit 430.
  • the current mirror circuits can use a different ratio than the programming circuitry.
  • the channel width for the FETs 415 and 422 can be made smaller than the channel width of the FET 408, thereby producing lower currents in the current mirror circuits which in turn reduces power consumption.
  • the FET 408 could be manufactured to be N-times that of the FETs 415 and 422, where N is the desired current ratio. In such an example, the FET 408 can be implemented using N transistors used in parallel relative to using one transistor for the FETs 415 and 422.
  • FIG. 5 is a schematic diagram of a memory device 500 according to another embodiment of the invention.
  • the memory device 500 illustrated in FIG. 5 provides separate circuitry for monitoring programming and limiting program current as do the memory device 300 illustrated in FIG. 3 and the memory device 400 illustrated in FIG. 4.
  • the memory device 500 utilizes a double current mirror design.
  • the memory device 500 includes a memory element 502.
  • the memory element 502 is coupled between a bitline 504 and a wordline 506.
  • the memory device 500 operates, in one mode, to program the memory element 502 by applying a voltage across the memory element 502.
  • the result of the voltage across the memory element 502 is to effectuate programming of the memory element 502.
  • the program current (Ipmg) passing through the memory element 502 increases.
  • the level of the program current (Ipmg) can signal that the memory element 502 has been adequately programmed.
  • the memory device 500 includes a first FET 508 that couples to a voltage potential (Vp) suitable for programming.
  • the first FET 508 is utilized to provide the program current (Ipmg) that is used to program the memory element 502.
  • a second FET 510 couples between the first FET 508 and the memory element 502.
  • the second FET 510 is utilized to limit the amount of current that can flow through to the memory element 502. In other words, the FET 510 is controlled to limit the program current (Ipmg) to a maximum level.
  • a source terminal of the FET 508 is coupled to the voltage potential (Vp) and a drain terminal of the FET 508 is coupled to a drain terminal of the FET 510.
  • a source terminal of the FET 510 is coupled to the memory element 502 by way of the bitline 504.
  • a third FET 512, a fourth FET 514 and a current source (Imax) 516 are connected in series to bias a gate terminal of the FET 510 such that the program current (Ipmg) does not exceed the maximum current (Imax).
  • the FETs 510 and 512 are connected to form a current mirror circuit for a maximum reference current (Imax).
  • the memory device 500 also includes a FET 518, a current source (Is) 520 and a node 522.
  • the FET 518 has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET 508 and a drain terminal connected to the node 522.
  • the FETs 508 and 510 provide another current mirror used to compare the program current (Ipmg) with a sense reference current (Is).
  • the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET 508 is mirrored to the FET 518.
  • the node 522 can determine whether the program current (Ipmg) exceeds the sense reference current (Is).
  • FIG. 6 is a schematic diagram of a memory device 600 according to another embodiment of the invention.
  • the memory device 600 illustrated in FIG. 6 provides separate circuitry for monitoring programming and limiting program current.
  • the memory device 600 utilizes a current mirror and a replicated memory element current path.
  • the memory device 600 includes a memory element 602.
  • the memory element 602 is coupled between a bitline 604 and a wordline 606.
  • the memory device 600 operates, in one mode, to program the memory element 602 by applying a voltage across the memory element 602.
  • the result of the voltage across the memory element 602 is to effectuate programming of the memory element 602.
  • the program current (Ipmg) passing through the memory element 602 increases.
  • the level of the program current (Ipmg) can signal that the memory element 602 has been adequately programmed.
  • the memory device 600 includes a first FET 608 that couples to a voltage potential (Vp) suitable for programming.
  • the first FET 608 is utilized to provide the program current (Ipmg) that is used to program the memory element 602.
  • a source terminal of the FET 608 is coupled to the voltage potential (Vp) and a drain terminal of the FET 608 is coupled to the memory element 602 by way of the bitline 604.
  • a second FET 610 and a current source (Imax) 612 are connected in series.
  • a source terminal of the FET 610 is coupled to the voltage potential (Vp) and a drain terminal of the FET 610 is coupled to the current source (Imax) 612.
  • the gate terminals of the FETs 608 and 610 are connected together.
  • the FET 610 and the current source (Imax) 612 operate to bias a gate terminal of the FET 608 such that the program current (Ipmg) does not exceed the maximum current (Imax).
  • the FETs 608 and 610 are connected to form a current mirror circuit that operates to prevent the program current (Ipmg) from exceeding a maximum reference current (Imax).
  • the memory device 600 also includes a FET 614, a comparator 616 and a FET 518 to replicate the memory element current path.
  • the FETs 614 and 618 are connected in series between the voltage potential (Vp) and ground.
  • a node 615 is provided at the connection of the FETs 614 and 618.
  • the comparator 616 compares the voltage at the node 615 with the voltage at node 617, which is at the connection of the FET 608 and the memory element 602.
  • the output of the comparator 616 serves to bias the gate terminal of the FET 618 such that a monitored current (Im) is substantially the same (i.e., replicated) as the program current (Ipmg).
  • the memory device includes a FET 620 and current source (Is) 622.
  • the current source (Is) 622 is connected to the voltage potential (Vp) and to a node 624.
  • the FET 620 is connected between the node 622 and ground.
  • the gate of the FET 620 is connected to the gate of the FET 618 such that a mirrored monitored current (Im') is drawn from the node 624 by the FET 620.
  • the node 624 can determine whether the program current (Ipmg) exceeds the sense reference current (Is).
  • the program current (Ipmg) exceeds the sense reference current (Is) the node 622 is pulled low.
  • a program control circuit (not shown) understands that the programming of the memory element 602 has been completed. At this point, either immediately or following a predetermined delay, the program control circuit can disable further programming of the memory element 602.
  • FIG. 7 is a schematic diagram of a memory device 700 according to another embodiment of the invention.
  • the memory device 700 illustrated in FIG. 7 provides monitoring for both programming current and excessive current.
  • the memory device 700 includes a memory element 702.
  • the memory element 702 is coupled between a bitline 704 and a wordline 706.
  • the memory device 700 operates, in one mode, to program the memory element 702 by applying a voltage across the memory element 702.
  • the result of the voltage across the memory element 702 is to effectuate programming of the memory element 702.
  • the program current (Ipmg) passing through the memory element 702 increases.
  • the level of the program current (Ipmg) can signal that the memory element 702 has been adequately programmed.
  • the memory device 700 includes a first FET 708 that couples to a voltage potential (Vp) suitable for programming.
  • the first FET 708 is utilized to provide the program current (Ipmg) that is used to program the memory element 702.
  • a second FET 710 couples between the first FET 708 and the memory element 702.
  • the second FET 510 can be utilized to limit the amount of current that can flow through to the memory element 702.
  • the FET 710 can be controlled to limit the program current (Ipmg) to a maximum level.
  • a source terminal of the FET 708 is coupled to the voltage potential (Vp) and a drain terminal of the FET 708 is coupled to a drain terminal of the FET 710.
  • a source terminal of the FET 710 is coupled to the memory element 702 by way of the bitline 704.
  • the memory device 700 also includes a FET 712 and a current source (Is) 714 and a node 716.
  • the FET 712 has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET 708 and a drain terminal connected to the node 716.
  • the FETs 708 and 712 provide a first current mirror used to compare a mirrored program current (Ipmg') with a sense reference current (Is).
  • the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET 708 is mirrored to the FET 712.
  • the node 716 can determine whether the mirrored program current (Ipmg') exceeds the sense reference current (Is).
  • the program control circuit 718 When the mirrored program current (Ipmg') exceeds the sense reference current (Is), the node 716 is pulled high. When the node 716 is pulled high, a program control circuit 718 understands that the programming of the memory element 702 has been completed. At this point, either immediately or following a predetermined delay, the program control circuit 718 can disable further programming of the memory element 702 in any of a number of ways (including through use of the FET 710).
  • the memory device 700 also includes a FET 720 and a current source (Imax) 722 and a node 724.
  • the FET 720 has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET 708 and a drain terminal connected to the node 724.
  • the FETs 708 and 720 provide a second current mirror used to compare a mirrored program current (Ipmg") with a maximum current (Imax).
  • the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET 708 is mirrored to the FET 720.
  • the node 724 can determine whether the mirrored program current (Ipmg") exceeds the maximum current (Imax).
  • the current limit control 726 can disable further programming of the memory element 702. For example, as shown in FIG. 7, the current limit control 726 can supply a control signal (CTRL) to the gate of the FET 710 so that the program current (Ipmg) does not exceed the maximum current (Imax).
  • CTRL control signal
  • the limiting of the program current (Ipmg) is not directly provided in an analog domain as one or more other embodiments, but is instead provided by feedback control (e.g., in a digital domain) which has some inherent delay.
  • Two-terminal memory cells can be formed from polysilicon diodes, transition metal oxide (e.g., NiO) memory elements, and chalcogenide-based memory elements.
  • Two-terminal memory arrays can be formed in a compact manner when arranged into cross-point memory arrays. Additional details on some two-terminal memory cells are provided in the following papers which are hereby incorporated herein by reference: (i) Pirovano et al., "Electronic Switching in Phase-Change Memories," IEEE Transactions on Electronic Devices, Vol. 51 , No.
  • the invention is suitable for use with both single-level (binary) memories and multi-level (multi-state) memories.
  • multi-level memories each data storage element stores two or more bits of data.
  • operatively connected refers to direct or indirect electrical connection between electrical components.
  • the invention can further pertain to an electronic system that includes a memory system as discussed above.
  • a memory system is a system that includes at least a memory device that provides data storage.
  • Memory systems i.e., memory cards
  • the memory system is often removable from the electronic system so the stored digital data is portable.
  • the memory systems according to the invention can have a relatively small form factor and be used to store digital data for electronics products (e.g., consumer electronic products) that acquire data, such as cameras, hand-held or notebook computers, network cards, network appliances, set-top boxes, hand-held or other small media (e.g., audio) players/recorders (e.g., MP3 devices), personal digital assistants, mobile telephones, and medical monitors.
  • One advantage of the invention is that a programming current used to program a memory element (i.e., memory cell) is limited so as not exceed a maximum current. This serves to protect the memory element from potentially damaging high current levels, such as while programming the memory element or at other times.
  • Another advantage of the invention is that sensing current to monitor programming of a memory element can be provided separate from limiting programming current to a maximum current.
  • Still another advantage of the invention is that a higher programming voltage can be used for faster programming since the program current is otherwise limited to the maximum current.
  • Another advantage of the invention is that memory elements to be programmed can be pre-charged while protecting the memory elements from excessive currents.
  • programming time to program a memory element can be optimized.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne des circuits et des procédés améliorés pour programmer les cellules de mémoire d'un dispositif de mémoire. Les circuits et les procédés améliorés fonctionnent pour protéger les cellules de mémoire contre de l'énergie électrique qui pourrait potentiellement causer un dommage lorsque ladite énergie est imposée pendant une programmation des cellules de mémoire. En outre, les circuits et les procédés améliorés fonctionnent pour détecter le moment où la programmation des cellules de mémoire a été complétée. Les circuits et les procédés améliorés sont particulièrement utiles pour programmer des cellules de mémoire non volatile. Selon un mode de réalisation, le dispositif de mémoire concerne un produit de mémoire à semi-conducteurs, tel qu'une puce mémoire à semi-conducteurs ou une carte mémoire portable.
PCT/US2007/081916 2006-10-24 2007-10-19 Dispositif de mémoire et procédé pour protéger des cellules de mémoire pendant la programmation WO2008051835A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/552,441 2006-10-24
US11/552,441 US7589989B2 (en) 2006-10-24 2006-10-24 Method for protecting memory cells during programming
US11/552,426 2006-10-24
US11/552,426 US7391638B2 (en) 2006-10-24 2006-10-24 Memory device for protecting memory cells during programming

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WO2021178590A1 (fr) * 2020-03-06 2021-09-10 Qualcomm Incorporated Systèmes et procédés pour fournir une terminaison d'écriture pour des cellules de mémoire programmables une seule fois

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Publication number Priority date Publication date Assignee Title
WO2021178590A1 (fr) * 2020-03-06 2021-09-10 Qualcomm Incorporated Systèmes et procédés pour fournir une terminaison d'écriture pour des cellules de mémoire programmables une seule fois

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