WO2008048985A3 - Method of manufacturing integrated deep and shallow trench isolation structures - Google Patents

Method of manufacturing integrated deep and shallow trench isolation structures Download PDF

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Publication number
WO2008048985A3
WO2008048985A3 PCT/US2007/081592 US2007081592W WO2008048985A3 WO 2008048985 A3 WO2008048985 A3 WO 2008048985A3 US 2007081592 W US2007081592 W US 2007081592W WO 2008048985 A3 WO2008048985 A3 WO 2008048985A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
trench isolation
shallow trench
hard mask
isolation structures
Prior art date
Application number
PCT/US2007/081592
Other languages
French (fr)
Other versions
WO2008048985A2 (en
Inventor
Joerg Haussman
Christoph Dirnecker
Rupert Wagner
Original Assignee
Texas Instruments Inc
Joerg Haussman
Christoph Dirnecker
Rupert Wagner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102006048960.8A external-priority patent/DE102006048960B4/en
Application filed by Texas Instruments Inc, Joerg Haussman, Christoph Dirnecker, Rupert Wagner filed Critical Texas Instruments Inc
Publication of WO2008048985A2 publication Critical patent/WO2008048985A2/en
Publication of WO2008048985A3 publication Critical patent/WO2008048985A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack (10) having a plurality of layers formed on a substrate (11) such that the hard mask (16) is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.
PCT/US2007/081592 2006-10-17 2007-10-17 Method of manufacturing integrated deep and shallow trench isolation structures WO2008048985A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102006048960.8 2006-10-17
DE102006048960.8A DE102006048960B4 (en) 2006-10-17 2006-10-17 Method for producing insulation structures with integrated deep and shallow trenches
US11/873,062 US8088664B2 (en) 2006-10-17 2007-10-16 Method of manufacturing integrated deep and shallow trench isolation structures
US11/873,062 2007-10-16

Publications (2)

Publication Number Publication Date
WO2008048985A2 WO2008048985A2 (en) 2008-04-24
WO2008048985A3 true WO2008048985A3 (en) 2008-10-30

Family

ID=39314805

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/081592 WO2008048985A2 (en) 2006-10-17 2007-10-17 Method of manufacturing integrated deep and shallow trench isolation structures

Country Status (1)

Country Link
WO (1) WO2008048985A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102478764B (en) * 2010-11-30 2013-08-07 中芯国际集成电路制造(北京)有限公司 Dual graphing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020072197A1 (en) * 2000-07-25 2002-06-13 Samsung Electronics Co., Ltd. Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device using the same
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors
US20060134882A1 (en) * 2004-12-22 2006-06-22 Chartered Semiconductor Manufacturing Ltd. Method to improve device isolation via fabrication of deeper shallow trench isolation regions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020072197A1 (en) * 2000-07-25 2002-06-13 Samsung Electronics Co., Ltd. Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device using the same
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors
US20060134882A1 (en) * 2004-12-22 2006-06-22 Chartered Semiconductor Manufacturing Ltd. Method to improve device isolation via fabrication of deeper shallow trench isolation regions

Also Published As

Publication number Publication date
WO2008048985A2 (en) 2008-04-24

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