WO2008044828A1 - Single-electron logic transistor with dual gates operating at room temperature and the method thereof - Google Patents

Single-electron logic transistor with dual gates operating at room temperature and the method thereof Download PDF

Info

Publication number
WO2008044828A1
WO2008044828A1 PCT/KR2007/004384 KR2007004384W WO2008044828A1 WO 2008044828 A1 WO2008044828 A1 WO 2008044828A1 KR 2007004384 W KR2007004384 W KR 2007004384W WO 2008044828 A1 WO2008044828 A1 WO 2008044828A1
Authority
WO
WIPO (PCT)
Prior art keywords
electron
beam resist
resist pattern
photo
nano
Prior art date
Application number
PCT/KR2007/004384
Other languages
French (fr)
Inventor
Jung Bum Choi
Sang Jin Kim
Seong Jin Choi
Chang Keun Lee
Original Assignee
Chungbuk National University Industry-Academic Cooperation Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chungbuk National University Industry-Academic Cooperation Foundation filed Critical Chungbuk National University Industry-Academic Cooperation Foundation
Publication of WO2008044828A1 publication Critical patent/WO2008044828A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/125—Quantum wire structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Definitions

  • the present invention relates to a dual-gate single- electron logic transistor operating at room temperature and a method of manufacturing the same, and more particularly, to a dual-gate single-electron logic device operating at room temperature and a method of manufacturing the same, which defines a nano-wire region using a negative photo or electron- beam resist pattern and a positive photo or electron-beam resist pattern and forms dual -gates capable of controlling the potential of a quantum dot on the left and right sides of the nano-wire region through selective etching according to a height difference between the nano-wire region and a region having no nano-wire and a height difference between the negative photo or electron-beam resist pattern and a region having no negative photo or electron-beam resist pattern.
  • a single-electron transistor is a semiconductor device that processes 1-bit information using only a single-electron. That is, the single-electron transistor passes only a single electron through a quantum dot to process 1-bit information while a conventional semiconductor device passes hundreds of electrons through a channel to process 1-bit information. Accordingly, the single-electron transistor can remarkably reduce power consumption from a mili-watt level to a pico-watt level, increase an information processing speed and improve a degree of integration to higher than tera-bit grade.
  • the single-electron transistor has a quantum dot formed in a channel, and an electron tunnels the quantum dot to causes Coulomb oscillation.
  • the single-electron transistor has low power consumption because it controls only a single electron.
  • Typical methods of controlling the potential of the quantum dot of the single-electron transistor are divided into a method of forming a side gate on the same plane on which the quantum dot is formed and a method of forming a gate right on the quantum dot .
  • a conventional single-electron transistor has the following problems.
  • the conventional single-electron transistor has the advantage of low power consumption because it controls only a single electron
  • the conventional single-electron transistor requires another gate to control the potential of the quantum dot because the phase of Coulomb oscillation cannot be controlled with a single gate.
  • the method of forming a side gate has the advantage of simple process.
  • electrical capacitance coupling of the quantum dot and the gate is weak because the quantum dot and the gate are located apart from each other by tens to hundreds nm, and thus a high voltage should be applied in order to control the potential of the quantum dot. This increases power consumption.
  • the method of forming a gate right on the quantum dot can control the potential of the quantum dot even with a low voltage, it is difficult to align the gate with the quantum dot because the quantum dot is very small.
  • a method of manufacturing a dual-gate single-electron logic transistor operating at room temperature comprising the steps of: (a) etching a semiconductor layer laminated on an insulating layer formed on a substrate including multi-layered semiconductor layers and insulating layers each of which is formed between neighboring semiconductor layers to define a channel region; (b) forming an oxide layer on the channel region; (c) forming a negative photo or electron-beam resist pattern on the oxide layer; (d) coating a positive photo or electron-beam resist on the negative photo or electron-beam resist pattern and pattering the coated positive photo or electron-beam resist layer into a positive photo or electron-beam resist pattern perpendicular to the negative photo or electron-beam resist pattern; (e) etching portions of the oxide layer and the semiconductor layer, exposed by the positive photo or electron-beam resist pattern, to form a nano-wire region; (f) forming an oxide layer on both sides of the semiconductor layer to form a quantum dot in
  • the channel region is formed by etching the semiconductor layer using photolithography.
  • the negative photo or electron-beam resist pattern is made of an inorganic material .
  • the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern are formed using photolithography or electron-beam lithography.
  • the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern have widths of several to tens nm.
  • the size of the nano-wire region is determined by the widths of the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern.
  • the oxide layer is formed by thermal oxidation on both sides of the nano-wire region other than the negative photo or electron-beam resist pattern.
  • step (g) polysilicon is deposited on the negative photo or electron-beam resist pattern and patterned using photolithography to form the gate.
  • the positive photo or electron-beam resist layer is coated such that the portion of the positive photo or electron-beam resist layer, which is coated on the nano-wire region, is thinner than the portion of the positive photo or electron-beam resist layer, which is coated on a region other than the nano-wire region.
  • the etching process is selectively performed using a height difference between a region in which the nano-wire region and the negative photo or electron-beam resist pattern are formed and a region in which the nano-wire region and the negative photo or electron-beam resist pattern are not formed.
  • the present invention has the following advantages. Firstly, a side gate having a thickness of several nm is formed on the side of the quantum dot to increase electrical capacitance coupling, and thus the potential of the quantum dot can be controlled even with a low voltage to reduce power consumption. That is, capacitance coupling between the quantum dot and a control gate for controlling the potential of the quantum dot is increased to easily adjust the potential of the quantum dot using a low voltage to reduce power consumption of the single-electron transistor.
  • dual -gates are formed on both sides of the quantum dot through selective etching using a thickness difference between negative and positive photo or electron- beam resist patterns. Accordingly, the single-electron transistor can be easily manufactured.
  • the method of manufacturing a single-electron transistor according to the present invention can use the existing CMOS manufacturing process to form components other than the nano-wire region, and thus the operational function of a nano-size logic transistor can be improved and the manufacturing process can be simplified. Furthermore, since Coulomb oscillation of the single-electron transistor can be controlled through a control gate, the operational function of the single-electron transistor can be diversified.
  • FIGS. 1 through 9 are plan views showing a method of manufacturing a dual-gate single-electron transistor according to the present invention.
  • FIG. 10 is a cross-sectional view taken along the line 2- 2 of FIG. 1;
  • FIG. 11 is a cross-sectional view taken along the line 3- 3 Of FIG. 2;
  • FIG. 12 is a cross-sectional view taken along the line 4a-4a of FIG. 3 ;
  • FIG. 13 is a cross-sectional view taken along the line 4b-4b of FIG. 3 ;
  • FIG. 14 is a cross-sectional view taken along the line 5a-5a of FIG. 4 ;
  • FIG. 15 is a cross-sectional view taken along the line 5b-5b of FIG. 4 ;
  • FIG. 16 is a cross-sectional view taken along the line
  • FIG. 17 is a cross-sectional view taken along the line 6b-6b of FIG. 5 ;
  • FIG. 18 is a cross-sectional view taken along the line 7a-7a of FIG. 6;
  • FIG. 19 is a cross-sectional view taken along the line 7b-7b of FIG. 6 ;
  • FIG. 20 is a cross-sectional view taken along the line 8a-8a of FIG. 7;
  • FIG. 21 is a cross-sectional view taken along the line 8b-8b of FIG. 7;
  • FIG. 22 is a cross-sectional view taken along the line 9a- 9a of FIG. 8 ;
  • FIG. 23 is a cross-sectional view taken along the line 9b- 9b of FIG. 8 ;
  • FIG. 24 is a cross-sectional view taken along the line 1Oa-IOa of FIG. 9;
  • FIG. 25 is a cross-sectional view taken along the line lOb-lOb of FIG. 9.
  • FIGS. 1 through 9 are plan views showing a method of manufacturing a dual-gate single-electron transistor according to an embodiment of the present invention.
  • the method of manufacturing a dual-gate single-electron transistor according to the present invention uses a substrate including an insulating layer 11 formed between semiconductor layers 10. That is, the substrate includes multi-layered semiconductor layers 10 and insulating layers 11 each of which is formed between neighboring semiconductor layers.
  • FIGS. 1 through 9 illustrate only the insulating layer 11 and the semiconductor layer 10 formed thereon, and illustration of semiconductor layers and insulating layers formed under the insulating layer 11 is omitted.
  • FIG. 10 is a cross-sectional view of the channel region 10a, taken along the line 2-2 of FIG. 1.
  • an oxide layer 20 is formed on the overall surface of the semiconductor layer 10 through thermal oxidation or deposition. Specifically, the oxide layer 20 having a predetermined thickness is formed on the overall surface of the semiconductor layer 10 including the cannel region 10a, as shown in FIGS. 2 and 11.
  • the oxide layer 20 functions as a gate insulating layer.
  • an inorganic negative photo or electron-beam resist is coated on the oxide layer 20 to form a negative photo or electron-beam resist pattern 30.
  • a positive photo or electron-beam resist is coated on the negative photo or electron-beam resist pattern and then the coated positive photo or electron-beam resist layer is patterned into a positive photo or electron-beam resist pattern perpendicular to the negative photo or electron-beam resist pattern.
  • the negative photo or electron-beam resist pattern 30 is formed by photolithography or electron-beam lithography.
  • the negative photo or electron-beam resist pattern 30 has a width of several to tens nm, as shown in FIGS. 12 and 13.
  • a positive photo or electron-beam resist is coated on the substrate including the negative photo or electron-beam resist pattern 30 to form a positive photo or electron-beam resist pattern 40.
  • the positive photo or electron-beam resist pattern 40 is formed by photolithography or electron- beam lithography such that the positive photo or electron-beam resist pattern 40 is perpendicular to the negative photo or electron-beam resist pattern 30 and has the same width as that of the negative photo or electron-beam resist pattern 30.
  • the widths of the positive photo or electron-beam resist pattern 40 and the negative photo or electron-beam resist pattern can be controlled in order to adjust the size of a target nano line.
  • an oxide layer 60 is formed on both sides of the nano-wire region 50 to form a quantum dot in the nano-wire region 50.
  • the oxide layer 60 is formed on the channel region 10a so as to be connected with the oxide layer 20 of the nano- wire region 50 to form the quantum dot, as shown in FIG. 19.
  • the oxide layer 60 is formed through thermal oxidation, and the oxide layer is not formed on the inorganic negative photo or electron-beam resist pattern 30.
  • FIGS. 18 and 19 are cross- sectional views taken along the lines la-la and 7b-7b of FIG. 6.
  • polysilicon is deposited on the substrate and etched to form a gate 70.
  • the polysilicon is deposited on the substrate and patterned through photolithography to form the gate 70 on the negative photo or electron-beam resist pattern 30.
  • FIGS. 20 and 21 are cross-sectional view taken along the lines 8a-8a and 8b-8b of FIG. 7.
  • the substrate including the semiconductor layer 10 is coated with positive photo or electron-beam resist 40.
  • the coated positive photo or electron-beam resist 40 has different thicknesses at the nano line region, the negative photo or electron-beam resist pattern, and regions in which the nano-wire region and the negative photo or electron-beam resist pattern are not formed. That is, the positive photo or electron-beam resist layer 40 has a stepped portion corresponding to the thickness of the gate 70 in the region where the negative photo or electron- beam resist pattern is formed, as shown in FIG. 22, and has a stepped portion at the boundary of the nano-wire region and a region other than the nano-wire region, as shown in FIG. 23.
  • the gate is divided into two gates 70a and 70b.
  • the polysilicon layer forming the gate 70 is dry-etched to selectively expose the upper portion of the negative photo or electron-beam resist pattern 30 on which the polysilicon layer is formed with a relatively thin thickness. Accordingly, the polysilicon layer is divided into the two gates 70a and 70b, as shown in FIGS. 24 and 25.
  • an oxide layer is formed on the overall surface of the substrate including the two separated gates 70a and 70b, and then a gate is formed using a metal such that the gate covers the negative photo or electron-beam resist pattern to accomplish the dual-gate single-electron transistor according to the present invention.
  • the method of manufacturing a single-electron transistor employs the existing CMOS manufacturing process to form components of the single-electron transistor other than the nano-wire region.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention relates to a method of manufacturing a dual-gate single-electron logic device operating at room temperature, which defines a nano-wire region using a negative photo or electron-beam resist pattern and a positive photo or electron-beam resist pattern and forms dual -gates capable of controlling the potential of a quantum dot on the left and right sides of the nano-wire region through selective etching according to a height difference between the nano-wire region and a region having no nano line and a height difference between the negative photo or electron-beam resist pattern and a region having no negative photo or electron-beam resist pattern.

Description

SINGLE-ELECTRON LOGIC TRANSISTOR WITH DUAL GATES OPERATING AT ROOM TEMPERATURE AND THE METHOD THEREOF
Technical Field
The present invention relates to a dual-gate single- electron logic transistor operating at room temperature and a method of manufacturing the same, and more particularly, to a dual-gate single-electron logic device operating at room temperature and a method of manufacturing the same, which defines a nano-wire region using a negative photo or electron- beam resist pattern and a positive photo or electron-beam resist pattern and forms dual -gates capable of controlling the potential of a quantum dot on the left and right sides of the nano-wire region through selective etching according to a height difference between the nano-wire region and a region having no nano-wire and a height difference between the negative photo or electron-beam resist pattern and a region having no negative photo or electron-beam resist pattern.
Background Art
A single-electron transistor is a semiconductor device that processes 1-bit information using only a single-electron. That is, the single-electron transistor passes only a single electron through a quantum dot to process 1-bit information while a conventional semiconductor device passes hundreds of electrons through a channel to process 1-bit information. Accordingly, the single-electron transistor can remarkably reduce power consumption from a mili-watt level to a pico-watt level, increase an information processing speed and improve a degree of integration to higher than tera-bit grade.
The single-electron transistor has a quantum dot formed in a channel, and an electron tunnels the quantum dot to causes Coulomb oscillation. The single-electron transistor has low power consumption because it controls only a single electron.
Typical methods of controlling the potential of the quantum dot of the single-electron transistor are divided into a method of forming a side gate on the same plane on which the quantum dot is formed and a method of forming a gate right on the quantum dot .
Disclosure of Invention Technical Problem
However, a conventional single-electron transistor has the following problems.
Although the conventional single-electron transistor has the advantage of low power consumption because it controls only a single electron, the conventional single-electron transistor requires another gate to control the potential of the quantum dot because the phase of Coulomb oscillation cannot be controlled with a single gate. Furthermore, the method of forming a side gate has the advantage of simple process. However, electrical capacitance coupling of the quantum dot and the gate is weak because the quantum dot and the gate are located apart from each other by tens to hundreds nm, and thus a high voltage should be applied in order to control the potential of the quantum dot. This increases power consumption. Moreover, although the method of forming a gate right on the quantum dot can control the potential of the quantum dot even with a low voltage, it is difficult to align the gate with the quantum dot because the quantum dot is very small.
Technical Solution
To solve the aforementioned problems, there is provided a method of manufacturing a dual-gate single-electron logic transistor operating at room temperature, the method comprising the steps of: (a) etching a semiconductor layer laminated on an insulating layer formed on a substrate including multi-layered semiconductor layers and insulating layers each of which is formed between neighboring semiconductor layers to define a channel region; (b) forming an oxide layer on the channel region; (c) forming a negative photo or electron-beam resist pattern on the oxide layer; (d) coating a positive photo or electron-beam resist on the negative photo or electron-beam resist pattern and pattering the coated positive photo or electron-beam resist layer into a positive photo or electron-beam resist pattern perpendicular to the negative photo or electron-beam resist pattern; (e) etching portions of the oxide layer and the semiconductor layer, exposed by the positive photo or electron-beam resist pattern, to form a nano-wire region; (f) forming an oxide layer on both sides of the semiconductor layer to form a quantum dot in the nano-wire region; (g) forming a gate on the negative photo or electron-beam resist pattern; (h) coating a positive photo or electron-beam resist on the overall surface of the semiconductor layer using a spin coating method; (i) performing an etching process to expose the negative photo or electron-beam resist pattern so as to divide the gate into two gates having the negative photo or electron-beam resist pattern between them; and (j) forming an oxide layer and forming a gate using a metal to cover the whole negative photo or electron-beam resist pattern.
The channel region is formed by etching the semiconductor layer using photolithography.
The negative photo or electron-beam resist pattern is made of an inorganic material .
The negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern are formed using photolithography or electron-beam lithography.
The negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern have widths of several to tens nm.
The size of the nano-wire region is determined by the widths of the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern. In the step (f) , the oxide layer is formed by thermal oxidation on both sides of the nano-wire region other than the negative photo or electron-beam resist pattern.
In the step (g) , polysilicon is deposited on the negative photo or electron-beam resist pattern and patterned using photolithography to form the gate.
In the step (h) , the positive photo or electron-beam resist layer is coated such that the portion of the positive photo or electron-beam resist layer, which is coated on the nano-wire region, is thinner than the portion of the positive photo or electron-beam resist layer, which is coated on a region other than the nano-wire region.
In the step (i) , the etching process is selectively performed using a height difference between a region in which the nano-wire region and the negative photo or electron-beam resist pattern are formed and a region in which the nano-wire region and the negative photo or electron-beam resist pattern are not formed.
There is also provided a dual-gate single-electron logic transistor operating at room temperature, which is manufactured by the aforementioned manufacturing method.
Advantageous Effects
The present invention has the following advantages. Firstly, a side gate having a thickness of several nm is formed on the side of the quantum dot to increase electrical capacitance coupling, and thus the potential of the quantum dot can be controlled even with a low voltage to reduce power consumption. That is, capacitance coupling between the quantum dot and a control gate for controlling the potential of the quantum dot is increased to easily adjust the potential of the quantum dot using a low voltage to reduce power consumption of the single-electron transistor.
Furthermore, dual -gates are formed on both sides of the quantum dot through selective etching using a thickness difference between negative and positive photo or electron- beam resist patterns. Accordingly, the single-electron transistor can be easily manufactured.
Moreover, the method of manufacturing a single-electron transistor according to the present invention can use the existing CMOS manufacturing process to form components other than the nano-wire region, and thus the operational function of a nano-size logic transistor can be improved and the manufacturing process can be simplified. Furthermore, since Coulomb oscillation of the single-electron transistor can be controlled through a control gate, the operational function of the single-electron transistor can be diversified.
Description of the Drawings
Further objects and advantages of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIGS. 1 through 9 are plan views showing a method of manufacturing a dual-gate single-electron transistor according to the present invention;
FIG. 10 is a cross-sectional view taken along the line 2- 2 of FIG. 1;
FIG. 11 is a cross-sectional view taken along the line 3- 3 Of FIG. 2;
FIG. 12 is a cross-sectional view taken along the line 4a-4a of FIG. 3 ;
FIG. 13 is a cross-sectional view taken along the line 4b-4b of FIG. 3 ; FIG. 14 is a cross-sectional view taken along the line 5a-5a of FIG. 4 ;
FIG. 15 is a cross-sectional view taken along the line 5b-5b of FIG. 4 ;
FIG. 16 is a cross-sectional view taken along the line FIG. 17 is a cross-sectional view taken along the line 6b-6b of FIG. 5 ;
FIG. 18 is a cross-sectional view taken along the line 7a-7a of FIG. 6; FIG. 19 is a cross-sectional view taken along the line 7b-7b of FIG. 6 ;
FIG. 20 is a cross-sectional view taken along the line 8a-8a of FIG. 7;
FIG. 21 is a cross-sectional view taken along the line 8b-8b of FIG. 7;
FIG. 22 is a cross-sectional view taken along the line 9a- 9a of FIG. 8 ;
FIG. 23 is a cross-sectional view taken along the line 9b- 9b of FIG. 8 ; FIG. 24 is a cross-sectional view taken along the line 1Oa-IOa of FIG. 9; and
FIG. 25 is a cross-sectional view taken along the line lOb-lOb of FIG. 9.
Mode for Invention
The configuration and operation of the present invention will be explained with reference to the attached drawings.
FIGS. 1 through 9 are plan views showing a method of manufacturing a dual-gate single-electron transistor according to an embodiment of the present invention.
The method of manufacturing a dual-gate single-electron transistor according to the present invention uses a substrate including an insulating layer 11 formed between semiconductor layers 10. That is, the substrate includes multi-layered semiconductor layers 10 and insulating layers 11 each of which is formed between neighboring semiconductor layers. FIGS. 1 through 9 illustrate only the insulating layer 11 and the semiconductor layer 10 formed thereon, and illustration of semiconductor layers and insulating layers formed under the insulating layer 11 is omitted.
The semiconductor layer 10 formed on the insulating layer 11 is selectively etched to form a channel region 10a. In a preferred embodiment of the present invention, the channel region 10a has an "H" shape. In this step, a portion of the semiconductor layer 10 other than an active layer is removed using photolithography. FIG. 10 is a cross-sectional view of the channel region 10a, taken along the line 2-2 of FIG. 1.
Subsequently, an oxide layer 20 is formed on the overall surface of the semiconductor layer 10 through thermal oxidation or deposition. Specifically, the oxide layer 20 having a predetermined thickness is formed on the overall surface of the semiconductor layer 10 including the cannel region 10a, as shown in FIGS. 2 and 11. The oxide layer 20 functions as a gate insulating layer.
Referring to FIG. 3, an inorganic negative photo or electron-beam resist is coated on the oxide layer 20 to form a negative photo or electron-beam resist pattern 30. A positive photo or electron-beam resist is coated on the negative photo or electron-beam resist pattern and then the coated positive photo or electron-beam resist layer is patterned into a positive photo or electron-beam resist pattern perpendicular to the negative photo or electron-beam resist pattern. The negative photo or electron-beam resist pattern 30 is formed by photolithography or electron-beam lithography. The negative photo or electron-beam resist pattern 30 has a width of several to tens nm, as shown in FIGS. 12 and 13.
Subsequently, a positive photo or electron-beam resist is coated on the substrate including the negative photo or electron-beam resist pattern 30 to form a positive photo or electron-beam resist pattern 40. In a preferred embodiment of the present invention, the positive photo or electron-beam resist pattern 40 is formed by photolithography or electron- beam lithography such that the positive photo or electron-beam resist pattern 40 is perpendicular to the negative photo or electron-beam resist pattern 30 and has the same width as that of the negative photo or electron-beam resist pattern 30. However, the widths of the positive photo or electron-beam resist pattern 40 and the negative photo or electron-beam resist pattern can be controlled in order to adjust the size of a target nano line.
A portion of the positive photo or electron-beam resist pattern 40, which intersects the negative photo or electron- beam resist 30, is opened in the width direction of the negative photo or electron-beam resist pattern 30, as shown in FIGS. 4 and 14. Furthermore, the positive photo or electron- beam resist pattern 40 is formed apart from both sides of the negative photo or electron-beam resist pattern 30 by a predetermined distance, as shown in FIG. 15. Referring to FIG. 5, a nano-wire region 50 is formed by etching portions of the oxide layer 20, the semiconductor layer 10 and the channel region 10a, which are exposed by the positive photo or electron-beam resist pattern 40. Accordingly, the nano-wire region 50 is defined by the width of the negative photo or electron-beam resist pattern 30 and the length of the positive photo or electron-beam resist pattern 40 in the channel region defined by the etching process, as shown in FIGS. 16 and 17.
Then, an oxide layer 60 is formed on both sides of the nano-wire region 50 to form a quantum dot in the nano-wire region 50. The oxide layer 60 is formed on the channel region 10a so as to be connected with the oxide layer 20 of the nano- wire region 50 to form the quantum dot, as shown in FIG. 19. In a preferred embodiment of the present invention, the oxide layer 60 is formed through thermal oxidation, and the oxide layer is not formed on the inorganic negative photo or electron-beam resist pattern 30. FIGS. 18 and 19 are cross- sectional views taken along the lines la-la and 7b-7b of FIG. 6. Subsequently, polysilicon is deposited on the substrate and etched to form a gate 70. In a preferred embodiment of the present invention, the polysilicon is deposited on the substrate and patterned through photolithography to form the gate 70 on the negative photo or electron-beam resist pattern 30. FIGS. 20 and 21 are cross-sectional view taken along the lines 8a-8a and 8b-8b of FIG. 7.
Referring to FIG. 8, the substrate including the semiconductor layer 10 is coated with positive photo or electron-beam resist 40. Here, the coated positive photo or electron-beam resist 40 has different thicknesses at the nano line region, the negative photo or electron-beam resist pattern, and regions in which the nano-wire region and the negative photo or electron-beam resist pattern are not formed. That is, the positive photo or electron-beam resist layer 40 has a stepped portion corresponding to the thickness of the gate 70 in the region where the negative photo or electron- beam resist pattern is formed, as shown in FIG. 22, and has a stepped portion at the boundary of the nano-wire region and a region other than the nano-wire region, as shown in FIG. 23. Referring to FIG. 9, the gate is divided into two gates 70a and 70b. Specifically, the polysilicon layer forming the gate 70 is dry-etched to selectively expose the upper portion of the negative photo or electron-beam resist pattern 30 on which the polysilicon layer is formed with a relatively thin thickness. Accordingly, the polysilicon layer is divided into the two gates 70a and 70b, as shown in FIGS. 24 and 25.
Subsequently, an oxide layer is formed on the overall surface of the substrate including the two separated gates 70a and 70b, and then a gate is formed using a metal such that the gate covers the negative photo or electron-beam resist pattern to accomplish the dual-gate single-electron transistor according to the present invention.
In a preferred embodiment of the present invention, the method of manufacturing a single-electron transistor employs the existing CMOS manufacturing process to form components of the single-electron transistor other than the nano-wire region.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A method of manufacturing a dual-gate single-electron logic transistor operating at room temperature, the method comprising the steps of:
(a) etching a semiconductor layer laminated on an insulating layer formed on a substrate including multi-layered semiconductor layers and insulating layers each of which is formed between neighboring semiconductor layers to define a channel region;
(b) forming an oxide layer on the channel region;
(c) forming a negative photo or electron-beam resist pattern on the oxide layer;
(d) coating a positive photo or electron-beam resist on the negative photo or electron-beam resist pattern and pattering the coated positive photo or electron-beam resist layer into a positive photo or electron-beam resist pattern perpendicular to the negative photo or electron-beam resist pattern; (e) etching portions of the oxide layer and the semiconductor layer, exposed by the positive photo or electron-beam resist pattern, to form a nano-wire region;
(f) forming an oxide layer on both sides of the semiconductor layer to form a quantum dot in the nano-wire region;
(g) forming a gate on the negative photo or electron-beam resist pattern;
(h) coating a positive photo or electron-beam resist on the overall surface of the semiconductor layer using a spin coating method;
(i) performing an etching process to expose the negative photo or electron-beam resist pattern so as to divide the gate into two gates having the negative photo or electron-beam resist pattern between them,- and
(j) forming an oxide layer and forming a gate using a metal to cover the whole negative photo or electron-beam resist pattern.
2. The method according to claim 1, wherein the channel region is formed by etching the semiconductor layer using photolithography.
3. The method according to claim 1, wherein the oxide layer is formed through thermal oxidation or deposition in the step (b) .
4. The method according to claim 1, wherein the negative photo or electron-beam resist pattern is made of an inorganic material .
5. The method according to claim 1, wherein the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern are formed using photolithography or electron beam lithography.
6. The method according to claim 1 or 5, wherein the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern have widths of several to tens nm.
7. The method according to claim 1, wherein the size of the nano-wire region is determined by the widths of the negative photo or electron-beam resist pattern and the positive photo or electron-beam resist pattern.
8. The method according to claim 1, wherein the oxide layer is formed by thermal oxidation on both sides of the nano-wire region other than the negative photo or electron- beam resist pattern in the step (f) .
9. The method according to claim 1, wherein polysilicon is deposited on the negative photo or electron-beam resist pattern and patterned using photolithography to form the gate in the step (g) .
10. The method according to claim 1, wherein the positive photo or electron-beam resist layer is coated such that the portion of the positive photo or electron-beam resist layer, which is coated on the nano-wire region, is thinner than the portion of the positive photo or electron-beam resist layer, which is coated on a region other than the nano-wire region in the step (h) .
11. The method according to claim 1, wherein the gate is divided into the two gates using dry etching in the step (i) .
12. The method according to claim 1 or 11, wherein the etching process is selectively performed using a height difference between a region in which the nano-wire region and the negative photo or electron-beam resist pattern are formed and a region in which the nano-wire region and the negative photo or electron-beam resist pattern are not formed.
13. A dual-gate single-electron logic transistor operating at room temperature, which is manufactured by the method according to any one of claims 1 to 12.
PCT/KR2007/004384 2006-10-10 2007-09-11 Single-electron logic transistor with dual gates operating at room temperature and the method thereof WO2008044828A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060098330A KR100905869B1 (en) 2006-10-10 2006-10-10 Method for preparing Single-Electron Logic Transistor with Dual Gates operating at Room Temperature
KR10-2006-0098330 2006-10-10

Publications (1)

Publication Number Publication Date
WO2008044828A1 true WO2008044828A1 (en) 2008-04-17

Family

ID=39283002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2007/004384 WO2008044828A1 (en) 2006-10-10 2007-09-11 Single-electron logic transistor with dual gates operating at room temperature and the method thereof

Country Status (2)

Country Link
KR (1) KR100905869B1 (en)
WO (1) WO2008044828A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816479B2 (en) 2008-06-17 2014-08-26 National Research Council Of Canada Atomistic quantum dot
WO2019081837A1 (en) * 2017-10-26 2019-05-02 Commissariat A L'Énergie Atomique Et Aux Energies Alternatives Method for producing an electronic component with double quantum dots

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731598A (en) * 1995-06-23 1998-03-24 Matsushita Electric Industrial Co. Ltd. Single electron tunnel device and method for fabricating the same
US6335245B2 (en) * 1999-04-02 2002-01-01 Hyundai Electronics Industries Co., Ltd. Method for fabricating single electron transistor
US6597036B1 (en) * 2000-04-15 2003-07-22 Samsung Electronics Co., Ltd. Multi-value single electron memory using double-quantum dot and driving method thereof
US6894352B2 (en) * 2002-07-04 2005-05-17 Shu-Fen Hu Single-electron transistor and fabrication method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000138371A (en) 1998-10-30 2000-05-16 Toyota Central Res & Dev Lab Inc Semiconductor device
KR20020090068A (en) * 2001-05-24 2002-11-30 최중범 Method of manufacturing a silicon-based single electron transistor logic device.
WO2003083949A1 (en) 2002-03-28 2003-10-09 Koninklijke Philips Electronics N.V. Nanowire and electronic device
KR20050081124A (en) * 2004-02-11 2005-08-18 최중범 Silicon dual gate structure single electron nano device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731598A (en) * 1995-06-23 1998-03-24 Matsushita Electric Industrial Co. Ltd. Single electron tunnel device and method for fabricating the same
US6335245B2 (en) * 1999-04-02 2002-01-01 Hyundai Electronics Industries Co., Ltd. Method for fabricating single electron transistor
US6597036B1 (en) * 2000-04-15 2003-07-22 Samsung Electronics Co., Ltd. Multi-value single electron memory using double-quantum dot and driving method thereof
US6894352B2 (en) * 2002-07-04 2005-05-17 Shu-Fen Hu Single-electron transistor and fabrication method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816479B2 (en) 2008-06-17 2014-08-26 National Research Council Of Canada Atomistic quantum dot
US9213945B2 (en) 2008-06-17 2015-12-15 National Research Council Of Canada Method for controlling quantum dot device by perturbing dangling bond electronic states
US9400957B2 (en) 2008-06-17 2016-07-26 National Research Council Of Canada Method for quantum computation by perturbing dangling bond electronic states
US9704101B2 (en) 2008-06-17 2017-07-11 National Research Council Of Canada Method for operating an electronic state device by perturbating dangling bond electronic states
WO2019081837A1 (en) * 2017-10-26 2019-05-02 Commissariat A L'Énergie Atomique Et Aux Energies Alternatives Method for producing an electronic component with double quantum dots
FR3073079A1 (en) * 2017-10-26 2019-05-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT WITH DOUBLE QUANTUM BOXES
US11398593B2 (en) 2017-10-26 2022-07-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing an electronic component with double quantum dots

Also Published As

Publication number Publication date
KR20080032465A (en) 2008-04-15
KR100905869B1 (en) 2009-07-03

Similar Documents

Publication Publication Date Title
KR100923193B1 (en) Nanoscale Multi-junction Quantum Dot Device and Fabrication Method thereof
US8022393B2 (en) Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US7462917B2 (en) Semiconductor device and method of fabricating the same
KR100521433B1 (en) Method for forming Silicon quantum dot and the method for fabricating semiconductor memory device using the same
US20070051942A1 (en) Etch masks based on template-assembled nanoclusters
WO2008044828A1 (en) Single-electron logic transistor with dual gates operating at room temperature and the method thereof
KR100602084B1 (en) Method for forming Silicon quantum dot and the method for fabricating semiconductor memory device using the same
CN107946354A (en) A kind of SOI FinFETs of anti-integral dose radiation and preparation method thereof
KR100418182B1 (en) Method for manufacturing a silicon single electron transistor memory device
KR20090028360A (en) Fabrication method for room temperature operating single-electron device
US20110294296A1 (en) Using edges of self-assembled monolayers to form narrow features
KR100796281B1 (en) Spin Dependent Single Electron Transistor
KR101036692B1 (en) Multi Quantum dot Nano Device and Fabrication Method thereof
JP3175666B2 (en) Method for manufacturing semiconductor device
US8164118B2 (en) Semiconductor device and its manufacturing method
JPH09246536A (en) Semiconductor element
US20200343435A1 (en) Method for producing an electronic component with double quantum dots
US6074936A (en) Method of fabricating a quantum device
KR100347673B1 (en) Method of fabricating single electron device
KR101050875B1 (en) Manufacturing method of single electron nano device and accordingly single electron nano device
KR101012265B1 (en) Fabrication method of room temperature-operating Single-Electron Device
KR20050103821A (en) Fabrication method of single electron transistor using oxidation
KR20190020547A (en) Meteal structure for forming skyrmion and method therefor
KR20040102480A (en) Self-assembled monolayer field-effect transistors and methods of manufacturing the same
KR100346778B1 (en) Fabrication method for multi-junction single electron transistor by metal evaporation

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07808176

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07808176

Country of ref document: EP

Kind code of ref document: A1