WO2008041974A2 - Unité de microcontrôleur (mcu) avec mode de suspension - Google Patents

Unité de microcontrôleur (mcu) avec mode de suspension Download PDF

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Publication number
WO2008041974A2
WO2008041974A2 PCT/US2006/038301 US2006038301W WO2008041974A2 WO 2008041974 A2 WO2008041974 A2 WO 2008041974A2 US 2006038301 W US2006038301 W US 2006038301W WO 2008041974 A2 WO2008041974 A2 WO 2008041974A2
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WO
WIPO (PCT)
Prior art keywords
clock signal
external clock
circuit
signal
microcontroller unit
Prior art date
Application number
PCT/US2006/038301
Other languages
English (en)
Other versions
WO2008041974A3 (fr
Inventor
Kafai Leung
Tao Yonghong
Original Assignee
Kafai Leung
Tao Yonghong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kafai Leung, Tao Yonghong filed Critical Kafai Leung
Priority to PCT/US2006/038301 priority Critical patent/WO2008041974A2/fr
Priority to US11/694,619 priority patent/US7536570B2/en
Publication of WO2008041974A2 publication Critical patent/WO2008041974A2/fr
Publication of WO2008041974A3 publication Critical patent/WO2008041974A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to suspend mode operations of microcontroller units, and more particularly, to a microcontroller unit having a suspend mode that operates off of an external clock signal.
  • SOC system-on- a-chip
  • MCUs microcontroller units
  • the analog section typically includes an analog-to-digital converter that may have the input thereof multiplexed such that it can sample analog values from a plurality of different sources, such as various sensors or transducers.
  • MCUs are designed to operate on very low power, such that they can be disposed in remote areas and then run off of " battery power for long durations of time. Since sampling of data is a rather intermittent operation, it is advantageous for these devices to have the ability to enter into a low power operating mode.
  • the power budget for these types of MCU chips is divided among a number of functional elements.
  • the processor On the digital side, the processor lias a large number of gates and typically requires a relatively high frequency of operation to provide adequate capabilities, on the order of 25 MHz.
  • timers, Input/Output (FO) devices, etc. There also a plurality of timers, Input/Output (FO) devices, etc., but the largest portion of the power " budget is the processor.
  • the clock circuitry can also take up a fair portion of the power budget, even when not driving the processor, " but the primary portion of the power budget due to the power requirement of the digital processing and the clock speed thereof.
  • MCUs have clock speeds ranging from 25 MHz to 100 MHz. Even if the processor is not processing information, the clock is still clocking the chip at a relatively high frequency and, as long as gates are being driven to different states, power will be dissipated. Therefore, most of these MCU devices have a low power operating mode wMch allows the processor or a digital portion thereof to be placed into a very "deep sleep" mode by halting the processing operation or just allow a lower power mode. In the lower -power mode, it is sometimes necessary to lower the clock speed down to a low clock operating speed of, for example, 32 kHz. This can allow the processor to continue operating, but at a much lower speed.
  • ADCs analog-to-digital converters
  • DACs digital-to- analog converters
  • the lowest power operation is to place the digital portion in a deep sleep mode wherein the processing operation is substantially terminated, with the configuration information for the "current state" of the processor maintained.
  • An external monitoring circuit will monitor some conditions such as an interrupt generated " by another block, an external event, etc., and will then wake up the part and initiate processing at the last current state.
  • a real time clock function is required. This is easily facilitated in the MCU running at the nigh speed, since there are typically provided timers and the such on-board that can be clocked by a high frequency clock.
  • One type of MCU that provides for this is the family of MCU products, C8051FXXX, manufactured by Silicon Laboratories Inc.
  • the count must be segmented, or perceived in some way such that it can count seconds, minutes, hours, days, etc. and stored in a register.
  • the entire real time clock function could be carried out in the background with a low frequency clock.
  • a high frequency clock for operating the processor in the default operating mode -which is the high power operating mode and a low frequency clock for operating the processor in the low power mode.
  • a low frequency clock can ⁇ be utilized to clock the timers independent of the operation of the processor and to generate interrupts.
  • the functionality of the xeal time clock basically takes advantage of the operation of the entire digital section. As such, in very low power applications wherein it is desirable to have time- stamp information on samples that are taken, the real time clock and the entire digital section must be run during the very low power mode. Therefore, it would be desirable to nave none or very little of the digital section operating during this time. Additionally, it would ⁇ be beneficial if the circuit could operate in the low power applications using an external clock signal without the use of an internal ⁇ eal time clock to completely eliminate the power requirements of the internal ⁇ eal time clock.
  • the present invention disclosed and claimed herein in one aspect thereof, comprises a microcontroller unit having a suspend mode of operation.
  • a processing circuit within the microcontroller unit receives digital information and processes the digital information.
  • Timing circuitry generates timing signals to the processing circuit responsive to received clock signals.
  • a clock circuit generates a synchronized external clock signal and an external clock signal for providing the timing to the timing circuit.
  • a circuit for selectively applying the synchronized external and external clock signals to the timing circuitry applies the synchronized external clock signal to the tuning circuitry in an active mode of operation responsive to at least one first control signal.
  • the circuitry also applies the external clock signal to the timing circuitry in at least a suspended mode of the operation of the microcontroller unit responsive to a suspend control signal.
  • Fig. 1 illustrates an overall diagram view of an MCU that may operate in a low power mode without a real time clock
  • Fig. 2 more particularly illustrates the configuration of the circuitry enabling operation of an
  • Fig. 3 illustrates the synchronization circuit for synchronizing external and internal oscillator clock signals
  • Fig. 4 illustrates the process for switching between the internal and external clock signals
  • Fig. 5 illustrates the circuitry for switching between the internal and external clock signals
  • Fig. 6 illustrates the gated clock system for preventing clock glitch when switching between the external and internal clock signals
  • Fig. 7 illustrates an overall block diagram of the MCU chip showing the various functional blocks thereof.
  • Fig. 8 illustrates a block diagram of the oscillators utilized for the processing operation of the
  • Fig. 1 there is illustrated a block diagram of a processor based system that drives the mixed signal technologies that includes as a part thereof, a digital section including a central processing unit 102 and a digital I/O section 104 that is operable to interface with various serial inputs and outputs.
  • the system also includes the analog section wMch provides to an analog-to-digital converter (ADC) 106 that is operable to receive one or more analog inputs and also provides a digital-to-analog converter (DAC) 110 for allowing digital information from the CPU 102 to be converted to analog output information.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the operation of the CPU 102 is controlled by various clocks 112 in a primary oscillator section. These are the operational clocks that control the overall operation of the MCU.
  • the clock section 112 may provide both " internal and external clocks for operation of the CPU 102. Switching between these clock signals may be controlled by a multiplexer 142 under the control of a MCU multiplexer switch control circuit 116 providing control signals to the multiplexer 142 over control line 140.
  • the MCU multiplexer switch control circuit 116 provides the internal clock signal to the CPU 102 during the active mode of operation and can provide the external clock signal to the CPU 102 during the mode of operation.
  • the clocks 112 also provide clock signals to timer 118 through a multiplexer 144.
  • the timer 118 provides timing information to the MCU 102 in both active and suspend modes of operation, and acts a general purpose timer for peripheral devices. During the suspend mode of operation, the timer 118 will operate under control of the external clocks rather than the internal clocks which will be powered down to conserve system power. During the active mode of operation, the timer 118 will operate under control of an external clock signal synchronized with the internal clock signal or under the internal clock signal.
  • the timer 118 contain current time and date-information therein separate and independent of the operation of the digital and analog sections and the power required or provided thereto. This information can be utilized by the CPU 102.
  • the timer 118 will update its internal time and date information.
  • the timer 118 is operable to generate an interrupt on interrupt line 132 to the CPU 102. As will be described herein below, this interrupt facilitates waking up the CPU 102 when it is placed into idle mode. However, the CPU 102 at any time can query the timer 118 for information stored therein.
  • the clock circuit 112 includes an internal clock which is operable to generate a base frequency of around 25 Mhz that cant>e multiplied or divided.
  • the external clocks may provide external frequencies of around 32 Khz for an alternative low frequency time base for the system clock. This will allow the CPU 102 to operate at a low frequency for power conservation purposes during an active mode.
  • the clock signals are gated to the multiplexer 144 through a gate 146 connected to the internal clock signal and a gate 148 connected to the external clock signal.
  • the multiplexer 144 and the gates 146,148 are under the control of the timer multiplexer controller 150.
  • the controller 150 causes the multiplexer to switch between the clock signals depending on the mode of operation and controls the gating of signals onto the multiplexer 144 through gates 146,148 to prevent clock glitch problems.
  • the internal and external clock signals are provided to the clock multiplexer 144.
  • the internal clock is provided to the clock multiplexer 144 via input line 202.
  • the external clock signals are provided to the clock multiplexer via line 204.
  • the internal and external clock signals are provided to a synchronization circuit 206 to enable synchronization of the internal and external clock signals with each other during switching between the clock signals.
  • the external oscillator signal is completely asynchronous with the internal circuits of the microcontroller unit 102 which are Tunning on the internal oscillator during the normal mode of operation. If the timer circuit 118 uses the external clock signal as a direct clock source, the timer 118 and MCU 102 will he running asynchronously. This is not an optimal situation for the analog circuits associated with the MCU 102 due to noise management reasons. Additionally, communication between the timer 118 and other circuits would not be reliable due to possible signal glitches. All of the signals crossing clock domains have to be synchronized to avoid glitches. The chip size will increase because of the number of synchronization circuits needed as there are many signals crossing various clock domains.
  • the present circuit synchronizes the external clock signal with the internal clock signal using synchronization circuit 206.
  • the timer 118 uses the external clock signal during a wake up mode from the suspended mode of operation, the actual clock signal to the timer 118 is a synchronous external clock signal that has been synchronized with the external clock via the sync circuit 206.
  • the key to glitch free clock switching is to make sure that both the "original" clock and “new” clock signals are “off' or at zero volts before any switching takes place. With the original clock being at zero volts, the switch must happen after the falling edge of the "new" clock signal. For example, to switch from the internal clock to the external clock when entering the suspend mode of operation, glitch free operation is guaranteed by generating a signal to gate off the internal clock signal and manage the multiplexer switch signal to change states after the falling edge of the external clock. Since both of the clock sources are at zero volts at the moment of switching, the multiplexing between the signals will be glitch free. The same theory is applied to a wake up condition when the clock source switches from the external clock signal back to the internal clock signal.
  • the multiplexer 144 selection signals provided from the switch control 116 always synchronize to the falling edge of the "new clock.” If the trigger of the suspend mode happens right before the counter (or timer) clock edge, the counter may miss an up-count. This is due to the internal oscillator being stopped immediately upon entering the suspend mode, while the clock source multiplexer is waiting for the falling edge of the external clock. The design ensures that there is no missing count caused by any switching. A check is done after the switch to make sure that the counter always has the correct value. [0019] The clock multiplexer 144 enables any of the clock signals on any of lines 202, 208 and 204 to " be applied to both the missing clock detect circuit 210 and the timer circuit 118.
  • the timer circuit 118 provides the timing control signals to the microcontroller unit 102 via an 8 bit bus 212. Additionally, the timer 118 can generate an RTC alarm to the MCU 102 and the internal clock source in circuit 112 via line 214 and various interrupts to the MCU via line 216.
  • the missing clock detect circuit 210 monitors the output line 218 of the clock multiplexer 142 to confirm that either the internal or external clock signal is being applied thereto based upon the modes of operation. If missing clock detect circuit 210 determines that no clock signal is present on output line 218 of clock multiplexer 144 a reset signal is generated to the microcontroller unit 102 on reset line 220. This enables a complete reset of the microcontroller unit 102 when lack of an applied clock signal would necessarily cause errors within the microcontroller unit 102 operation.
  • the switch control circuit 116 provides control signals to the clock multiplexer 144 via control line 222 to enable selection of one of the input lines 202, 204 or 208 depending on which clock signal is to be provided at a particular time as discussed previously.
  • the switch control circuitry 116 is responsive to input signals such as the comparator alarm, port match alarm, RTC alarm on various external inputs and the suspend signal on input line 224.
  • the switch control circuit 116 selects the internal clock signal or the synchronized external clock signal for provision to the timer 118, and thus, the clock signal on line 202 or line 208 is multiplexed onto output line 218 to the timer 118.
  • the switch control circuit 116 When the suspend signal on line 224 is applied to the switch control circuit 116 and the internal clock source in 112, the internal clock source stops at zero volts and the MCU operation is completely suspended.
  • the multiplexer 142 multiplexes the external clock signal after the falling edge on the external clock signal on line 204 onto output line 218 for provision to the timer 118. This enables the timer 118 to continue operating during the suspend mode without requiring the higher power requirements associated with the internal clock signal and MCU.
  • the switch control circuit 116 enables the clock multiplexer 144 to select between the internal and external clock signals depending upon whether or not the MCU 102 is operating in the suspended mode or normal mode of operation.
  • the suspended operation enables the continued operation of the timer circuit 118 using the external clock signal without incurring the additional power requirements associated with active operations.
  • the switch control circuitry 116 controls operation of the clock multiplexer 144 in order to provide both clock and enable signaling of the timer 118.
  • the switch control circuit 116 generates a control signal to toggle the mux select signal for the clock multiplexer 144 ⁇ when the CPU sets the suspend bit indicating that the internal oscillator of 25 Mhz will be stopped. This signal is applied to the switch control circuit via line 224. This causes the generation of control signal on line 226 by control block 150 to gate off the internal clock. Then timer 118 will switch from the internal system clock signal to the external clock signal.
  • the switch control circuit 116 generates a toggle signal on line 222 to the clock multiplexer 144 when the internal oscillator is awakened by any of a number of events and the timer 118 switches from the external clock to the internal system clock or synchronized external clock.
  • These events may include indication of a port match, a comparator zero interrupt or an RTC timer overflow condition.
  • Sync circuit 206 consists of a first flip-flop latch 302 and a second flip-flop latch 304.
  • the external clock signal is applied to the D input of latch 302.
  • the Q output of latch 302 is applied to the D input of latch 304.
  • the Q output of latch 304 is connected to output line 208.
  • the high frequency internal clock signal is provided to the clock inputs of both latch 302 and 304.
  • the control logic of the switch control 116 provides for the switching from the system clock to the external clock or from the external clock to the system clock as illustrated in Fig. 4.
  • clock A and clock B rather than the internal and external clocks which may be either of clock A or B.
  • inquiry step 104 looks for a falling edge of clock A. Once the falling edge of clock A is detected, clock A is gated off from the multiplexer at step 406. It is done by a control signal generated in step 405.
  • inquiry step 408 monitors for the falling edge of clock B.
  • clock B is switched into the multiplexer circuit at stejp 410.
  • This process is the same no matter which clock signals are " being switched between. [0U25J
  • the circuitry for implementing this process is more fully illustrated in Fig. 5 where there is illustrated the multiplexer 144, Hie internal or system clock signal is applied to an AND gate 502.
  • the external clock signal is provided to an AND gate 504.
  • the second inputs of AND gates 502 and 504 are connected to control logic 506 which is responsible for gating a signal onto its respective input to multiplexer 142 in accordance with the flow chart described previously with respect to Fig. 4.
  • Once a signal has been gated onto multiplexer 142, the signal is applied to the timer circuit 118. It is necessary to use a gated clock signal even if the other clock signal has already been removed from input to the clock multiplexer 142 in order to avoid clock glitch if a "wakeup" condition is asserted before clock switching is completed.
  • Fig. 6 there is illustrated the circuitry within the switch control circuit 116 for preventing clock glitch when entering suspend condition.
  • clock switching will only occur after "suspend_qq" is toggled to higli.
  • the circuit is to synchronize the suspend signal to the external clock.
  • the anti-glitch circuit of the switch control circuit 116 consists of a gate 602 and three D flip-flop circuits 604, 606 and 608.
  • the gate 602 receives a number of inputs which may initiate a suspend condition of the MCU 102. All of these conditions being asserted high will cause the output of gate 601 to ⁇ be asserted high.
  • the output of gate 602 is connected to the D input of D flip-flop 604.
  • the Q output of D flip-flop 604 line "suspend_neg” is connected to the D input of D flip-flop 606.
  • the Q output of D flip-flop 606 line “suspend_q” is connected to the D input of the flip-flop 608.
  • the Q output of D flip-flop 608 is connected to line "suspend_qq”.
  • the internal clock signal is connected to the clock input of D flip-flop 604.
  • the external clock signal is connected to the clock input of D flip-flops 606 and 608.
  • the multiplexer will continue to select the internal clock rather than the external clock signal. However, the internal clock has already teen gated off. No clock signal will pass to timer 118 until clock multiplexer 144 has been switched to the external clock.
  • the MCU is generally of the type similar to part number C8051F330/1 manufactured by Silicon Laboratories Inc.
  • the MCU includes in the center thereof a processing core 102 which is typically comprised of a conventional microprocessor of the type "8051.”
  • the processing core 102 receives a clock signal on a line 218 from a multiplexer 142.
  • the multiplexer 142 is operable to select among multiple clocks.
  • the precision internal oscillator 710 is described in U.S. Patent Application Serial No.
  • the processing core 102 is also operable to receive an external reset on terminal 713 or is operable to receive the reset signal from a power-on-reset block 714, all of which provide a reset to processing core 102.
  • the processing core 102 lias associated therewith a plurality of memory resources, "those being either flash memory 716, SRAM memory 718 or random access memory 720.
  • the processing core 102 interfaces with various digital circuitry through an on-board digital bus 722 which allows the processing core 102 to interface with ⁇ arious operating pins 726 that can interface external to the chip to receive digital values, output digital values, receive analog values or output analog values.
  • Various digital I/O circuitry are provided, these being latch circuitry 730, serial port interface circuitry, such as a UART 732, an SPI circuit 734 or an SMBus interface circuit 736.
  • Three timers 738 are provided in addition to another latch circuit 740. All of this circuitry 730-740 is interfacable to the output pins 726 through a crossbar device 742, which is operable to configurably interface these devices with select ones of the outputs.
  • the digital input/outputs can also be interfaced to a digital-to-analog converter 744 for allowing a digital output to be converted to an analog output, or to the digital output of an analog-to-digital converter 746 that receives analog input signals from an analog multiplexer 748 interfaced to a plurality of the input pins on the integrated circuit.
  • the analog multiplexer 748 allows for multiple outputs to be sensed through the pins 726 such that the ADC can be interfaced to various sensors.
  • the MCU 102 is a conventional circuit.
  • the oscillator 710 is a crystal controlled oscillator that is interfaced through two external terminals 802 and 804 to an external crystal 806 and operates up to frequencies in excess of 25 MHz.
  • a Tegister 808 is provided, labeled OSCXCN, which is operable to drive control signals for the oscillator 710 and to record output values thereof.
  • the output of the oscillator 710 is provided on a line 810 to one input of the multiplexer 142.
  • the programmable precision trimmable oscillator 712 is controlled by a register 818 and a register 820 to control the operation thereof, i.e., to both set the frequency thereof and to ena " ble this oscillator.
  • the output of the oscillator 712 is processed through a divide circuit 830, the divide ratio thereof set by bits in the register 820 to provide on an output 822 a precision high frequency clock to another input of the multiplexer 142.
  • the output of the multiplexer 142 is provided to the MCU .102 on the clock line 218 as a system clock signal SYSCLK.
  • the clock select operation is facilitated with a register 824 labeled CLKSEL, which controls the multiplexer 142.
  • the programmable high frequency oscillator 712 is the default clock for system operation after a system reset.
  • the values in the register 818, labeled OSCICL, provide " bits that are typically programmed at the factory, these bits stored in the flash memory.
  • the center frequency of the high frequency clock is 24.5 MHz.
  • the divide circuit 830 can provide a divide ⁇ atio of one, two, four or eight.
  • the oscillator 712, in the C8051F330 device by way of example only, is a ⁇ 2 percent accuracy oscillator which has a center frequency that, although programmed at the factory, is allowed to be adjusted by changing the bits in the register 818.
  • the register 820 provides an enable bit for the oscillator 712 and a bit that determines if the oscillator 712 is running at the programmed frequency. Two bits in the register 820 are utilized to set the divide ratio of "the divider 830.

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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne une unité de microcontrôleur ayant un mode de fonctionnement de suspension comprenant un circuit de traitement pour recevoir des informations numériques et traiter lesdites informations numériques reçues. Un circuit de temporisation génère des signaux de temporisation vers le circuit de traitement en réponse à des signaux reçus depuis un circuit d'horloge générant à la fois un signal d'horloge interne et un signal d'horloge externe. L'invention concerne également un circuit pour commander l'application sélective d'un signal d'horloge externe synchronisé et du signal d'horloge externe au circuit de temporisation. Le circuit applique le signal d'horloge externe synchronisé au circuit de temporisation dans au moins un mode de fonctionnement actif de l'unité de microcontrôleur en réponse à au moins un premier signal de commande et applique le signal d'horloge externe au circuit de temporisation dans au moins un mode de fonctionnement de suspension de l'unité de microcontrôleur en réponse à au moins un signal de commande de suspension.
PCT/US2006/038301 2006-10-02 2006-10-02 Unité de microcontrôleur (mcu) avec mode de suspension WO2008041974A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2006/038301 WO2008041974A2 (fr) 2006-10-02 2006-10-02 Unité de microcontrôleur (mcu) avec mode de suspension
US11/694,619 US7536570B2 (en) 2006-10-02 2007-03-30 Microcontroller unit (MCU) with suspend mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2006/038301 WO2008041974A2 (fr) 2006-10-02 2006-10-02 Unité de microcontrôleur (mcu) avec mode de suspension

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WO2008041974A2 true WO2008041974A2 (fr) 2008-04-10
WO2008041974A3 WO2008041974A3 (fr) 2009-04-30

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9503102B2 (en) * 2014-08-29 2016-11-22 Tektronix, Inc. Synchronization for multiple arbitrary waveform generators

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6687843B2 (en) * 1999-11-30 2004-02-03 Hyundai Electronics Industries Co., Ltd. Rambus DRAM with clock control circuitry that reduces power consumption
US7057967B2 (en) * 2001-12-26 2006-06-06 Brian Johnson Multi-mode synchronous memory device and methods of operating and testing same
US7194644B2 (en) * 2003-02-06 2007-03-20 Stmicroelectronics S.A. System and method for operating a microprocessor in a low power mode by providing a wakeup clock to the microprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6687843B2 (en) * 1999-11-30 2004-02-03 Hyundai Electronics Industries Co., Ltd. Rambus DRAM with clock control circuitry that reduces power consumption
US7057967B2 (en) * 2001-12-26 2006-06-06 Brian Johnson Multi-mode synchronous memory device and methods of operating and testing same
US7194644B2 (en) * 2003-02-06 2007-03-20 Stmicroelectronics S.A. System and method for operating a microprocessor in a low power mode by providing a wakeup clock to the microprocessor

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