WO2008040031A2 - Emitter ballasting by contact area segmentation in esd bipolar based semiconductor component - Google Patents

Emitter ballasting by contact area segmentation in esd bipolar based semiconductor component Download PDF

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Publication number
WO2008040031A2
WO2008040031A2 PCT/US2007/080412 US2007080412W WO2008040031A2 WO 2008040031 A2 WO2008040031 A2 WO 2008040031A2 US 2007080412 W US2007080412 W US 2007080412W WO 2008040031 A2 WO2008040031 A2 WO 2008040031A2
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emitter
type
forming
region
well
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PCT/US2007/080412
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French (fr)
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WO2008040031A3 (en
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Marie Denison
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Texas Instruments Incorporated
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Priority claimed from US11/863,971 external-priority patent/US8866263B2/en
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Publication of WO2008040031A2 publication Critical patent/WO2008040031A2/en
Publication of WO2008040031A3 publication Critical patent/WO2008040031A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H01L29/7304—Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • This invention relates to the field of integrated circuits. More particularly, this invention relates to bipolar transistors as independent components and as elements of electronic components in integrated circuits. BACKGROUND
  • ICs integrated circuits
  • ICs are comprised of microelectronic components such as transistors, diodes, resistors, capacitors, etc., in a substrate, and metal interconnects which connect the components in circuits.
  • some internal nodes of an IC are connected to external nodes.
  • Internal nodes of an IC are connected to external nodes by metal elements, known as Input-Output (IO) pads or bondpads, among other designations, on the top surface of an IC.
  • IO pads are connected to external functions by various means, including wire bonding, bump bonding, beam lead bonding, etc.
  • IO pads are connected to external functions by various means, including wire bonding, bump bonding, beam lead bonding, etc.
  • ESD electrostatic discharge
  • ESD protection devices and circuits in ICs are connected to bondpads to provide sufficient ESD immunity from typical IC manufacturing, packaging and assembly, and product end use environments.
  • bipolar transistors Common electrical components in ESD protection circuits are bipolar transistors. Bipolar transistors are used to provide a low resistance shunt to ground during ESD events. In order to handle large currents associated with ESD events, bipolar transistors used in ESD protection circuits have large emitter-base junction areas, compared to transistors used for logic or signal processing circuits. Large junction areas are necessary to sustain the high power dissipated during ESD events and to minimize the voltage increase across the device at high current. Contacts and optional metal suicide uniformly distributed across the surface of the emitter, base and collector are used for uniform junction biasing and low resistive current conduction to the metal interconnects.
  • the invention comprises a segmented emitter contact region of a bipolar transistor separated into a plurality of contact islands by emitter diffusion drift regions, which act as a ballast network distributed around each contact island. Additionally, the emitter may be subdivided into a plurality of junctions, each with one or a plurality of contact islands separated by emitter drift regions. Furthermore, emitter ballast resistors may be connected in series with emitter contact islands. This invention also includes a method for fabricating an emitter with segmented contact region and segmented diffused regions. BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a bipolar transistor with multiple emitter contact islands according to an embodiment of the instant invention.
  • FIGS. 2A - 2C are a set of top views of bipolar transistors according to embodiments of the instant invention.
  • FIGS. 3A and 3B are a set of top views of contact islands to emitters of a bipolar transistors according to embodiments of the instant invention.
  • FIG. 4 is a cross-sectional view of a bipolar transistor with multiple diffused regions in the emitter according to an embodiment of the instant invention.
  • FIGS. 5 A and 5B are a top view of the emitter region of a bipolar transistor in an ESD protection circuit with multiple emitter diffused regions and one contact island per emitter diffused region according to an embodiment of the instant invention.
  • FIGS. 6 A and 6B are a top view of the emitter region of a bipolar transistor in an ESD protection circuit with multiple emitter diffused regions and multiple contact islands per emitter diffused region according to an embodiment of the instant invention.
  • DETAILED DESCRIPTION OF REPRESENTATIVE EXAMPLE EMBODIMENTS For the purposes of this disclosure, a contact island is defined as a region containing a plurality of contacts wherein the contacts are spaced more closely to one another than to other contacts not in the contact island. If metal suicide is used in the contact island, the contact island extends to the boundaries of the metal suicide.
  • an emitter diffused region is defined as a contiguous region of an IC substrate forming part or all of an emitter of a bipolar transistor, in which the contiguous region of the IC substrate is doped the same type throughout.
  • the boundary of the emitter diffused region extends to the boundary of the contiguous region of the IC substrate with the same type doping as the emitter diffused region.
  • FIG. 1 is a cross-sectional view of a bipolar transistor with multiple emitter contact islands according to an embodiment of the instant invention.
  • An IC (100) includes a substrate (102), which may have an epitaxial layer (104), n-channel MOS (NMOS) transistors (not shown for clarity) and p-channel MOS (PMOS) transistors (not shown for clarity).
  • the substrate is p-type silicon and the epitaxial layer is n-type silicon.
  • the epitaxial layer may also be p-doped and counter-doped by a deep n-well.
  • P-type regions (106) isolate the region of the bipolar transistor.
  • An optional buried collector of n- type silicon (108) and n-type connector region (110) provide a low resistance path from the collector surface diffused region (112) to the base region (114).
  • the collector surface diffused region (112) may be formed in the same process operations that form the source and drain region of n-channel MOS transistors in said integrated circuit.
  • the emitter (116) of the bipolar transistor is n-type silicon, and is typically formed in the same operations as the collector surface diffused region at the surface of the wafer.
  • the base region (118) at the surface of the wafer is p-type silicon, and may be formed in the same process operations that form the source and drain region of P-channel MOS transistors in said integrated circuit.
  • the base well (114) is p-type silicon, and may be formed in the same process operations that forms the backgate well of n-channel MOS transistors in said integrated circuit.
  • Base, emitter and collector regions may be separated by a thick isolation layer penetrating into the silicon (not shown for clarity), typically comprised of silicon dioxide, typically formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI).
  • Metal suicide (120, 122, 124) may be formed on the top surfaces of the collector, base and emitter, respectively, to reduce the contact series resistance.
  • a plurality of contact and metal regions (126), including suicide, if used, is formed on the top surface of the emitter.
  • the contact and suicide area segmentation is advantageous as it results in a distributed emitter diffusion drift ballast resistance network which counteracts any local increase of current across the emitter during ESD stress and therefore suppresses or significantly delays current crowding.
  • Bipolar transistors are prone to develop localized current filaments under ESD surge, and the current flow is unstable in the presence of any variation of electrical parameters across the transistor. If ESD collector-emitter current tends to increase in some region within the emitter area, the voltage drop across a local emitter ballast will cause a decrease of the effective base-emitter voltage difference in this region, resulting in a decrease of ESD collector-emitter current in this segment.
  • Another advantage of emitter contact segmentation is increased bipolar gain in technologies based on advanced CMOS processes.
  • junction depths of diffused regions 114, 116 and 118 are very shallow, especially if they are suicided, resulting in an, resulting in lower bipolar transistor gain in advanced CMOS ICs due to increased injection of base majority carriers into emitter contact regions. Emitter contact segmentation reduces this injection, and thus increases bipolar transistor gain. Contacts are made to the collector (128), to the emitter (130) and to the base (132) to connect the bipolar transistor to the ESD protection circuit. The area of the emitter-base junction (134) is sized appropriately to carry the anticipated ESD discharge current and power at a desired voltage drop.
  • the metal suicide islands over the emitter is preferably offset from the edge of the emitter diffused region to form a drift region along an edge of the emitter.
  • a base region may be placed between a collector and an emitter, if no lateral bipolar component is required.
  • External resistors such as polysilicon resistors or metal interconnect meander resistors, may be connected to each emitter contact island to increase ballasting.
  • bipolar transistor of opposite polarity from that described in reference to FIG. 1, namely a pnp bipolar transistor, may be fabricated to have a plurality of contact islands on an emitter, by following the discussion in reference to FIG. 1, with an appropriate change in doping of some elements, including the collector, base and emitter.
  • FIGS. 2A - 2C are a set of top views of bipolar transistors according to embodiments of the instant invention.
  • a collector (200) is near an emitter (202) and a base (204).
  • the collector (200) may have a layer of metal suicide (206) that may be coterminous with the collector (200).
  • the collector may include a buried layer (omitted for clarity) under emitter and base or extending from the deep collector (110) toward the base.
  • Base (204) may have a layer of metal suicide (210) that may be coterminous with base (204).
  • Collector (200) is contacted by metal vias (212).
  • Base (202) is contacted by metal vias (216).
  • Emitter (202) is contacted by metal vias (214).
  • the groups of metal vias (214) in combination with metal suicide islands, if used, over the emitter (202) form contact islands (218).
  • Emitter (202) has a plurality of contact islands (208) with optional metal suicide.
  • Contact islands (218) may be any shape, including, but not limited to, square, rectangular, hexagonal, circular or oval. Contact islands (218) need not be uniform in size or shape. Contact islands may e configured concentrically. ESD discharge current produces a voltage drop that debiases the base-emitter junction around the contact islands, impeding any significant increase of current flowing through each contact island and thereby effectively maintaining a balanced sharing of ESD discharge current between the contact islands on the emitter.
  • an avalanche region is located near the buried collector, and ESD current flows from the discrete contact islands (218) to a homogeneous power dissipating region under the base. Emitter contact area segmentation produces a more uniform current distribution across the base, resulting in a higher current capacity than would be possible in absence of emitter contact segmentation.
  • a collector (200) is near an emitter (202) and a base (204).
  • the collector (200) may have a layer of metal suicide (206) that may be coterminous with the collector (200).
  • Collector may include a buried layer (not shown for clarity) under emitter and base or extending from the deep collector (110) toward the base.
  • Base (204) may have a layer of metal suicide (210) that may be coterminous with base (204).
  • Collector (200) is contacted by metal vias (212).
  • Base (202) is contacted by metal vias (216).
  • Emitter (202) is contacted by metal vias (214).
  • the groups of metal vias (214) in combination with metal suicide islands (208), if used, over the emitter (202) form contact islands (218).
  • Emitter (202) has a plurality of contact islands (208) with optional metal suicide, configured in this embodiment to reduce current crowding at the ends of emitter (202).
  • Size and shape of contact islands (218) may be any shape, including, but not limited to, square, rectangular, hexagonal, circular or oval.
  • Contact islands (218) need not be uniform in size or shape.
  • ESD discharge current produces a voltage drop that debiases the base-emitter junction around the contact island at the emitter end, effectively impeding an increase in the discharge current density at this position compared to the remaining of the emitter area.
  • an avalanche region is located near the buried collector, and ESD current flows from the discrete contact islands (218) to a homogeneous power dissipating region under the base.
  • Emitter contact area segmentation as shown in FIG. 2B produces a more uniform current distribution across the base, resulting in a higher current capacity than would be possible in absence of emitter contact segmentation.
  • FIG. 2C depicts another embodiment of the instant invention, in which an emitter (202) is located between two bases (204), which are located between two collectors (200).
  • the configuration depicted in FIG. 2C is advantageous because current capacity is increased.
  • FIGS. 3A and 3B are a set of top views of contact islands to emitters of bipolar transistors in ESD protection circuits in other embodiments of the instant invention.
  • FIG. 3 A depicts an embodiment of the instant invention with a single emitter diffused region (300) with a plurality of arbitrarily shaped contact islands (302) that are contacted by metal vias (304), and a drift region ballast around each contact island (302). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands (306). This configuration optimizes the current distribution in bipolar transistors with emitter lengths longer than a typical current filament.
  • FIG. 3B depicts another embodiment of the instant invention with an emitter (300) with a plurality of elongated contact islands (302) that are contacted by metal vias (304). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands (506). This configuration is advantageous for bipolar transistors with emitter lengths comparable to a typical current filament extent.
  • FIG. 3C depicts another embodiment of the instant invention with an emitter (300) with a plurality of elongated contact islands (302) that are oriented parallel to a long axis of the emitter. The configuration depicted in FIG. 3C is advantageous for some ranges of doping and geometry of emitter and collector regions.
  • bipolar transistors with a single emitter diffused region having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, interleaved combs, and square.
  • FIG. 4 is a cross-sectional view of a bipolar transistor with a plurality of emitter diffused regions in an emitter according to another embodiment of the instant invention.
  • An IC (400) includes a substrate (402), which may have an epitaxial layer (404), n-channel MOS (NMOS) transistors (not shown for clarity) and p-channel MOS (PMOS) transistors (not shown for clarity).
  • the substrate is p-type silicon and the epitaxial layer is n- type silicon.
  • the epitaxial layer may also be p-doped and counter-doped by a deep n-well.
  • P-type regions (406) isolate the region of the bipolar transistor.
  • a buried collector of n-type silicon (408) and n-type connector region (410) provide a low resistance path from the collector surface diffused region (412) to the base region (414).
  • the collector surface diffused region (412) may be formed in the same process operations that form the source and drain region of N-channel MOS transistors in said integrated circuit.
  • the emitters (416) of the bipolar transistor are n-type silicon, and are typically formed in the same operations as the collector region at the surface of the wafer.
  • the base contact diffusion region (418) at the surface of the wafer is p-type silicon, and may be formed in the same process operations that form the source and drain region of P-channel MOS transistors in said integrated circuit.
  • Base, emitter and collector regions may be separated by an insulating layer partially penetrating into the substrate (not shown for clarity), typically comprised of silicon dioxide, typically formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI).
  • Metal suicide (420, 422, 424) may be formed on the top surfaces of the collector, base and emitter, respectively, to reduce the contact series resistance.
  • the plurality of emitter diffused regions and segmentation of contact and suicide area are advantageous as they result in a distributed emitter diffusion drift resistance network which counteracts any local increase of current across the emitter during ESD stress and therefore delays current crowding, reducing current crowding.
  • Contacts are made to the collector (428) and to the emitter (430) and to the base (432) to connect the bipolar transistor to the ESD protection circuit.
  • the combined area of the emitter-base junctions (434) is sized appropriately to carry the anticipated ESD discharge current and power at a desired voltage drop.
  • the metal suicide islands over the emitter is preferably offset from the edge of the emitter diffused region to form a drift region along an edge of the emitter.
  • External resistors such as polysilicon resistors or metal interconnect meander resistors, may be connected to each emitter contact island to increase ballasting.
  • bipolar transistor of opposite polarity from that described in reference to FIG. 1, namely a pnp bipolar transistor, may be fabricated to have a plurality of contact islands on an emitter, by following the discussion in reference to FIG. 1, with an appropriate change in doping and polarity of some elements, including the collector, base and emitter.
  • FIGS. 5A and 5B are a set of top views of emitters of bipolar transistors in ESD protection circuits with multiple emitter diffused regions and one contact island per emitter diffused region, and a drift region around each contact island, according to an embodiment of the instant invention.
  • FIG. 5 A depicts an embodiment of the instant invention wherein a plurality of emitter diffused regions (500) comprises the emitter of the bipolar transistor, with one arbitrarily shaped contact island (502), which may include metal suicide on the surface of the emitter in the island region (502), per emitter region.
  • Each contact island is contacted by metal vias (504). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands.
  • FIG. 5B depicts another embodiment of this invention wherein a plurality of elongated emitter diffused regions (500) comprises the emitter of the bipolar transistor, with one elongated contact island (502) per emitter region. Each contact island is contacted by metal vias (504). This configuration may be used for emitter lengths shorter than a typical current filament. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands. A plurality of emitter diffused regions can be advantageous to spread the power density in the underlying collector or to modulate the gain of the transistor. In some circuits, a plurality of emitter diffused regions separated by base contact areas can be advantageous to in order to maintain a homogeneous gain across the transistor.
  • bipolar transistors with a plurality of emitter diffused regions having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, comb and serpent, and square.
  • Emitter diffused regions may be configured concentrically.
  • FIGS. 6A and 6B are a set of top views of emitters of bipolar transistors in ESD protection circuits with a plurality of emitter diffused regions and a plurality of contact islands in each emitter diffused region, and a drift region around each contact island, according to embodiments of the instant invention invention.
  • FIG. 6 A depicts an embodiment of this invention wherein a plurality of arbitrarily shaped emitter diffused regions (600) comprises the emitter of the bipolar transistor, with a plurality of contact islands (602) per emitter region. Each contact island is contacted by metal vias (604). This configuration may be used with emitters larger than typical current filament lengths. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands.
  • FIG. 6B depicts another embodiment of this invention wherein a plurality of elongated emitter diffused regions (600) comprises the emitter of the bipolar transistor, with a plurality of elongated contact islands (602) per emitter region. Each contact island is contacted by metal vias (604). This configuration may be used with emitter lengths comparable to a typical current filament. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands. The advantages of segmenting the contacts and of a plurality of emitter diffused regions are both realized in the embodiments depicted in FIGS. 6 A and 6B.
  • bipolar transistors with a plurality of emitter diffused regions and a plurality of contact islands in each emitter diffused region having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, comb and serpent, and square.

Abstract

Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.

Description

EMITTER BALLASTING BY CONTACT AREA SEGMENTATION IN ESD BIPOLAR BASED SEMICONDUCTOR COMPONENT
This invention relates to the field of integrated circuits. More particularly, this invention relates to bipolar transistors as independent components and as elements of electronic components in integrated circuits. BACKGROUND
It is well known that integrated circuits (ICs) are comprised of microelectronic components such as transistors, diodes, resistors, capacitors, etc., in a substrate, and metal interconnects which connect the components in circuits. It is furthermore well known that some internal nodes of an IC are connected to external nodes. Internal nodes of an IC are connected to external nodes by metal elements, known as Input-Output (IO) pads or bondpads, among other designations, on the top surface of an IC. IO pads are connected to external functions by various means, including wire bonding, bump bonding, beam lead bonding, etc. By necessity, internal nodes of an IC that are connected to IO pads are exposed to the electrical environment of manufacturing processes and packaging and assembly processes. Moreover, in some applications, internal nodes are exposed to user electrical environments during the life of a product in which an IC is included. Electrical environments consist of static and time-varying electric and magnetic fields, and electric charge sources, such as humans with a static charge or electrically charged objects in close proximity to ICs. These features of electrical environments, especially charge sources, pose a significant danger to ICs. Charge sources are often at a much higher electrical potential than ICs. When charge sources come into close proximity to ICs, large potential differences between charge sources and ICs, typically between a few tens of volts and a few thousand volts, can cause a gap between them to become electrically conducting as a result of avalanche ionization and breakdown of a separating medium, usually air. The result of breakdown of a gap between a charge source and an IC is to partially or completely discharge the charge source into the IC, and is known as electrostatic discharge (ESD). Electrical currents associated with ESD are typically very high and can damage components of an IC.
In typical IC manufacturing and packaging and assembly operations, great care is taken to avoid exposing ICs to ESD hazards. Nevertheless, ICs are subject to ESD incidents. ESD protection devices and circuits in ICs are connected to bondpads to provide sufficient ESD immunity from typical IC manufacturing, packaging and assembly, and product end use environments.
Common electrical components in ESD protection circuits are bipolar transistors. Bipolar transistors are used to provide a low resistance shunt to ground during ESD events. In order to handle large currents associated with ESD events, bipolar transistors used in ESD protection circuits have large emitter-base junction areas, compared to transistors used for logic or signal processing circuits. Large junction areas are necessary to sustain the high power dissipated during ESD events and to minimize the voltage increase across the device at high current. Contacts and optional metal suicide uniformly distributed across the surface of the emitter, base and collector are used for uniform junction biasing and low resistive current conduction to the metal interconnects.
Current nonhomogeneity and current crowding are well known to be issues in bipolar transistors in ESD protection circuits. Current crowding occurring during ESD events can result in permanent damage to bipolar transistors, causing loss of circuit functionality or shortened operating life of ESD protection circuit and IC. SUMMARY
The invention comprises a segmented emitter contact region of a bipolar transistor separated into a plurality of contact islands by emitter diffusion drift regions, which act as a ballast network distributed around each contact island. Additionally, the emitter may be subdivided into a plurality of junctions, each with one or a plurality of contact islands separated by emitter drift regions. Furthermore, emitter ballast resistors may be connected in series with emitter contact islands. This invention also includes a method for fabricating an emitter with segmented contact region and segmented diffused regions. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a bipolar transistor with multiple emitter contact islands according to an embodiment of the instant invention.
FIGS. 2A - 2C are a set of top views of bipolar transistors according to embodiments of the instant invention.
FIGS. 3A and 3B are a set of top views of contact islands to emitters of a bipolar transistors according to embodiments of the instant invention. FIG. 4 is a cross-sectional view of a bipolar transistor with multiple diffused regions in the emitter according to an embodiment of the instant invention.
FIGS. 5 A and 5B are a top view of the emitter region of a bipolar transistor in an ESD protection circuit with multiple emitter diffused regions and one contact island per emitter diffused region according to an embodiment of the instant invention.
FIGS. 6 A and 6B are a top view of the emitter region of a bipolar transistor in an ESD protection circuit with multiple emitter diffused regions and multiple contact islands per emitter diffused region according to an embodiment of the instant invention. DETAILED DESCRIPTION OF REPRESENTATIVE EXAMPLE EMBODIMENTS For the purposes of this disclosure, a contact island is defined as a region containing a plurality of contacts wherein the contacts are spaced more closely to one another than to other contacts not in the contact island. If metal suicide is used in the contact island, the contact island extends to the boundaries of the metal suicide.
For the purposes of this disclosure, an emitter diffused region is defined as a contiguous region of an IC substrate forming part or all of an emitter of a bipolar transistor, in which the contiguous region of the IC substrate is doped the same type throughout. The boundary of the emitter diffused region extends to the boundary of the contiguous region of the IC substrate with the same type doping as the emitter diffused region.
FIG. 1 is a cross-sectional view of a bipolar transistor with multiple emitter contact islands according to an embodiment of the instant invention. An IC (100) includes a substrate (102), which may have an epitaxial layer (104), n-channel MOS (NMOS) transistors (not shown for clarity) and p-channel MOS (PMOS) transistors (not shown for clarity). In this example, the substrate is p-type silicon and the epitaxial layer is n-type silicon. The epitaxial layer may also be p-doped and counter-doped by a deep n-well. P-type regions (106) isolate the region of the bipolar transistor. An optional buried collector of n- type silicon (108) and n-type connector region (110) provide a low resistance path from the collector surface diffused region (112) to the base region (114). The collector surface diffused region (112) may be formed in the same process operations that form the source and drain region of n-channel MOS transistors in said integrated circuit. The emitter (116) of the bipolar transistor is n-type silicon, and is typically formed in the same operations as the collector surface diffused region at the surface of the wafer. The base region (118) at the surface of the wafer is p-type silicon, and may be formed in the same process operations that form the source and drain region of P-channel MOS transistors in said integrated circuit. The base well (114) is p-type silicon, and may be formed in the same process operations that forms the backgate well of n-channel MOS transistors in said integrated circuit. Base, emitter and collector regions may be separated by a thick isolation layer penetrating into the silicon (not shown for clarity), typically comprised of silicon dioxide, typically formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Metal suicide (120, 122, 124) may be formed on the top surfaces of the collector, base and emitter, respectively, to reduce the contact series resistance. A plurality of contact and metal regions (126), including suicide, if used, is formed on the top surface of the emitter. The contact and suicide area segmentation is advantageous as it results in a distributed emitter diffusion drift ballast resistance network which counteracts any local increase of current across the emitter during ESD stress and therefore suppresses or significantly delays current crowding. Bipolar transistors are prone to develop localized current filaments under ESD surge, and the current flow is unstable in the presence of any variation of electrical parameters across the transistor. If ESD collector-emitter current tends to increase in some region within the emitter area, the voltage drop across a local emitter ballast will cause a decrease of the effective base-emitter voltage difference in this region, resulting in a decrease of ESD collector-emitter current in this segment. Another advantage of emitter contact segmentation is increased bipolar gain in technologies based on advanced CMOS processes. In advanced CMOS ICs, junction depths of diffused regions 114, 116 and 118 are very shallow, especially if they are suicided, resulting in an, resulting in lower bipolar transistor gain in advanced CMOS ICs due to increased injection of base majority carriers into emitter contact regions. Emitter contact segmentation reduces this injection, and thus increases bipolar transistor gain. Contacts are made to the collector (128), to the emitter (130) and to the base (132) to connect the bipolar transistor to the ESD protection circuit. The area of the emitter-base junction (134) is sized appropriately to carry the anticipated ESD discharge current and power at a desired voltage drop. If suicide is used, the metal suicide islands over the emitter is preferably offset from the edge of the emitter diffused region to form a drift region along an edge of the emitter. A base region may be placed between a collector and an emitter, if no lateral bipolar component is required. External resistors, such as polysilicon resistors or metal interconnect meander resistors, may be connected to each emitter contact island to increase ballasting.
It will be recognized by those familiar with bipolar transistor fabrication, that a bipolar transistor of opposite polarity from that described in reference to FIG. 1, namely a pnp bipolar transistor, may be fabricated to have a plurality of contact islands on an emitter, by following the discussion in reference to FIG. 1, with an appropriate change in doping of some elements, including the collector, base and emitter.
FIGS. 2A - 2C are a set of top views of bipolar transistors according to embodiments of the instant invention. Referring to FIG. 2A, a collector (200) is near an emitter (202) and a base (204). The collector (200) may have a layer of metal suicide (206) that may be coterminous with the collector (200). The collector may include a buried layer (omitted for clarity) under emitter and base or extending from the deep collector (110) toward the base. Base (204) may have a layer of metal suicide (210) that may be coterminous with base (204). Collector (200) is contacted by metal vias (212). Base (202) is contacted by metal vias (216). Emitter (202) is contacted by metal vias (214). The groups of metal vias (214) in combination with metal suicide islands, if used, over the emitter (202) form contact islands (218). Emitter (202) has a plurality of contact islands (208) with optional metal suicide. Contact islands (218) may be any shape, including, but not limited to, square, rectangular, hexagonal, circular or oval. Contact islands (218) need not be uniform in size or shape. Contact islands may e configured concentrically. ESD discharge current produces a voltage drop that debiases the base-emitter junction around the contact islands, impeding any significant increase of current flowing through each contact island and thereby effectively maintaining a balanced sharing of ESD discharge current between the contact islands on the emitter. In an ESD event, an avalanche region is located near the buried collector, and ESD current flows from the discrete contact islands (218) to a homogeneous power dissipating region under the base. Emitter contact area segmentation produces a more uniform current distribution across the base, resulting in a higher current capacity than would be possible in absence of emitter contact segmentation.
The layout depicted is an asymmetric bipolar transistor. It is within the scope of this invention to have other transistor layouts with emitter segmentation, including symmetric layouts. Referring to FIG. 2B, a collector (200) is near an emitter (202) and a base (204). The collector (200) may have a layer of metal suicide (206) that may be coterminous with the collector (200). Collector may include a buried layer (not shown for clarity) under emitter and base or extending from the deep collector (110) toward the base. Base (204) may have a layer of metal suicide (210) that may be coterminous with base (204). Collector (200) is contacted by metal vias (212). Base (202) is contacted by metal vias (216). Emitter (202) is contacted by metal vias (214). The groups of metal vias (214) in combination with metal suicide islands (208), if used, over the emitter (202) form contact islands (218). Emitter (202) has a plurality of contact islands (208) with optional metal suicide, configured in this embodiment to reduce current crowding at the ends of emitter (202). Size and shape of contact islands (218) may be any shape, including, but not limited to, square, rectangular, hexagonal, circular or oval. Contact islands (218) need not be uniform in size or shape. ESD discharge current produces a voltage drop that debiases the base-emitter junction around the contact island at the emitter end, effectively impeding an increase in the discharge current density at this position compared to the remaining of the emitter area. In an ESD event, an avalanche region is located near the buried collector, and ESD current flows from the discrete contact islands (218) to a homogeneous power dissipating region under the base. Emitter contact area segmentation as shown in FIG. 2B produces a more uniform current distribution across the base, resulting in a higher current capacity than would be possible in absence of emitter contact segmentation.
FIG. 2C depicts another embodiment of the instant invention, in which an emitter (202) is located between two bases (204), which are located between two collectors (200). The configuration depicted in FIG. 2C is advantageous because current capacity is increased. FIGS. 3A and 3B are a set of top views of contact islands to emitters of bipolar transistors in ESD protection circuits in other embodiments of the instant invention.
FIG. 3 A depicts an embodiment of the instant invention with a single emitter diffused region (300) with a plurality of arbitrarily shaped contact islands (302) that are contacted by metal vias (304), and a drift region ballast around each contact island (302). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands (306). This configuration optimizes the current distribution in bipolar transistors with emitter lengths longer than a typical current filament.
FIG. 3B depicts another embodiment of the instant invention with an emitter (300) with a plurality of elongated contact islands (302) that are contacted by metal vias (304). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands (506). This configuration is advantageous for bipolar transistors with emitter lengths comparable to a typical current filament extent. FIG. 3C depicts another embodiment of the instant invention with an emitter (300) with a plurality of elongated contact islands (302) that are oriented parallel to a long axis of the emitter. The configuration depicted in FIG. 3C is advantageous for some ranges of doping and geometry of emitter and collector regions.
It is within the scope of this invention to have bipolar transistors with a single emitter diffused region having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, interleaved combs, and square.
FIG. 4 is a cross-sectional view of a bipolar transistor with a plurality of emitter diffused regions in an emitter according to another embodiment of the instant invention. An IC (400) includes a substrate (402), which may have an epitaxial layer (404), n-channel MOS (NMOS) transistors (not shown for clarity) and p-channel MOS (PMOS) transistors (not shown for clarity). In this example, the substrate is p-type silicon and the epitaxial layer is n- type silicon. The epitaxial layer may also be p-doped and counter-doped by a deep n-well. P-type regions (406) isolate the region of the bipolar transistor. A buried collector of n-type silicon (408) and n-type connector region (410) provide a low resistance path from the collector surface diffused region (412) to the base region (414). The collector surface diffused region (412) may be formed in the same process operations that form the source and drain region of N-channel MOS transistors in said integrated circuit. The emitters (416) of the bipolar transistor are n-type silicon, and are typically formed in the same operations as the collector region at the surface of the wafer. The base contact diffusion region (418) at the surface of the wafer is p-type silicon, and may be formed in the same process operations that form the source and drain region of P-channel MOS transistors in said integrated circuit. Base, emitter and collector regions may be separated by an insulating layer partially penetrating into the substrate (not shown for clarity), typically comprised of silicon dioxide, typically formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Metal suicide (420, 422, 424) may be formed on the top surfaces of the collector, base and emitter, respectively, to reduce the contact series resistance. A plurality of contact islands (426), including suicide, if used, is formed on the top surface of the emitter. The plurality of emitter diffused regions and segmentation of contact and suicide area are advantageous as they result in a distributed emitter diffusion drift resistance network which counteracts any local increase of current across the emitter during ESD stress and therefore delays current crowding, reducing current crowding. Contacts are made to the collector (428) and to the emitter (430) and to the base (432) to connect the bipolar transistor to the ESD protection circuit. The combined area of the emitter-base junctions (434) is sized appropriately to carry the anticipated ESD discharge current and power at a desired voltage drop. If suicide is used, the metal suicide islands over the emitter is preferably offset from the edge of the emitter diffused region to form a drift region along an edge of the emitter. External resistors, such as polysilicon resistors or metal interconnect meander resistors, may be connected to each emitter contact island to increase ballasting.
It will be recognized by those familiar with bipolar transistor fabrication that a bipolar transistor of opposite polarity from that described in reference to FIG. 1, namely a pnp bipolar transistor, may be fabricated to have a plurality of contact islands on an emitter, by following the discussion in reference to FIG. 1, with an appropriate change in doping and polarity of some elements, including the collector, base and emitter.
FIGS. 5A and 5B are a set of top views of emitters of bipolar transistors in ESD protection circuits with multiple emitter diffused regions and one contact island per emitter diffused region, and a drift region around each contact island, according to an embodiment of the instant invention.
FIG. 5 A depicts an embodiment of the instant invention wherein a plurality of emitter diffused regions (500) comprises the emitter of the bipolar transistor, with one arbitrarily shaped contact island (502), which may include metal suicide on the surface of the emitter in the island region (502), per emitter region. Each contact island is contacted by metal vias (504). If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands.
FIG. 5B depicts another embodiment of this invention wherein a plurality of elongated emitter diffused regions (500) comprises the emitter of the bipolar transistor, with one elongated contact island (502) per emitter region. Each contact island is contacted by metal vias (504). This configuration may be used for emitter lengths shorter than a typical current filament. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands. A plurality of emitter diffused regions can be advantageous to spread the power density in the underlying collector or to modulate the gain of the transistor. In some circuits, a plurality of emitter diffused regions separated by base contact areas can be advantageous to in order to maintain a homogeneous gain across the transistor.
It is within the scope of this invention to have bipolar transistors with a plurality of emitter diffused regions having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, comb and serpent, and square. Emitter diffused regions may be configured concentrically.
FIGS. 6A and 6B are a set of top views of emitters of bipolar transistors in ESD protection circuits with a plurality of emitter diffused regions and a plurality of contact islands in each emitter diffused region, and a drift region around each contact island, according to embodiments of the instant invention invention.
FIG. 6 A depicts an embodiment of this invention wherein a plurality of arbitrarily shaped emitter diffused regions (600) comprises the emitter of the bipolar transistor, with a plurality of contact islands (602) per emitter region. Each contact island is contacted by metal vias (604). This configuration may be used with emitters larger than typical current filament lengths. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands.
FIG. 6B depicts another embodiment of this invention wherein a plurality of elongated emitter diffused regions (600) comprises the emitter of the bipolar transistor, with a plurality of elongated contact islands (602) per emitter region. Each contact island is contacted by metal vias (604). This configuration may be used with emitter lengths comparable to a typical current filament. If suicide is used, the boundary of each suicide region extends to the boundary of the corresponding contact island. If suicide is not used, the contacts are configured in a plurality of contact islands. The advantages of segmenting the contacts and of a plurality of emitter diffused regions are both realized in the embodiments depicted in FIGS. 6 A and 6B. It is within the scope of this invention to have bipolar transistors with a plurality of emitter diffused regions and a plurality of contact islands in each emitter diffused region having other configurations of collector, base and emitter regions, including, but not limited to, circular, oval, comb and serpent, and square.
Those skilled in the art will appreciate that the described embodiments are representative implementations, and that many variations of those implementations and other implementations exist within the scope of the claimed invention.

Claims

CLAIMSWhat is claimed is:
1. A bipolar transistor comprising: an emitter, contacts to said emitter, wherein contacts are configured in a plurality of groups known as contact islands, a base, adjacent to said emitter and including a region under said emitter, and a collector, including a region extending toward and possibly under said base.
2. The bipolar transistor of claim 1, wherein said emitter is further comprised of a single emitter diffused region.
3. The bipolar transistor of claim 1, wherein said emitter is further comprised of a plurality of emitter diffused regions.
4. The bipolar transistor of claim 3, further comprising a plurality of contact islands in each emitter diffused region.
5. An integrated circuit comprising: provided a substrate; a region of an insulating layer partially penetrating into said substrate; an n-well in said substrate; a p-well in said substrate; an n-channel MOS transistor in said p-well comprising: a first gate dielectric on a top surface of said p-well; a first gate structure on a top surface of said first gate dielectric; n-type source and drain regions in said p-well adjacent to said first gate structure; and an optional first set of suicide regions on, and in contact with, top surfaces of said n-type source and drain regions; a p-channel MOS transistor in said n-well comprising: a second gate dielectric on a top surface of said n-well; a second gate structure on a top surface of said second gate dielectric; p-type source and drain regions in said n-well adjacent to said second gate structure; and an optional second set of suicide regions on, and in contact with, top surfaces of said p-type source and drain regions; an npn bipolar transistor in said substrate, comprising: an n-type emitter, comprising an n-type emitter diffused region; a p-type base adjacent to said n-type emitter and including a region under said n-type emitter; and an n-type collector, comprising an n-type collector diffused region and an n-type buried collector region contacting the n-type collector diffused region and extending toward and possibly under said p-type base; a pre-metal dielectric layer stack on said n-channel transistor and said p-channel transistor; and contacts in said pre-metal dielectric layer stack on, and electrically connected to, said n-type source and drain regions, said p-type source and drain regions, said n-type collector, said p-type base, and said n-type emitter, wherein the contacts to said n-type emitter are configured in a plurality of contact islands.
6. The integrated circuit of claim 5, wherein said n-type emitter is further comprised of a plurality of emitter diffused regions.
7. The integrated circuit of claim 10, further comprising a plurality of contact islands in each emitter diffused region.
8. A method for fabricating an integrated circuit, comprising the steps: providing a substrate; forming a region of an insulating layer partially penetrating into said substrate; forming an n-well in said substrate; forming a p-well in said substrate; forming an n-channel MOS transistor in said p-well comprising the steps: forming a first gate dielectric on a top surface of said p-well; forming a first gate structure on a top surface of said first gate dielectric; forming n-type source and drain regions in said p-well adjacent to said first gate structure; and forming an optional first set of suicide regions on, and in contact with, top surfaces of said n-type source and drain regions; forming a p-channel MOS transistor in said n-well comprising the steps: forming a second gate dielectric on a top surface of said n-well; forming a second gate structure on a top surface of said second gate dielectric; forming p-type source and drain regions in said n-well adjacent to said second gate structure; and forming an optional second set of suicide regions on, and in contact with, top surfaces of said p-type source and drain regions; forming an npn bipolar transistor in said substrate, comprising the steps: forming an n-type emitter, comprising an n-type emitter diffused region; forming a p-type base adjacent to said n-type emitter and including a region under said n-type emitter; and forming an n-type collector, comprising an n-type collector diffused region and an n-type buried collector region contacting the n-type collector diffused region and extending toward and possibly under said p-type base; forming contacts in said pre-metal dielectric layer stack on, and electrically connected to, said n-type source and drain regions, said p-type source and drain regions, said n-type collector, said p-type base, and said n-type emitter, wherein the contacts to said n-type emitter are configured in a plurality of contact islands.
9. The method of claim 8, wherein the step "forming an n-type emitter" further comprises the step forming a plurality of n-type emitter diffused regions.
10. The method of claim 9, wherein said contacts to said n-type emitter are configured in a plurality of contact islands in each said emitter diffused region.
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