KR20040023477A - Electrostatic discharge protection silicon controlled rectifier(esd-scr) for silicon germanium technologies - Google Patents

Abstract

PURPOSE: An electrostatic discharge protection silicon controlled rectifier(ESD-SCR) for silicon germanium technologies is provided to protect effectively an IC by using an ESD device having an SCR. CONSTITUTION: An ESD protection device has an SCR for protecting circuitry of an IC. The SCR includes a N-doped layer(208) disposed over a substrate(203) and a first P doped region(214) disposed over the N-doped layer. At least one first N+ doped region(216) forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.

Description

Electrostatic Discharge Protection Silicon Control Rectifiers (ESD-SCR) for Silicon Germanium Technology {ESC-STATIC DISCHARGE PROTECTION SILICON CONTROLLED RECTIFIER (ESD-SCR) FOR SILICON GERMANIUM TECHNOLOGIES}

This application claims the benefit of the invention described in US Provisional Application No. 60 / 318,550, filed Sept. 11, 2001, and US Application No. 10 / 238,699, Sept. 10, 2002, the contents of which are herein incorporated by reference. Are incorporated by reference.

FIELD OF THE INVENTION The present invention relates generally to the field of electrostatic discharge (ESD) protection circuits, and more particularly to silicon controlled rectifier (SCR) structures useful for ESD protection circuits.

Currently, technologies using high frequency signals such as mobile phones and other wireless devices are incorporating silicon germanium (SiGe) into integrated circuits (ICs). Silicon germanium technology gives chipmakers the ability to meet analog / RF design requirements, such as transistor speed, while maintaining high transistor current gain. The introduction of the SiGe layer onto the silicon layer (N-epitaxial layer) forms a HETEORJUNCTION therebetween. Thus, a heterojunction bipolar transistor (HBT) can be formed and integrated with a functional circuit, ie, a complementary metal oxide semiconductor (CMOS) circuit, on a chip. That is, HBT is used as a functional RF circuit, where the SiGe layer enables the fabrication of high speed transistors that can be used in RF applications.

Semiconductor devices, such as ICs with SiGe HBT transistors, are sensitive to the high voltages that can be encountered by contacting ESD generation. As described above, an electrostatic discharge (ESD) protection circuit is essential for an integrated circuit. ESD generation usually results from discharge of high voltage potentials (typically a few kilovolts) and causes short duration (typically 100 ns) high current (few amperes) pulses.

Recent studies have shown that functional heterojunction bipolar transistors also have some inherent ESD protection. For example, one publication found that without any additional ESD protection circuitry, a functional HBT has inherent ESD protection properties that are measurable, such as between two transistor terminals (eg, base-collector, base-emitter, etc.). It is starting. For a more detailed understanding of one such study, see "Electrostatic Discharge Characterization of Epitaxial-Base Silicon-Germanium Heterojunction Bipolar Transistors" by Electrical Overstress / Electrostatic Discharge Symposium 2000, EOS-22, pp.239- 250, IEEE Catalog No. 00TH8476, ISBN-1-58537-018-5).

However, the inherent ESD protection of functional heterojunction bipolar transistors is limited, so that ESD protection (voltage clamping and current performance) for the functional circuit may not be adequately provided. For example, the emitter-base junction can only adjust very limited ESD current until a disruptive failure occurs. One reason is that ESD stress current must flow from the base contact to the active base emitter junction. Thus, the current will flow in an extremely thin layer of SiGe (eg, 50 nm) connecting the base contact to the active transistor region. This not only causes significant voltage buildup at the device terminals, but also causes an initial failure, which improperly impairs the device in any ESD application of a protected RF receiver input where the base of the HBT is connected to the input terminal while the emitter is grounded. Make.

In addition, an additional reason for this low current ESD failure may be due to the long and narrow base polycrystalline silicon connection that is essential for the actual RF transistor layout. Along these base polycrystalline silicon connections, the resistance increases, while the voltage drops during ESD, which is not allowed. Accordingly, there is a need in the art for an improved ESD protection device in semiconductor technology using silicon-germanium technology.

The disadvantages thus far associated with the prior art are overcome by the present invention, which is an electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for the protection circuit of an integrated circuit (IC). SCRs include vertical NPN transistors and horizontal PNP transistors.

In one embodiment, an N-doped (eg, low doped or N-epitaxial) layer is disposed on the substrate and the first P doped region is disposed on the N-epitaxial layer. The first N + doped region is disposed on the P− doped region and coupled to ground. The first N + doped region, the first P− doped region and the N− epitaxial layer form a vertical NPN transistor of the SCR, where the first N + doped region forms a cathode of the SCR.

The second P doped region is coupled to the protective pad. The second P doped region forms an anode of the SCR, is disposed on the N-epitaxial layer, is positioned horizontally with respect to the first P doped region, and is electrically insulated from the first P doped region. The second P doped region, the N-epitaxial layer and the first P doped region form a horizontal PNP transistor of the SCR. The trigger device may be coupled to the gate of the SCR. For example, an external on-chip trigger device may be coupled to the gate of the SCR, which is on the same IC, but the trigger device does not share any components with the SCR. Optionally, an integrated trigger device may be coupled to the gate of the SCR, which not only shares at least one component with the SCR but also resides on the same IC.

In one embodiment, the first P-doped region is made of a silicon-germanium (SiGe) lattice. As described above, the vertical NPN transistor is a heterojunction bipolar transistor (HBT) and has a low junction capacitance between the base (SiGe layer) and the collector (N-epitaxial Si). The SCR incorporating the vertical HBT of the present invention is suitable for protecting circuit operation under high frequency applications such as circuits in wireless devices.

1A and 1B show a schematic embodiment of the SCR ESD protection device of the present invention.

2 shows a cross-sectional view of a first embodiment of the SCR ESD protection device of FIGS. 1A and 1B.

3 shows a top view of a second embodiment of the SCR ESD protection device of FIGS. 1A and 1B.

4 shows a cross-sectional view of a third embodiment of the SCR ESD protection device of FIGS. 1A and 1B.

5A and 5B show a cross-sectional view of the triggering device of the first embodiment of the present invention.

Figure 6 shows a cross sectional view of a second embodiment of a triggering device of the present invention.

7 shows a cross sectional view of a third embodiment of a trigger device of the invention.

8A-8C show schematic embodiments of the trigger device shown in FIGS. 6 and 7.

9 shows a schematic diagram of the SCR ESD protection device of FIG. 1B coupled to a shunt diode.

* Description of the main parts of the drawings *

100: integrated circuit 102: ESD protection device

103: SCR122: anode

124: cathode 142: resistance

205: N type buried layer 250: internal level dielectric (ILD)

514: P doped region 532: cathode terminal

602: N + emitter region 624: insulating layer

For ease of understanding, like reference numerals have been used to designate like elements common to the figures.

The process steps and structures detailed below do not form a complete process for manufacturing an integrated circuit (IC). Since the present invention may be practiced in conjunction with integrated circuit fabrication techniques currently used in the industry, some of the process steps that are generally carried out are included as necessary to aid the understanding of the present invention. During fabrication, drawings showing the cross section and layout of a portion of the IC are not drawn to scale, but to illustrate various features of the invention. Moreover, the figure includes a schematic diagram of a circuit (eg, an SCR circuit) associated with P and N type doped regions of an integrated circuit.

1A and 1B show a schematic embodiment of the SCR ESD protection device 102 of the present invention. Each of the embodiments of schematics a and b has an integrated circuit (IC) having a protected circuit (functional circuit) 101 and an SCR ESD protection device 102 coupled to the pad 104 of the protected circuit 101 ( A part of 100) is disclosed. Although the single pad 104 and the SCR ESD protection device 102 are shown in the schematic diagram, those skilled in the art will appreciate that additional ESD protection device 102 may be provided for other pads (e.g., for the functional circuit 101 of the IC 100) if necessary. For example, an I / O pad).

ESD protection device 102 includes an SCR 103 coupled between pad 104 and ground 112, which is coupled to an external on-chip triggering device 105. The triggering device 105 and the SCR 103 together act as a static discharge protection device 102 for the circuit (ie, functional circuit) 101 of the integrated circuit (IC) 100. In particular, the SCR 103 coupled with the triggering device 105 protects the IC circuit 101 from electrostatic discharge (ESD) that occurs at the pad 104 of the IC circuit 101. When turned on, SCR 103 functions as a shunt to allow any ESD current to flow from pad 104 to ground 112 through anode 122 and cathode 124 of SCR 103. . To quickly dissipate such overvoltage ESD conditions, the trigger device 105 "turns on", i.e., triggers the SCR.

The configuration of the SCR 103, the pad 104, the ground 112, and the protected circuit 101 are the same for both the embodiments shown in FIGS. 1A and 1B. Only the coupling of the triggering device 105 to the SCR 103 is the difference between the schematics of FIGS. 1A and 1B.

Referring to the exemplary schematic diagram of FIG. 1A, the SCR protection device 102 includes a PNP transistor QP 132 and an NPN transistor QN 131. In particular, the anode 122 of the SCR 103 is connected to the pad and optionally to the first side of the resistor R _N 142. Resistor R _N 142 is used to suppress unexpected triggering at low currents. Additionally, anode 122 is connected to emitter 108 of PNP transistor QP 132 that is parallel to shunt resistor R _N 142. Optionally, many series diodes D _S (not shown) may be connected between emitter 108 and anode 122 of PNP transistor QP 132. Diodes D _S (typically 1-4 diodes) connected in series are optionally provided to increase the holding voltage of the SCR 103 which may be needed to meet the latch-up specification.

The first node 134 includes the base of the PNP transistor QP 132, the other side of the resistor R _N 142 and the collector of the NPN transistor QN 131. In addition, the collector of the PNP transistor QP 132 is connected to the base of the NPN transistor QN 131 and one side of the resistor R _P 141 and forms a second node 136. The other side of the resistor R _P (141) is coupled to the third node 124 is coupled to ground 112. The Resistor R _P 141 is used to suppress unexpected triggering at low currents such as leakage currents. Moreover, the emitter of NPN transistor QN 131 is connected to grounded third node 124 and functions as the cathode of SCR 103.

Those skilled in the art will appreciate that resistors 141 and 142 may control the overall resistance of ground 112 and may control the triggering and holding current of SCR 103. Moreover, any leakage current from trigger device 105 is connected to ground 112 via a path through resistor 141.

The triggering device 105 in the schematic diagram of FIG. 1A is an external on-chip trick device 105 connected between the first node 134 and ground 112. In particular, the trigger device 105 is connected to the base of the PNP transistor QP 132, commonly referred to as the second gate G2 of the SCR 103. In another embodiment shown in FIG. 1B, the triggering device 105 is connected between the pad 104 and the second node 136. In particular, the trigger device 105 is connected to the base of the NPN transistor QN 131, commonly referred to as the first gate G1 of the SCR 103. In an embodiment, the trigger device 105 is considered to be "outside" of the SCR 103 because the trigger device 105 does not have any structural component in which the structural components of the SCR 103 are integrated. Another aspect of the invention provides SCR triggering through various embodiments of an external on-chip triggering diode using an HBT structure, as discussed with respect to FIGS. 5-9. Triggering of the SCR may be possible by using an internal trigger mechanism such as breakdown of the junction formed between the N-epitaxial layer and the first p-doped (p-base) region, as shown in FIG.

Various embodiments detailing the structure and doping material of the SCR are shown and discussed in connection with FIGS. 2-4. For example, an improved feature of the SCR of the present invention is a structural formation comprising a lateral bipolar transistor and a vertical bipolar transistor for forming the SCR 103. Another improved aspect of the present invention is the utilization of silicon germanium (SiGe) in SCR 103 to form a vertical heterojunction bipolar transistor (HBT).

2 shows a cross-sectional view of a first embodiment of the SCR ESD protection device of FIGS. 1A and 1B. The schematic diagram shown in FIG. 2 represents a component of the SCR 103, which corresponds to the schematic embodiment of FIGS. 1A and 1B. That is, FIG. 2 is shown and discussed with SCRs formed by side bipolar transistors and vertical bipolar transistors. Note that the trigger device 105 is not shown on the cross sectional view of FIG. 2.

In particular, the side bipolar transistor is formed by the PNP transistor (QP) 132, while the vertical bipolar transistor is formed by the NPN transistor (QN) 131. The SCR protection device 103 includes a P-type substrate 203, a buried N-doped layer (hereinafter referred to as an N-type buried layer (BLN)) 205, an N-doped layer (eg, Lightly doped or stacked with a doped layer comprising an N-epitaxial layer) 208 and at least one N + sinker region 206. The SCR ESD protection device also includes a first P doped region 214, at least one second P doped region 212, a first N + doped polysilicon region 216, and at least one second N + doped region. And 210.

On the silicon P-substrate 203, a heavily N-doped (e.g., 2 x 10 ¹⁹ atom / cm ^-3 ), highly conductive BLN 205 is formed. A slightly N-doped layer 208 (eg, 10 ¹⁶ to 10 ¹⁷ atoms / cm ⁻³ ), hereinafter referred to as “N-epitaxial layer 208 exemplarily” across the BLN 205 Isolation of the N-epitaxial layer 208 is provided by a ring of deep trench isolation (DTI) 219. That is, the deep trench is etched around the active device region and in particular It is filled with an insulating oxide such as silicon dioxide (SiO ₂ ).

Deep heavily N-doped regions (ie, N + sinker regions) 206 ₁ and 206 ₂ (collective N + sinker regions 206) are N-type dopants having a doping concentration of approximately 10 ¹⁸ atom / cm ⁻³ . It is formed adjacent to the DTI 219 by implanting a dopant. As such, a slightly N-doped layer 208 is formed over the BLN 205 and between the N-sinker regions 206. N + sinker region 206 is used to form a resistive connection under N + diffusion region 210 under BLN 205.

Shallow trench isolation (STI) 218 allows formation (eg, implantation / diffusion) of heavily-doped regions (e.g., second N + and P + doped regions 210,212), as shown in FIG. It is used to separate the area designated for the purpose. In particular, shallow trenches are etched in certain areas, and insulating material (eg, silicon dioxide (SiO ₂ ), etc.) is deposited in the shallow trenches. Regions 210 and 212 also cover other techniques known in the prior art that are useful for SCR operation as described in commonly assigned US patent application Ser. No. 10 / 007,833, filed November 5, 2001 and fully incorporated herein. Can be separated by.

As exemplarily shown in FIG. 2, the SCR 103 is preferably symmetric such that the cathode 124 is substantially centered between the two P + regions 212 ₁ and 212 ₂ forming the anode 122. And are formed, wherein each P + anode region 122 is on the opposite side of the cathode 124. Instead of providing only a single large P + region 212 to function as the anode 122, symmetry is preferably provided as a technique for saving real estate on the IC 100, thus making it more compact. And less area expenses. In addition, symmetry allows for a more efficient geometric arrangement that promotes increased current.

Note that the N + and P + implantation and heat cooling steps are performed after the STI region formation to form the only-doped N + and P + regions 210 and 212, respectively. Implantation is provided through separate photo masks for N + and P + to allow the dopant to only pass into the IC 100 dedicated area. Referring to FIG. 4, an area surrounding the cathode region 216, the first gate region 226, the anode region 212, and the second gate region 210 is shown to be covered by an insulating STI material during processing. .

During implantation, each N-sinker region in which second N + regions (N + diffusion regions) 210 ₁ and 210 ₂ (collectively second N + regions 210) form a second gate (G2) 134. 206 is provided above. Additionally, second P + regions (P + diffusion regions) 212 ₁ and 212 ₂ (collectively second P + regions 212) are over N-epitaxial layer 208 to form anode 122. Is provided. As shown in FIG. 2, the STI 218 electrically separates the second P + region 212 from the first P + region 214 as well as the second N + region 210 from the second P + region 212. Insulate

Vertical NPN transistor (QN) 131 has a first P doped region 214 formed over N-epitaxial layer 208 and a first N + polysilicon region 216 formed over first P doped region 214. It is formed by). In particular, the first N + polysilicon region (N + emitter) 216 and the first P doped region 214 form the emitter and base of the vertical NPN transistor (QN) 131, respectively. In addition, N-epitaxial layer 208, N-sinker region 206 and BLN 205 together form a collector of vertical NPN transistor (QN) 131. The first N + polysilicon region (emitter 216, as its name indicates, is typically an N + doped polysilicon material forming the cathode 124 of the SCR 103.

3 shows a top view of a second embodiment of the SCR ESD protection device of FIGS. 1A and 1B. 3 illustrates one embodiment of many possible arrangements of SCR elements to enhance performance by minimizing SCR transistor base widths and to maintain real area on IC 100. Many aspects shown in FIG. 3 can be applied to the embodiments shown in FIGS. 2 and 4 herein. For example, cathode 124 may comprise a plurality of first N + polysilicon regions (eg, 216 ₁ to 216 ₃ , collectively N + regions 216) that are linearly scattered over first P doped region 214. Is formed by. In addition, the trigger gate G1 formed by the P + polysilicon region 226 is scattered and aligned with the plurality of second N + polysilicon regions 216 over the first P doped region 214.

Similarly, anode 122 may be formed by a plurality of second P + polysilicon regions (not shown) that are linearly scattered over N-epitaxial layer 208. Moreover, the trigger gate G2 formed by the second N + doped region 210 is also scattered so that the plurality of second N + doped regions aligned with the plurality of second P + polysilicon regions on the N-epitaxial layer 208. Area (not shown).

Referring to FIG. 2, the side PNP transistor QP 132 may comprise at least one second P ⁺ doped region (eg, 212 ₁ and 212 ₂ , 212 as a whole), an N-epi region 208 with a BLN 205. ) And the first P doped region 214. The second P + doped region 212, the N-epi region 208 with the BLN 205 and the first P doped region 214 form the emitter, base and collector of the side PNP transistor QP 132. The second P + doped region 212 is in another embodiment a P + doped polysilicon material, and the second P + doped region 212 is made of a P + doped SiGe material, as will be discussed in more detail later. The dual function is used because the first P doped region 214 is formed as the base of the vertical NPN transistor QN 131 as well as the collector of the side PNP transistor QP 132. As such, the N-epi layer 208 and BLN 205 use a dual function because they form the base for the lateral PNP transistor QP 132 as well as the collector of the NPN transistor QN 131.

The first gate G1 136 is formed by at least one P + base polysilicon region 226 disposed on the first P doped region 214, respectively. In the embodiment shown in FIGS. 2 and 3, the first gate 136 may comprise a plurality of P + base poly regions (eg, regions 226 ₁ and 20) disposed on opposite sides of the first N + cathode polysilicon region 216. 226 ₂ ).

For example, referring to FIG. 3, first gate regions 226 ₁ and 226 ₂ are disposed adjacent to and between each of a plurality of first N + emitter polysilicon regions 216. That is, the first gate regions 226 ₁ and 226 ₂ are disposed not only between the first N + emitter regions 216 ₁ and 216 ₂ , but also between the first N + emitter polysilicon regions 216 ₂ and 216 ₃ . . Providing a plurality of first gate regions 226 in line with the N + emitter / cathode polysilicon regions 216 allows the anode region (i.e., the second P + doped region 212) to be placed in close proximity to the cathode so that the side size ( L _N ) may be reduced for faster turn on of the SCR 103 as will be discussed in further detail below with respect to FIG. 2.

Insulating regions 224 ₁ and 224 ₂ (eg, silicon dioxide (SiO ₂ )) remove first N + emitter polysilicon region 216 from P + base polysilicon region 226 of first gate 136. Insulate. In particular, insulating regions 224 ₁ and 224 ₂ are disposed on first P doped region 214 and between first N + emitter polysilicon regions 216 and P + polysilicon regions 226 ₁ and 226 ₂ . . It is noted that first N + emitter polysilicon region 216 is formed on portions of insulating regions 224 ₁ and 224 ₂ . In addition, a portion of the first N + emitter polysilicon region 216 disposed between the insulating regions 224 ₁ and 224 ₂ may be a window (ie, “emitter opening”) 230 as will be discussed in further detail below. ).

Optionally, silicon layer 220 may comprise first N + polysilicon region 216 (cathode), first gate region 226 (G1), second gate region 210 (G2), and second P + region ( 212) (anode). In particular, a metal layer (eg, using cobalt, titanium, etc.) is deposited on the surface of IC 100. During the heat treatment, a high conductivity alloy is formed between the metal and silicon ("silicide"). The silicide layer 220 is used as a conductive bond between the high doping regions 216, 210, 212 and 226 and the respective metal contacts, and the anode 122, the cathode 124, and the first gate of the SCR 103 ( 136 and second gate 134 provide external connection.

To complete the processing of the SCR of the present invention, an oxide layer known as internal level dielectric (ILD) 250 (shown in dashed lines) is deposited on the doped region. The etching process is performed to form contact holes which are subsequently filled with metal to form metal contacts. Some contact holes may be placed in rows on emitter opening 230 to increase the maximum current. It is noted that the total number of contact holes on anode 122 (ie, second P + region 212) approximately matches the number of cathodes 124 (ie, first N + polysilicon region 216).

In one embodiment of FIG. 2, all P and N type regions 210, 212, 214 and 216 are formed of a silicon-only lattice structure. In particular, the first and second doped regions 214 and 212 have a doping concentration of about 10 ²¹ atoms / cm ⁻³ . In addition to the first N + polysilicon region (emitter) 216 and the second N + region (second gate 210), the P + polysilicon region 226 has a doping concentration of about 10 ²¹ atoms / cm ⁻³ . The BLN layer 205 has a doping concentration of about 10 ¹⁹ atoms / cm ⁻³ , the N + sinker region 206 has a doping concentration of 10 ²⁰ atoms / cm ⁻³ , and the N- epitaxial layer 208 has a doping concentration of 10 10 atoms / cm ⁻³ . It has a doping concentration of ¹⁶ to 10 ¹⁷ atoms / cm ⁻³ , which is the lowest doping concentration of the protective device 103.

In the second embodiment of FIG. 2, the first P doped region 214 comprises a silicon germanium (SiGe) lattice structure. In particular, the first P doped region 214 is formed of silicon and germanium. The concentration gradually increases with layer depth up to a peak concentration of 0% to approximately 10-13%. Silicon concentration decreases from 100% to approximately 90-87% respectively. In addition, SiGe is doped with boron at a concentration of about 10 ¹⁹ atoms / cm ⁻³ . The remaining layers and regions of protective device 102 are as discussed above. The use of silicon germanium lattice structures is particularly suitable for circuits that operate under RF application, such as wireless chips and devices.

The implementation of SiGe HBT (ie vertical NPM transistor 131) has a very low junction capacitance that makes SCR suitable for high frequency (RF), because the parasitic junction capacitance of SCR 103 provides very high levels of ESD hardness. Can be minimized by having a low junction capacitance. In particular, the junction region between the base and the collector (ie, SiGe P doped region 214 and N-epi region 208 region) is defined by the emitter opening and thus minimized. In addition, the N-epi layer 208 (collector) is doped very low compared to standard non-epi semiconductor processing. Typical junction capacitance is 0.7 femto parads per micron squared area (compared to 1.6 femto parr per micron squared for P + / N wells per micron squared area). For one parasitic capacitance, such as one between the BLN and the P substrate or the sidewall (DTI) of the device, all capacitance values are minimized to meet the high frequency requirements for the functional HBT device.

In the third embodiment of FIG. 2, the first and second P doped regions 214 and 212 are each made of SiGe and doped with boron at a concentration of about 10 ¹⁹ cm ⁻³ . The joint formation of the first and second P doped regions 214 and 212 allows for easier manufacturing processing, thereby lowering the manufacturing cost. In addition, the performance of this third embodiment is the same as the second embodiment in which the second P doped region 212 is formed only of the silicon based lattice structure.

An object of the present invention is to speed up the speed at which the SCR 103 is turned on. In the prior art, the SCR 103 turn-on speed is reduced by two characteristic differences on the SCRs 103 formed of a pair of lateral bipolar transistors. One difference from the prior art is that the size of each base region of transistor QN 131 and transistor QN 132 of SCR 103 is reduced, which is not only the current gain β of transistors 131 and 132 but also SCR 103. ) 'S turn-on time. The increased transistor current gain β helps to be provided to each transistor QN 131 and transistor QN 132 with forward bias, thereby operating the SCR 103 quickly and reliably.

In FIG. 2, dimensions L _P and L _N represent the respective base lengths of the vertical NPN transistor QN 131 and the lateral PNP transistor QP 132. In an embodiment where the first P + doped region 214 comprises a crystal structure of silicon and germanium, the base length L _P of the NPN transistor QN 131 is in the range of 15-50 nm.

The base length L _P is the length measured from the edge 211 of the second P + region 212 to the emitter opening 230. As described above, the emitter opening 230 is formed as an N-epi region located below the first P + doped region 214 and is not covered by an insulating material (SiO ₂ ) 224. The size of the emitter opening 230 determines the cross section through which the current flows. In one embodiment, the base length L _N of PNP transistor QP 132 is in the range of 1.0 to 2.0 microns.

The SCR turn on time is a combination of turn on times of each of the transistor QN 131 and the transistor QP 132. The turn on time of the bipolar transistors 131 and 132 is proportional to the square of the base width of each of these transistors. Therefore, since the base width L _P of the NPN bipolar transistor was reduced by implementing the vertical NPN transistor QN 131, the SCR turn-on time was also greatly reduced compared to SCR having a pair of transistors formed horizontally.

Furthermore, in an embodiment using a SiGe lattice structure in the base of the vertical NPN transistor QN 131, the SiGe heterojunction transistor enables control of electrons and holes, respectively. As a result, the overall gain-bandwidth product f _max characterizing the maximum frequency of operation can be improved. The overall gain-bandwidth product f _max can be improved by two manufacturing methods. The first manufacturing method is to provide a high germanium concentration in a uniform base, while the second manufacturing method is to provide a low germanium concentration in a graded base.

In the first manufacturing method, the resistivity of the base layer is greatly reduced. In particular, the heterojunction at the base-emitter interface of NPN transistor QN 131 reduces the holes injected into the emitter, so that the current gain remains high. As measured by the emitter-collector pass time, the speed of the device is the same as that of a normal bipolar transistor, but greatly increases due to the large reduction in base-diffusion resistance with low gain-bandwidth. The first manufacturing method is most suitable for the electric power field.

In a second manufacturing method (which is a low germanium concentration in the grade base), the germanium varies from very low concentration at the emitter-base junction to about 10% at the collector-base junction of the NPN transistor QN 131. In this case, the current gain is only marginally affected. However, as measured by the emitter-collector pass time, the speed of the device increases due to the built-in field created by the germanium concentration gradient across the base. Moreover, base-width modulation (modulation of base-collector depletion layer width caused by changes in collector-base voltage) is reduced, but high current gain falloff is due to heterojunction at the collector-base interface. Increases. Thus, this second manufacturing method is best suited for small signal applications. The second manufacturing method technique has a defect with higher specific resistance in the base layer. Therefore, the ESD performance of the aforementioned conventional device is relatively low.

4 shows a cross-sectional view of a third embodiment of the SCR ESD protection device of FIGS. 1A and 1B. The embodiment shown in FIG. 4 is the same as the embodiment of FIG. 2 except that the BLN 205 and the N + sinker region are omitted and the N-well 406 is formed over the N-epi layer 208.

In particular, an N-epitaxial layer 208 is formed over the P-substrate 203, and the N-well 406 diffuses into the N-epi layer 208 and is horizontally insulated by the DTI 219. N-well 406 has an N-doped concentration of about 10 ¹⁸ atoms / cm ⁻³ , which is less than BLN 205. The first P doped region 214, the second P doped region 212, the second N + doped region 210, and the first N + doped region 216 may be formed of N-wells as described above with reference to FIG. 2. 406 is formed. The first P doped region 214 and the second P doped region 212 may also contain only silicon doped material or SiGe, as described above in connection with FIG. 2.

Removing the BLN 205 and including the N-well 406 prevents the possibility of worsening the current gain of the distributed horizontal PNP transistor QP 132 of the SCR 103. In particular, the deterioration of the current gain, due to the high doping concentration of the BLN 205, may offset the advantage of having a low resistance current path through the BLN 205. Thus, the diffused N-well 406 forms the base of the horizontal PNP transistor 132 (as well as the collector of the vertical NPN transistor 132) which minimizes the reduction in the current gain β.

In the alternative embodiment of FIGS. 2-4, an asymmetrical layout can also be implemented. In an asymmetrical layout, not only a single second P + doped region 212 (ie 212 ₁ ) can be used, but also a single second N + doped region 210 forms a first gate and a single P base poly region 226. Forms a second gate. As such, since the number of contact holes in anode 122 must substantially match the number of contact holes in cathode 124, anode 122 formed by P + region 212 ₁ is larger than the symmetric embodiment. Moreover, a DTI ring of insulating material is formed below the STI region close to where the second P + base polysilicon region 226 ₂ is formed. Thus, all elements on the right side of the ring can be omitted from the SCR 103. With regard to the performance of the preferred SCR layout, the ESD protection performance of the asymmetric SCR of the present invention can be compared with respect to current gain and SCR turn on time.

The SCR of this embodiment provides the PNP transistor QP 132 distributed (horizontally) in the vertical NPN transistor QN 131. Vertical NPN transistors have a reduced base length (L _P ) and vertical current flows from the emitter to the collector, which increases current gain, current flow, and turn-on time compared to SCRs with distributed (horizontal) NPN and PNP transistors. Let's do it.

When the base of the NPN transistor 131 includes silicon-germanium, the SCR 103 is insulated in the vertical direction from the P substrate 203 by a reverse diode formed by the BLN 205 and the P substrate 203 junction. Similarly, it is insulated laterally by the DTI 219. Thus, the SCR 103 can be used as an ESD protection device in a number of situations typically encountered with ICs used in RF applications such as wireless devices. In such an RF circuit, the signal can swing above the positive supply voltage or below the negative supply voltage. Protection device insulated from P substrate 203 because overshoot or undershoot of such signals occurs, since protection devices meet circuit requirements that no conduction path opens to the supply line or ground line. Is useful in both cases.

Additionally, in some ESD protection applications, the gate may be omitted entirely, or a single gate or two gates (ie, gates G1 or G2) may be required based on the circuitry of the IC 100 to be protected. For example, referring to FIG. 1A, only second gate G2 136 is used to trigger SCR 103 when protection against an ESD event occurs at pad 104. As such, the P + polysilicon region 226 forming the first gate G1 will not be required. Using only the second gate G2 134 is any potential that may arise by using the first gate G1 134 due to the side (trigger) current flowing through the SiGe base 214 of the NPN transistor 131. Prevent heating problems.

Similarly, referring to FIG. 1B, only the first gate G1 134 is used to trigger the SCR 103. As such, the N + region 210 and N + sinker region 206 forming the second gate G2 will not be required. By eliminating unused gates, the ESD protection device 102 has a more compact layout. In addition, trigger gate G1 136 is a simple and direct way to inject the trigger current into the high efficiency HBT base region, and also compared to using second gate G2 134 to trigger the side PNP transistor 132. Reduce the trigger speed of the SCR 102.

However, two gates G1 134 and G2 136 may also be implemented to provide a connection to an independent trigger device 105. In particular, there are cases where each gate can be used to trigger the SCR 103 and protect it from different types of ESD events. The ESD event may include a positive ESD event or a negative ESD event occurring at a particular pad, which occurs in different components of the functional circuit 101 among others.

As mentioned above, in different embodiments of the SCR 103, the trigger gate can be completely removed. Removing both gates, the IC layout can be made more compact because the N + sinker region 506, N + G2 region 510, and P + base polysilicon 522 are no longer required. Omission of both gates G1 and G2 may be applied where the trigger voltage of the SCR can be determined by avalanche breakdown of the heterojunction between the N-epi and P base layer SiGe.

5A and 5B show a cross-sectional view of a first embodiment of a diode trigger device 105. As described above, the SCR may be turned on (ie triggered) by the external on-chip trigger device 105. Since the SCR 103 and the trigger device 105 cannot both have any integrated or shared components, the trigger device 105 is external to the SCR. The triggering device described in FIGS. 5-9 is used in an SCR embodiment using a SiGe lattice structure in the first P doped region 214. That is, the trigger device of FIGS. 5-9 can be used when the vertical NPN transistor 131 is a heterojunction bipolar transistor (HBT).

Exemplary trigger device 105 (both shown in FIGS. 5A and 5B) is a heterojunction diode (HBD) trigger device 105 that employs a collector C to the base B breakdown of the heterojunction transistor HBT. . In particular, the HBD trigger device 105, as described above with respect to the SCR 103, includes a P-type substrate 203, a buried N doped layer (hereinafter referred to as a " buried layer N-type (BLN). 505), an N-epitaxial layer 508, and at least one N + sinker region 506. The HBD trigger device 105 also includes a SiGe doped region 514, at least one N + diffusion region 510, and at least one P + poly base region 522.

The structure of the trigger device 105 is similar in many respects to that of the SCR 103. In particular, high conductivity BLN 505 is formed on silicon P substrate 203. N-epitaxial layer 508 is formed over BLN 205. Side insulation of the N-epi layer 508 is provided by a deep trench isolation ring, such as silicon dioxide (SiO ₂ ), among others.

Deep high N doping regions (i.e., N + sinker regions 506 ₁ and 506 ₂ (collectively, N + sinker regions 506) inject N-type dopants as described above with respect to SCR 103). Thereby forming in proximity to the DTI 519. Thus, an N-epi layer 508 is formed over the BLN 205 and between the N + sinker regions 506. The N + sinker region 506 is an N + diffusion region. It is used to form a low-ohmic connection to BLN 505 down from 510. Shallow trench isolation (STI) 518 is highly doped as described above with respect to SCR 103. Used to distinguish regions designated for formation (eg implantation) of regions (eg, N + diffusion region 510 and SiGe P doped region 514).

N + implanting and annealing steps perform the following STI region formation to form a high doping N + region 510. During implantation, N + diffusion regions 510 ₁ and 510 ₂ (collectively, N + diffusion regions 510) are provided over each N + sinker region 506, and the cathode 532 of the heterojunction diode (collector contact of the HBT) Equivalent to).

5A and 5B, STI regions 518 ₁ and 518 ₂ insulate N + diffusion regions 510 ₁ , while STI regions 518 ₃ and 518 ₄ insulate N + diffusion regions 510 ₂ . Moreover, N-epi layer region 509 is maintained between STI regions 518 ₂ and 518 ₃ . In addition, a SiGe P doped region 514 is deposited over the N-epi layer region 509 adjacent to the STI regions 518 ₂ and 518 ₃ .

In FIG. 5A, P + base polysilicon region 522 is formed over P doped region 514, which collectively forms an anode 534 (equivalent to the base contact of HBT) of HBD 105. In one embodiment of FIG. 5A, P + base polysilicon region 522 is concentrated over P doped region 514 and N-epi layer 508. That is, anode 534 has a direct contact over active SiGe P doped region 514.

In FIG. 5B, the P + base polysilicon region 522 is divided into two regions 522 ₁ , 522 ₂ and each P + base polysilicon region 522 is laterally on the P doped region 514 and a SiGe P doped region. 514 is formed above the STI 518 formed below. As such, since the anode 534 indirectly contacts the active junction, the P base polysilicon regions 522 ₁ , 522 ₂ are located on the side of the active SiGe P doped region 514. In either of the embodiments, it should be noted that the high doped regions (N + diffusion and P + base polysilicon regions 510, 522 may optionally be silicides as described above with respect to SCR 103).

Note that in practice there is no current emitter contact area within the trigger device layout. Omission of the emitter contact region allows the vertical current to flow through the metallization, contact, silicide layer 520, and P + base polysilicon region 522 and into the thin film SiGe base layer 514. As such, SiGe P doped region (base) 514 forms an anode of HBD 105, while N + diffusion regions 510 ₁ , 510 ₂ , N + sinker regions 506 ₁ , 506 ₂ , and N-epi layer 508 forms the cathode of HBD 105. More particularly, highly doped BLN 505, N + sinker region 506, and N + diffusion region 510 (silicide layer 520) To ensure a low-resistive connection to the cathode terminal 532.

Reverse breakdown of the trigger diode 105 occurs at the P-N junction disposed below between the SiGe P-base and the N-epi layer region 50. Typically, the breakdown voltage of the HBD is in the region between 6 and 9 volts. During an ESD event, once the breakdown threshold voltage is met, the trigger diode 105 is turned on and supplies a trigger current to the gate 134 or 136 of the SCR 103 that triggers the SCR 103.

It should be noted that the junction capacitance is very low because the N-epi layer 508 is lightly doped (eg doping concentration is approximately 10 ¹⁶ to 10 ¹⁷ atoms / cm ⁻³ ). Low level doping in the N-epi layer 508 causes the depletion layer of the diode to expand into the silicon of the N-epi layer. Longer depletion layer widths are due to lower junction capacitance.

In alternative embodiments of FIGS. 5A and 5B, N-well regions 507 (virtually drawn) are formed in the N-epitaxial layer. N-well 507 is formed under SiGe P doped region 514. In particular, the N-well 507 extends laterally between the DTI regions 519 below the N + diffusion regions 510. Thus, N + sinker region 506 is no longer required. N-well 507 is provided with a lower trigger voltage by increasing the doping concentration (eg, 1018 atoms / cm-3) at the N-side of the junction. Higher doping concentrations lead to shorter depletion layer widths where the voltage drops due to high electric field strength. The latter leads to a high avalanche increase factor and low breakdown voltage.

8A-8C show schematic diagrams of an exemplary embodiment of the trigger device shown in FIGS. 6 and 7. Each schematic diagram shows that the trigger device 105 is coupled to an SCR collectively formed with an ESD protection device 102 that protects the functional circuitry on the IC 100. In addition, an external on-chip register 802 is coupled from the triggering device 105 to ground 112 at node 136.

6 shows a cross section of a second embodiment of the trigger device 105 of the present invention. 8A shows a collector-base diode of a heterojunction bipolar transistor HBT 105 having a shorted base-emitter. 8B shows a collector-emitter device with an open base. The structure shown in FIG. 6 can be used in any of the configurations shown in FIGS. 8A and 8B, depending on how the base terminal is externally connected.

In particular, FIG. 6 shows a trigger device 105 for a SiGe SCR utilizing a collector-emitter breakdown of a heterogeneous bipolar transistor (HBT). FIG. 6 is structurally identical to that shown in FIG. 5B except that an N + emitter region 602 is formed between the SiGe P doped region and the P base polysilicon regions 522 ₁ , 522 ₂ . More specifically, insulating layer 624 is formed between N + emitter region 602 and P base polysilicon regions 522 ₁ , 522 ₂ . As such, as described above with respect to SCR 103, emitter opening 630 is defined below the N + emitter region 602 and within the edge of insulating layer 624.

One of the advantages of combining the N + emitter region 602 into the trigger device 105 is to reduce the trigger voltage. In addition, the N + emitter region 602 essentially provides a more robust trigger component because the internal current is amplified, as well as the vertical current flows from the emitter to the collector. It is noteworthy that the collector is tied to a high potential in the ESD protection circuit, while both the base and emitter are coupled to the low potential of the HBT SCR 103 (eg, gate G1 136).

In the alternative embodiment of FIG. 6, N-well 604 (shown virtually) is provided in a manner similar to that described in FIGS. 5A and 5B. By increasing the doping concentration (eg 10 ¹⁸ atoms / cm ³ ) on the N side of the junction in the same manner as described above in FIGS. 5A and 5B, the N-well 604 triggers lower to the N-epi layer 508 Provide the voltage.

As discussed above, the structure shown in FIG. 6 may have a base externally coupled to an emitter (FIG. 8A) or floating (FIG. 8B). The advantage of the structure having an emitter coupled to the structure with collector-base breakdown (FIGS. 5A and 5B) (FIGS. 8A and 8B) is that as described above, it is a more robust trigger device. Shorting the base-emitter (FIG. 8A) causes a breakdown and triggering voltage for ESD protection device 102, which is typically 6-9 volts. The floating base (Figure 8B) typically results in a low breakdown voltage at 4-7 volts. Depending on the trigger voltage required for the specified application, an appropriate version (Figure 8A or 8B) can be selected.

7 shows a cross section of a second embodiment of the trigger device 105 of the present invention, and FIG. 8C shows an emitter base diode having an open collector, as shown in FIG. 7.

Referring to FIG. 7, the emitter-base diode trigger device is a SiGe SCR utilizing the base-emitter breakdown of a heterojunction bipolar transistor (HBT). As described above for the other trigger device embodiments of FIGS. 5 and 6, in particular, the BLN 505 and the N-epitaxial layer 508 are disposed on the P-substrate 203.

SiGe P-base layer 514 is formed on N-epi layer 508. However, an insulating material provided during the formation of the STI 518 is formed on the N-epi layer 508 to isolate the SiGe P-base layer 514 from the N-epi layer 508. By this, the base-collector junction of the HBT is removed from the trigger device 105. Thus, the trigger device 105 includes a base-emitter diode formed between the N + emitter region 602 and the SiGe P-base layer 514.

The embodiment of FIG. 7 has a lower breakdown voltage than the embodiments of FIGS. 5A, 5B, 6, 8A, and 8B. The low breakdown voltage of FIG. 7 is due to the heterojunction formed by the highly P doped SiGe base region 514 and the highly doped N + emitter region 602. As mentioned above, increasing the doping level reduces the breakdown voltage. The emitter base breakdown voltage of the trigger device of FIG. 7 typically ranges from 4 to 6 Volt.

Providing the SCR 103 with a structural formation comprising a vertical NPN transistor 131 connected with a horizontal PNP transistor reduces the turn-on time of the SCR 103. In particular, when compared to SCRs with distributed (ie horizontal) NPN transistors, the performance of the SCRs is improved by the high current flowing through the vertical NPN transistor 131. Moreover, fabricating the base of vertical NPN transistors using a silicon-germanium lattice allows the SiGe SCR 103 to be used in high frequency applications such as wireless devices. In particular, the P-doped SiGe base provides very low junction capacitance for the lower doped N-epi collector region underlying it, which is suitable for RF applications.

The triggering device 105 may also be manufactured using SiGe technology. In particular, the heterojunction diode is connected to the gate of the SCR such that the reverse breakdown voltage of the heterojunction diode defines the trigger voltage for the SCR. Although heterojunction triggering devices are desirable for high frequency applications, those skilled in the art will appreciate that other types of triggering devices may be connected to the SCR 103 in accordance with the present invention to trigger the SCR.

The use of the HDB device of FIGS. 5A, 5B, 6 and 7 as a trigger device for an ESD-SCR has been described. However, HBD devices can also be used as ESD protection devices. That is, the diode can be applied to shunt an ESD pulse with "opposite polarity". The opposite polarity here means that the pad connected to the protection circuit receives a negative ESD pulse with respect to ground. In this case, the diode (but not SCR) will provide a conductive path that safely discharges ESD generation.

9 shows the SCR ESD protection device of FIG. 1B coupled to a shunt diode 902. 9 illustrates the use of a shunt diode 902 to shunt an ESD pulse having an opposite polarity. 9 is similar to FIG. 1 in that the triggering device 105 is a diode, and the shunt diode 902 is connected to the pad 104 and the anode 122 of the SCR 103 and also to ground. In particular, the cathode of the trigger diode 105 is connected to ground 112 via a resistor 141 and the anode of the trigger diode 105 is connected to the pad 104. The cathode of the shunt diode 902 is then directly connected to ground 112, and the anode of the shunt diode 902 is connected to the pad 104.

A preferred embodiment for an application of the type shown in FIG. 9 is an HBD device 500 as shown in FIG. 5A. The embodiment shown in FIG. 5A shows a direct anode (base) contact that provides the lowest forward on-resistance, with the forward on-resistance making the contact most suitable as a shunt element. . The direct anode (base) contact of Figure 5A, unlike the prior art, which uses an indirect anode (base) contact that limits the flow of current, allows the maximum current to flow through the heterojunction. Other types of HBD diodes shown in FIGS. 5B, 6 and 7 can also be used as ESD shunt devices, but these embodiments are more suitable to be used as trigger devices for SCR. These other types of HBD diodes have low performance due to their high resistance and low current capacity, but are typically desirable as trigger devices due to their low breakdown voltage.

While the present invention has been described in detail with reference to preferred embodiments, it will be appreciated by those skilled in the art that the above embodiments are for the purpose of disclosure and that various modifications and changes can be made without departing from the spirit and scope of the invention.

The electrostatic discharge (ESD) protection device 102 provided with the silicon controlled rectifier (SCR) 103 of the present invention can improve the protection of the integrated circuit as compared with the prior art.

Claims (10)

An electrostatic discharge (ESD) protection device 102 having a silicon controlled rectifier (SCR), A substrate 203; An N-doped layer 208 disposed on the substrate; A first P-doped region 214 disposed on the N-doped layer; At least one first N + doped region 216 forming a cathode 124, the at least one first N + doped region disposed on the first P-doped region and connected to ground 112; The at least one first N + doped region, the first P-doped region and the N-doped layer form a vertical NPN transistor of the SCR; And At least one second P-doped region 212 forming an anode 122 of the SCR and connected to a protective pad 104, wherein the at least one second P-doped region is on the N-doped layer. A second P-doped region, the N-doped layer, and the first substrate; 1 P-doped region forming a horizontal PNP transistor (132) of the SCR. The electrostatic discharge protection device of claim 1, wherein the first P-doped region comprises a P-doped silicon-germanium material. The device of claim 1 or 2, wherein the at least one second P-doped region comprises a silicon-germanium material. The device of claim 1 or 2, further comprising a first gate (136) electrically connected to the first P-doped region. 5. The apparatus of claim 4, wherein said first gate comprises at least one P + polysilicon region (226). The device of claim 1 or 2, further comprising a second gate (134) electrically connected to the N-doped layer. 7. The electrostatic discharge protection circuit of claim 6, wherein the second gate comprises at least one second N + doped region (210) disposed on the N-doped layer. An electrostatic discharge (ESD) protection device having a heterojunction diode, An N-doped layer 508 disposed on the substrate; A P-doped region 514 disposed on said N-doped layer, said N-doped layer and said P-doped region forming a vertical PN diode; At least one P + polysilicon region 522 formed on the P-doped region and forming an anode 534 of the diode, wherein the at least one P + polysilicon region is located on the N-doped layer. Is formed directly over a portion of the P-doped region; At least one N + doped region 510 disposed on the N-doped layer and forming a cathode 532 of the diode; A shallow trench isolation portion (STI) formed between the at least one N + doped region and the P doped region; And And a deep trench isolation (DTI) ring that horizontally insulates the N-doped layer. As an electrostatic discharge (ESD) protection device, A silicon controlled rectifier (SCR) having an anode 122 connected to the pad 104 of the protection circuit 101 and a cathode 124 connected to ground 112, The SCR further comprises a plurality of doped regions (203, 208, 214, 216), wherein at least one of the doped regions comprises a silicon-germanium material. The method of claim 9, wherein the SCR, First vertical transistor 131; And And a second horizontal transistor (132) connected to the first vertical transistor, wherein the first vertical transistor and the second horizontal transistor form an anode and a cathode of the SCR, respectively.