WO2008038236A3 - A multi-transistor based non-volatile memory cell with dual threshold voltage - Google Patents

A multi-transistor based non-volatile memory cell with dual threshold voltage Download PDF

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Publication number
WO2008038236A3
WO2008038236A3 PCT/IB2007/053911 IB2007053911W WO2008038236A3 WO 2008038236 A3 WO2008038236 A3 WO 2008038236A3 IB 2007053911 W IB2007053911 W IB 2007053911W WO 2008038236 A3 WO2008038236 A3 WO 2008038236A3
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
channel region
access
diffusion regions
threshold voltage
Prior art date
Application number
PCT/IB2007/053911
Other languages
French (fr)
Other versions
WO2008038236A2 (en
Inventor
Michiel Slotboom
Duuren Michiel J Van
Nader Akil
Schaijk Robertus T F Van
Almudena Huerta
Original Assignee
Nxp Bv
Michiel Slotboom
Duuren Michiel J Van
Nader Akil
Schaijk Robertus T F Van
Almudena Huerta
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Michiel Slotboom, Duuren Michiel J Van, Nader Akil, Schaijk Robertus T F Van, Almudena Huerta filed Critical Nxp Bv
Priority to EP07826550A priority Critical patent/EP2074649A2/en
Publication of WO2008038236A2 publication Critical patent/WO2008038236A2/en
Publication of WO2008038236A3 publication Critical patent/WO2008038236A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

A multi-transistor based non- volatile memory cell Ml arranged on a semiconductor substrate 1 includes at least one access transistor ATI; AT2; AT2'; AT2' and at least one memory transistor TM2a; TM2b; TM2c; TM2d. The at least one access transistor is a 'normally-off ' transistor and includes first and second diffusion regions Sl, S2, an access channel region Rl, and an access gate AG. The access channel region is intermediate the first and second diffusion regions. The at least one memory transistor includes third and fourth diffusion regions S2, S3, a channel region R2, a charge trapping element O1-N-O2 and a control gate CG. The channel region is intermediate the third and fourth diffusion regions, and the charge trapping element is above the channel region with the control gate being arranged above the charge trapping element. The semiconductor substrate is of a first conductivity type. The at least one memory transistor is provided with a memory threshold voltage window with an upper limit above and a lower limit below zero Volt.
PCT/IB2007/053911 2006-09-29 2007-09-26 A multi-transistor based non-volatile memory cell with dual threshold voltage WO2008038236A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07826550A EP2074649A2 (en) 2006-09-29 2007-09-26 A multi-transistor based non-volatile memory cell with dual threshold voltage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06121535 2006-09-29
EP06121535.6 2006-09-29

Publications (2)

Publication Number Publication Date
WO2008038236A2 WO2008038236A2 (en) 2008-04-03
WO2008038236A3 true WO2008038236A3 (en) 2008-07-03

Family

ID=39125602

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/053911 WO2008038236A2 (en) 2006-09-29 2007-09-26 A multi-transistor based non-volatile memory cell with dual threshold voltage

Country Status (3)

Country Link
EP (1) EP2074649A2 (en)
CN (1) CN101523580A (en)
WO (1) WO2008038236A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2340561B1 (en) 2008-10-23 2012-12-12 Nxp B.V. Multi-transistor memory cell
CN102110658B (en) * 2009-12-29 2013-07-17 中芯国际集成电路制造(上海)有限公司 Method for fabricating dibit flash memory
CN104779169B (en) * 2015-04-22 2017-12-08 上海华力微电子有限公司 A kind of manufacture method of double work voltage FinFET structure device
KR102420014B1 (en) * 2015-09-18 2022-07-12 삼성전자주식회사 Non-volatile inverter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040156240A1 (en) * 1999-09-17 2004-08-12 Ichiro Fujiwara Method of erasing non-volatile semiconductor memory device and such non-volatile semiconductor memory device
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US20060023505A1 (en) * 2004-07-27 2006-02-02 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040156240A1 (en) * 1999-09-17 2004-08-12 Ichiro Fujiwara Method of erasing non-volatile semiconductor memory device and such non-volatile semiconductor memory device
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US20060023505A1 (en) * 2004-07-27 2006-02-02 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device

Also Published As

Publication number Publication date
CN101523580A (en) 2009-09-02
EP2074649A2 (en) 2009-07-01
WO2008038236A2 (en) 2008-04-03

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