WO2008035598A1 - Complementary mis semiconductor device - Google Patents

Complementary mis semiconductor device Download PDF

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WO2008035598A1
WO2008035598A1 PCT/JP2007/067735 JP2007067735W WO2008035598A1 WO 2008035598 A1 WO2008035598 A1 WO 2008035598A1 JP 2007067735 W JP2007067735 W JP 2007067735W WO 2008035598 A1 WO2008035598 A1 WO 2008035598A1
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semiconductor device
type transistor
type
type mosfet
threshold voltage
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PCT/JP2007/067735
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French (fr)
Japanese (ja)
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Koichi Terashima
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Nec Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • the present invention provides either one of a p-type transistor and an n-type transistor.
  • Vthl VFB + 2 (i) F + (qNt / Cox) (1)
  • FIG. 1 shows a part of the manufacturing procedure of the semiconductor device of the present invention.
  • the SOI substrate shown in FIG. 1A includes a support substrate 201, a buried oxide film layer 202, and an SOI layer 203.
  • FIG. 1B after the element isolation region 204 is formed on this SOI substrate, the SOI layer and the buried oxide film layer in the region where the p-type MOSFET is formed are removed by etching, and the support substrate is formed on the surface. Make the layer appear.
  • FIG. 1 shows a part of the manufacturing procedure of the semiconductor device of the present invention.
  • FIG. 1A shows a part of the manufacturing procedure of the semiconductor device of the present invention.
  • the SOI substrate shown in FIG. 1A includes a support substrate 201, a buried oxide film layer 202, and an SOI layer 203.
  • FIG. 1B after the element isolation region 204 is formed on this SOI substrate, the SOI layer and the buried oxide film layer in the region where the p-type MOSFET is
  • a substrate comprising a layer 805 and a second SOI layer 806 is prepared.
  • the first SOI layer 805 and the second SOI layer 806 are regions where an n-type MOSFET and a p-type MOSFET are formed, respectively, and the threshold voltage is determined by the final thickness.
  • Such a substrate can be obtained, for example, by changing the energy and dose of oxygen ion implantation between the n-type MOSFET region and the p-type MOSFET region in the SIMOX method using oxygen ion implantation.
  • CMOSFET both the n-type MOSFET and p-type MOSFET have an SOI structure, and the threshold voltage is controlled by the thickness of the SOI layer.
  • the region where the p-type MOSFET is formed has a Balta substrate structure with the (110) plane as the main surface, and the region where the n-type MOSFET is formed has the SOI structure with the (100) plane as the main surface. be able to.
  • Both p-type and n-type MOSFETs can be fully depleted SOI structures.
  • a metal gate electrode can be used as the gate electrode, and a high dielectric constant insulating film can be used as the gate insulating film.
  • a p-type MOSFET can be created on the (110) plane. Therefore, the threshold voltage is controlled by one type of electrode material symmetrically between the n-type MOSFET and the p-type MOSFET, and at the same time, the parasitic capacitance is reduced and the radiation resistance is improved.
  • a semiconductor device which achieves high speed can be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

In a complementary MIS semiconductor device, either a p-type MOSFET or an n -type MOSFET has a completely depleted SOI structure. In the complementary MIS semiconductor device, gate electrodes of the p-type MOSFET and the n-type MOSFET are composed of the same material. The material has a work function that permits the absolute value of the threshold voltage of the p-type MOSFET and that of the n-type MOSFET to be substantially the same, and the polarities to be opposite.

Description

明 細 書  Specification
相補型 MIS半導体装置  Complementary MIS semiconductor device
技術分野  Technical field
[0001] 本発明は、相補型 MIS半導体装置に関し、更に詳しくは、 p型 MOSFET及び n型 MOSFETの少なくとも一方が、完全空乏型 SOI構造を有する相補型 MIS半導体装 置に関する。  The present invention relates to a complementary MIS semiconductor device, and more particularly to a complementary MIS semiconductor device in which at least one of a p-type MOSFET and an n-type MOSFET has a fully depleted SOI structure.
背景技術  Background art
[0002] 近年、シリコンの MOS型電界効果トランジスタ（以下、「MOSFET」と!/、う）にお!/ヽ て、微細化の進展とともに、ゲート電極の空乏化による駆動電流の劣化が問題となつ ている。そのため、駆動能力の向上を目的として、ゲート電極の材料に、従来の多結 晶シリコンに代えて金属系材料を用いる技術、いわゆるメタルゲート技術が検討され ている。  In recent years, silicon MOS field-effect transistors (hereinafter referred to as “MOSFETs”! /, U) have become a problem due to the progress of miniaturization and deterioration of drive current due to depletion of the gate electrode. It has been. Therefore, for the purpose of improving the driving capability, a technique using a metal material instead of the conventional polycrystalline silicon as a material for the gate electrode, so-called metal gate technique, has been studied.
[0003] 一方、トランジスタの微細化に伴い、ゲート絶縁膜の薄膜化によるゲートリーク電流 の増加が問題となっている。そのため、消費電力の低減を目的として、ゲート絶縁膜 に高誘電率材料 (High— k材料)を用いて物理膜厚を厚くすることでゲートリーク電 流を低減することが検討されて!/、る。  On the other hand, with the miniaturization of transistors, an increase in gate leakage current due to the thinning of the gate insulating film has become a problem. Therefore, with the aim of reducing power consumption, it has been studied to reduce the gate leakage current by increasing the physical film thickness using a high dielectric constant material (High-k material) for the gate insulating film! /, The
[0004] メタルゲート電極に用いる材料として、純金属や金属窒化物あるいはシリサイド材料 等が検討されている力 いずれの場合においても、メタルゲート電極を形成する際に 、ゲート絶縁膜の劣化を引き起こさないこと、及び、 n型 MOSFET及び p型 MOSFE Tのしき!/、値電圧（スレッシュホールド電圧）を適切な値に設定可能であることが必要 である。つまり、 n型 MOSFETと p型 MOSFETとで、スレッシュホールド電圧（Vth) が対称であること、すなわち絶対値が同じで極性が異なること力 理想的な相補型 M OSトランジスタ（CMOSFET)動作にお!/、て重要である。  [0004] Pure metals, metal nitrides, silicide materials, etc. are studied as materials used for the metal gate electrode. In any case, the gate insulating film is not deteriorated when the metal gate electrode is formed. In addition, the threshold voltage of the n-type MOSFET and p-type MOSFET must be set to an appropriate value. In other words, the threshold voltage (Vth) is symmetrical between the n-type MOSFET and p-type MOSFET, that is, the absolute value is the same and the polarity is different. For ideal complementary MOS transistor (CMOSFET) operation! / Is important.
[0005] 低電力動作のデバイス用の CMOSFETにおいて、 ± 0. 5V以下のスレッシュホー ルド電圧を実現するためには、 n型 MOSFETでは仕事関数が Siのミツドギャップ（4 . 6eV)以下、望ましくは 4. 5eV以下の材料をゲート電極に用い、 p型 MOSFETで は仕事関数が Siのミツドギャップ（4· 6eV)以上、望ましくは 4. 7eV以上の材料をゲ ート電極に用いることが求められる。 [0005] In order to achieve a threshold voltage of ± 0.5V or less in a CMOSFET for devices operating at low power, the work function of an n-type MOSFET is less than the Si gap (4.6eV), preferably 4. A material of 5 eV or less is used for the gate electrode, and for p-type MOSFETs, a material with a work function of Si gap (4.6 · 6 eV) or more, preferably 4.7 eV or more is used. It is required to be used for a gate electrode.
[0006] 上記スレッシュホールド電圧を実現する手段として、 n型 MOSFETのゲート電極お よび p型 MOSFETのゲート電極にそれぞれ最適な仕事関数を持った金属あるいは 合金を用い、作り分けることでトランジスタのスレッシュホールド電圧を制御する方法（ デュアルメタルゲート技術）が提案されて!/、る。  [0006] As a means for realizing the above threshold voltage, the threshold voltage of the transistor is obtained by using a metal or an alloy having an optimum work function for the gate electrode of the n-type MOSFET and the gate electrode of the p-type MOSFET, respectively, and making them separately. A voltage control method (dual metal gate technology) has been proposed!
[0007] ί列えば、、 Digest of International Electron Devices Meeting, p.359, 2002には、 SiO 2上に形成した Taと Ruの仕事関数はそれぞれ 4. 15eVと 4. 95eVであり、この二つ の電極間で 0. 8eVの仕事関数変調が可能であると述べられて!/、る。  [0007] As shown in Digest of International Electron Devices Meeting, p.359, 2002, the work functions of Ta and Ru formed on SiO 2 are 4.15 eV and 4.95 eV, respectively. It is stated that a work function modulation of 0.8 eV is possible between the electrodes!
[0008] 一方、国際公開第 2006/001271号パンフレット及び Digest of International Elec tron Devices meeting, p.91, 2004には、多結晶シリコンからなるゲートパターンをニッ ケル (Ni)で完全にシリサイド化して得られるシリサイドゲート電極に関する技術が開 示されている。この技術では、ゲート絶縁膜として HfSiON高誘電率膜を有し、ゲート 電極として完全にシリサイド化された Niシリサイド電極を有する MOSFETの作製に おいて、結晶相の形成を利用して Niシリサイドの組成を制御することにより、広範囲 な実効仕事関数の制御が可能であることが記載されている。  [0008] On the other hand, in International Publication No. 2006/001271 pamphlet and Digest of International Electron Devices meeting, p.91, 2004, a gate pattern made of polycrystalline silicon was obtained by fully siliciding with nickel (Ni). Technologies related to silicided gate electrodes are disclosed. In this technology, the composition of the Ni silicide is utilized by making use of the formation of the crystalline phase in the fabrication of a MOSFET having a HfSiON high dielectric constant film as the gate insulating film and a fully silicided Ni silicide electrode as the gate electrode. It is described that a wide range of effective work functions can be controlled by controlling.
[0009] 図 11A〜； 11Cは、ニッケルシリサイドをゲート電極とする CMOSFETの製造段階を 順次に方法を示す図である。図 11Aにおいて、通常の MOSFETの製造方法にした がって、シリコン基板 101に、素子分離領域 102、ソース'ドレイン領域 103、ゲート絶 縁膜 104、多結晶シリコン層を有するゲート電極 105、ゲート側壁 106、層間膜 107 が形成されている。この段階では、ゲート電極 105は、その頭頂部が層間膜 107に覆 われておらず、多結晶シリコンの上部が露出した状態になっている。  [0009] FIGS. 11A to 11C are diagrams illustrating a method of sequentially manufacturing CMOSFETs using nickel silicide as a gate electrode. In FIG. 11A, in accordance with a normal MOSFET manufacturing method, an element isolation region 102, a source / drain region 103, a gate insulating film 104, a gate electrode 105 having a polycrystalline silicon layer, a gate sidewall, 106 and an interlayer film 107 are formed. At this stage, the top of the gate electrode 105 is not covered with the interlayer film 107, and the upper portion of the polycrystalline silicon is exposed.
[0010] 次に、図 11Bに示すように、ニッケル 108を全面に堆積する。このステップでは、 p型 MOSFETと n型 MOSFETとで、堆積するニッケルの厚さを変えてある。その後、熱 処理を行なってニッケルと多結晶シリコンを完全に反応させ、層間膜上に残った未反 応のニッケルをウエットエッチングで除去する。これにより、図 11Cに示すような CMO SFET力 S得られる。この CMOSFETにおいては、堆積したニッケルの厚さによって、 ゲート電極 109および 110のニッケルシリサイドの組成が決定される。例えば、 p型 M OSFETでは Ni3Si、 n型 MOSFETでは NiSiから成るゲート電極を形成することに よって、 ± 0. 3Vのスレッシュホールド電圧を実現できる。 Next, as shown in FIG. 11B, nickel 108 is deposited on the entire surface. In this step, the thickness of the deposited nickel is changed between the p-type MOSFET and the n-type MOSFET. Thereafter, heat treatment is performed to completely react nickel and polycrystalline silicon, and unreacted nickel remaining on the interlayer film is removed by wet etching. This gives a CMO SFET force S as shown in Figure 11C. In this CMOSFET, the composition of the nickel silicide of the gate electrodes 109 and 110 is determined by the thickness of the deposited nickel. For example, a gate electrode made of Ni3Si is used for p-type MOS FETs and NiSi is used for n-type MOSFETs. Therefore, a threshold voltage of ± 0.3V can be realized.
[0011] 上記のように、多結晶シリコンからなるゲートパターンを、ニッケルで完全にシリサイ ド化してシリサイドゲート電極を得る技術では、 CMOSFETのソース'ドレイン拡散領 域の不純物活性化のための高温熱処理を行った後に、多結晶シリコンからなるグー トパターンをサリサイドプロセスによってシリサイド化をする。このプロセスは、従来の C MOSFETプロセスとの整合性が高い。しかしながら、 p型 MOSFETと n型 MOSFE Tとでニッケルシリサイドの組成を変えるために、堆積するニッケルの膜厚を p型 MO SFETと n型 MOSFETで変えなければならず、製造プロセスが複雑になり、特に、微 細パターン部分にお!/、ては、 p型 MOSFETと n型 MOSFETとで堆積するニッケル の膜厚を制御するのが非常に困難である、という問題があった。 [0011] As described above, in the technique of obtaining a silicide gate electrode by fully siliciding a gate pattern made of polycrystalline silicon with nickel, high-temperature heat treatment for activating impurities in the source-drain diffusion region of the CMOSFET After performing the above, a goot pattern made of polycrystalline silicon is silicided by a salicide process. This process is highly consistent with the traditional C MOSFET process. However, in order to change the composition of nickel silicide between p-type MOSFET and n-type MOSFET, the deposited nickel film thickness must be changed between p-type MOSFET and n-type MOSFET, which complicates the manufacturing process. In particular, there was a problem that it was very difficult to control the thickness of the nickel deposited by the p-type MOSFET and the n-type MOSFET in the fine pattern area!
発明の概要  Summary of the Invention
[0012] 上記に鑑み、本発明は、一種類の電極材料を使用しながらもしきい値電圧が n型ト ランジスタと p型トランジスタとで対称に制御できる相補型 MIS半導体装置を提供する ことを目白勺とする。  In view of the above, it is an object of the present invention to provide a complementary MIS semiconductor device in which a threshold voltage can be controlled symmetrically between an n-type transistor and a p-type transistor while using one kind of electrode material. Say it.
[0013] 本発明は、第 1の態様において、 p型トランジスタ及び n型トランジスタの何れか一方  [0013] In the first aspect, the present invention provides either one of a p-type transistor and an n-type transistor.
1S 完全空乏型 SOI構造を有する相補型 MIS半導体装置において、前記 p型トラン ジスタ及び n型トランジスタのゲート電極が同一の材料で構成され、かつ前記材料は 、 p型トランジスタ及び n型トランジスタの閾値電圧の絶対値を実質的に同じとすること 力 Sできる仕事関数を有する材料である、ことを特徴とする半導体装置を提供する。  1S In a complementary MIS semiconductor device having a fully depleted SOI structure, the gate electrodes of the p-type transistor and the n-type transistor are made of the same material, and the material is a threshold voltage of the p-type transistor and the n-type transistor. There is provided a semiconductor device characterized by being a material having a work function capable of making the absolute value of S substantially the same.
[0014] 本発明は、第 2の態様において、 p型トランジスタ及び n型トランジスタの何れか一方  [0014] In the second aspect, the present invention provides either one of a p-type transistor and an n-type transistor.
1S 完全空乏型 SOI構造を有する相補型 MIS半導体装置において、前記 p型トラン ジスタ及び n型トランジスタのゲート電極が同一の材料で構成され、かつ前記材料は 、 p型トランジスタ及び n型トランジスタの閾値電圧の絶対値のうち、大きい方の絶対 値と小さ!/、方の絶対値との差力 大き!/、方の絶対値の 20%以下とすることができる仕 事関数を有する材料である、ことを特徴とする半導体装置を提供する。  1S In a complementary MIS semiconductor device having a fully depleted SOI structure, the gate electrodes of the p-type transistor and the n-type transistor are made of the same material, and the material is a threshold voltage of the p-type transistor and the n-type transistor. The absolute value of the larger one is smaller! /, The difference between the absolute value of the larger one! /, And a material having a work function that can be 20% or less of the absolute value of the first, A semiconductor device is provided.
[0015] 本発明は、第 3の態様において、 p型トランジスタ及び n型トランジスタの双方力 完 全空乏型 SOI構造を有する相補型 MIS半導体装置にお!/、て、前記 p型トランジスタ 及び n型トランジスタの SOI層が異なる膜厚を有し、前記 p型トランジスタ及び n型トラ ンジスタのゲート電極が同一の材料で構成され、かつ前記材料は、 p型トランジスタ及 び n型トランジスタの閾値電圧の絶対値を実質的に同じにすることができる仕事関数 を有する材料である、ことを特徴とする半導体装置を提供する。 [0015] In the third aspect, the present invention provides a complementary MIS semiconductor device having a fully depleted SOI structure in which both a p-type transistor and an n-type transistor are combined! The SOI layers of the transistors have different thicknesses, and the p-type transistor and the n-type transistor The gate electrodes of the transistors are made of the same material, and the material has a work function capable of making the absolute values of the threshold voltages of the p-type transistor and the n-type transistor substantially the same. A semiconductor device is provided.
[0016] 本発明の上記、及び、他の目的、特徴及び利益は、図面を参照する以下の説明に より明らかになる。 [0016] The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the drawings.
図面の簡単な説明  Brief Description of Drawings
[0017] [図 1]図 1A〜； IEは、本発明の第 1の実施形態例に係る半導体装置の製造段階を順 次に示す断面図である。  [0017] FIG. 1A to FIG. 1E are cross-sectional views sequentially showing manufacturing steps of a semiconductor device according to a first embodiment of the present invention.
[図 2]図 2は、本発明の第 1の実施形態例に係る半導体装置の断面図である。  FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.
[図 3]図 3は、ニッケルシリサイドの組成と仕事関数との関係を示すグラフである。  FIG. 3 is a graph showing the relationship between the composition of nickel silicide and the work function.
[図 4]図 4は、第 1の実施形態例に係る半導体装置におけるチャネル濃度とスレッシュ ホールド電圧との関係を示すグラフである。  FIG. 4 is a graph showing the relationship between channel concentration and threshold voltage in the semiconductor device according to the first embodiment.
[図 5]図 5は、第 1の実施形態の変形例に係る半導体装置の断面図である。  FIG. 5 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.
[図 6]図 6は、第 1の実施形態の変形例に係る半導体装置の図 4と同様な図面である FIG. 6 is a drawing similar to FIG. 4 of a semiconductor device according to a modification of the first embodiment.
〇 Yes
[図 7]図 7A及び 7Bは、本発明の第 2の実施形態例に係る半導体装置の製造工程段 階を順次に示す断面図である。  FIGS. 7A and 7B are cross-sectional views sequentially showing manufacturing process steps of a semiconductor device according to a second embodiment of the present invention.
[図 8]図 8A〜8Cは、本発明の第 3の実施形態例に係る半導体装置の製造工程段階 を順次に示す断面図である。  FIGS. 8A to 8C are cross-sectional views sequentially showing manufacturing process steps of a semiconductor device according to a third embodiment of the present invention.
[図 9]図 9は、第 3の実施形態例に係る半導体装置の断面図である。  FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment.
[図 10]図 10は、第 3の実施形態の変形例に係る半導体装置の断面図である。  FIG. 10 is a cross-sectional view of a semiconductor device according to a modification of the third embodiment.
[図 11]図 11A〜； 11Cは、従来の半導体装置の製造工程段階を順次に示す断面図 である。  [FIG. 11] FIGS. 11A to 11C are cross-sectional views sequentially showing manufacturing process steps of a conventional semiconductor device.
好適な実施形態  Preferred embodiment
[0018] 本発明の理解を容易にするために、本発明の実施形態例の説明に先立って、本発 明の原理を説明する。  [0018] In order to facilitate understanding of the present invention, the principle of the present invention will be described prior to the description of the embodiments of the present invention.
一般に、 MOSFETのしきい値電圧は、完全空乏型の SOI構造では式（1)の Vthl で表わされ、式（2)で表わされる部分空乏型 SOIあるいはバルタ構造の MOSFET の Vth2よりも絶対値が小さくなる。 In general, the threshold voltage of a MOSFET is represented by Vthl in Equation (1) for a fully depleted SOI structure, and partially depleted SOI or Balta structure MOSFET represented by Equation (2). The absolute value is smaller than Vth2.
Vthl =VFB + 2 (i) F + (qNt/Cox) ( 1 )  Vthl = VFB + 2 (i) F + (qNt / Cox) (1)
Vth2 =VFB + 2 (i) F + 2 (q ε Si FN) l/2/Cox (2)  Vth2 = VFB + 2 (i) F + 2 (q ε Si FN) l / 2 / Cox (2)
(VFBはフラットバンド電圧、 （i> Fは Siのフェルミ電位、 qは電気素量、 Nはチャネル不 純物濃度、 tは SOI膜厚、 Coxはゲート絶縁膜容量、 ε Siは Siの誘電率を示す） また、スレッシュホールド電圧はゲート電極材料の仕事関数によって決まるから、ゲ ート電極材料として適当な仕事関数を持つものを選び、 p型あるいは n型のスレッシュ ホールド電圧の絶対値の大きい方だけを SOI構造とすることによって、 1種類のゲー ト電極材料を使って、 p型 MOSFETと n型 MOSFETのスレッシュホールド電圧の絶 対値を同じにすることができる。また、式（1 )および（2)からわ力、るように、 MOSFET のスレッシュホールド電圧はチャネルドーピングの濃度や、 SOI構造にした場合には SOIの膜厚によっても変化する。したがって、 SOI構造とするだけではスレッシュホー ルド電圧が所望の値に十分近づかない場合には、さらに SOIの膜厚を調整したり、 チャネルドーピングの濃度を調整したりすることによって、スレッシュホールド電圧を 調整すること力 Sでさる。  (VFB is a flat band voltage, (i> F is the Fermi potential of Si, q is the elementary charge, N is the channel impurity concentration, t is the SOI film thickness, Cox is the gate insulating film capacitance, ε Si is the Si dielectric) In addition, since the threshold voltage is determined by the work function of the gate electrode material, a gate electrode material having an appropriate work function is selected, and the absolute value of the p-type or n-type threshold voltage is large. By using only one of the SOI structures, the absolute value of the threshold voltage of the p-type MOSFET and the n-type MOSFET can be made the same by using one type of gate electrode material, and Equation (1) As shown in (2) and (2), the threshold voltage of the MOSFET also varies depending on the channel doping concentration and the SOI film thickness when the SOI structure is used. If the threshold voltage is not close enough to the desired value, use the force S to adjust the threshold voltage by further adjusting the SOI film thickness or the channel doping concentration.
[0019] 以下、本発明の実施形態例を、以下に図面を参照して詳細に説明する。  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.
[0020] <第 1の実施形態例〉  <First Embodiment>
図 1から図 6を参照して第 1の実施形態例の半導体装置について説明する。図 1は 、本発明の半導体装置の製造手順の一部を示したものである。本発明においては、 まず、図 1Aに示すような SOI基板を用意する。図 1Aの SOI基板は、支持基板 201、 埋め込み酸化膜層 202、 SOI層 203より構成されている。次に図 1Bに示すように、こ の SOI基板に素子分離領域 204を形成した後に、 p型 MOSFETが形成される領域 の SOI層と埋め込み酸化膜層をエッチングによって除去して、表面に支持基板層が 現れるようにする。次に図 1 Cに示すように、図 1Bで露出した支持基板層の上に、 Si 層 205をェピタキシャル成長させる。この時、 n型 MOSFETが形成される領域は、 Si がェピタキシャル成長しないように、シリコンの酸化膜等で覆っておく。ここまでで、 p 型 MOSFETが形成される領域は通常のバルタ基板構造、 n型 MOSFETが形成さ れる領域は SOI構造とすることができる。 [0021] なお、このような基板は、酸素のイオン注入を用いた方法、すなわち SIMOX法とし て知られている方法を用いて作ることもできる。その場合には、 p型 MOSFETが形成 される領域をマスクで覆うことによって、 n型 MOSFETが形成される領域にのみ酸素 イオンが注入されるようにしてから、酸素イオン注入を行ない、その後熱処理を行なう ことによって、 n型 MOSFETが形成される領域にのみ SOI層を形成することができるThe semiconductor device of the first embodiment will be described with reference to FIGS. FIG. 1 shows a part of the manufacturing procedure of the semiconductor device of the present invention. In the present invention, first, an SOI substrate as shown in FIG. 1A is prepared. The SOI substrate shown in FIG. 1A includes a support substrate 201, a buried oxide film layer 202, and an SOI layer 203. Next, as shown in FIG. 1B, after the element isolation region 204 is formed on this SOI substrate, the SOI layer and the buried oxide film layer in the region where the p-type MOSFET is formed are removed by etching, and the support substrate is formed on the surface. Make the layer appear. Next, as shown in FIG. 1C, an Si layer 205 is epitaxially grown on the support substrate layer exposed in FIG. 1B. At this time, the region where the n-type MOSFET is formed is covered with a silicon oxide film or the like so that Si does not grow epitaxially. Up to this point, the region where the p-type MOSFET is formed can be a normal Balta substrate structure, and the region where the n-type MOSFET is formed can be an SOI structure. [0021] Note that such a substrate can also be formed by a method using oxygen ion implantation, that is, a method known as a SIMOX method. In that case, the region where the p-type MOSFET is formed is covered with a mask so that oxygen ions are implanted only into the region where the n-type MOSFET is formed, and then oxygen ion implantation is performed, followed by heat treatment. By doing so, the SOI layer can be formed only in the region where the n-type MOSFET is formed.
〇 Yes
[0022] また、本発明の半導体材料については特に限定されることはない。以下の説明で は一般的なシリコンを例に挙げて説明する力 これに限定されることはなぐ例えばシ リコン.ゲノレマニウムなどを用いることも可能である。  [0022] The semiconductor material of the present invention is not particularly limited. In the following description, the force is described by taking a general silicon as an example. It is also possible to use, for example, silicon.
[0023] 次に、通常の CMOSFETの製造工程に従って、図 1Dに示すような p型 MOSFET と n型 MOSFETを形成する。ここで、 206はゲート絶縁膜、 207は多結晶シリコンの ゲート電極、 208はゲート側壁、 209は層間膜、 210はソース'ドレイン領域である。 図 1Dにおいて、ゲート電極 207は、その頭頂部が層間膜 208に覆われておらず、多 結晶シリコンの上部が露出した状態になっている。  Next, a p-type MOSFET and an n-type MOSFET as shown in FIG. 1D are formed according to a normal CMOSFET manufacturing process. Here, 206 is a gate insulating film, 207 is a polycrystalline silicon gate electrode, 208 is a gate sidewall, 209 is an interlayer film, and 210 is a source / drain region. In FIG. 1D, the top of the gate electrode 207 is not covered with the interlayer film 208, and the upper part of the polycrystalline silicon is exposed.
[0024] 次に図 1Eに示すように、ニッケル 211を全面に堆積する。この時、 p型 MOSFETと n型 MOSFETとで、堆積するニッケルの厚さを変えておく必要はない。その後、熱処 理を行なってニッケルと多結晶シリコンを完全に反応させ、層間膜上に残った未反応 のニッケルをウエットエッチングで除去すると、図 2に示すような CMOSFETが得られ る。図 2において、 301はシリコンの支持基板、 302はェピタキシャル成長したシリコ ン層、 303は SOI層、 304は埋め込み酸化膜層である。 p型 MOSFETはバルタ上に 、 n型 MOSFETは SOI上に形成されており、 305は素子分離領域、 306はソース 'ド レイン領域、 307はゲート絶縁膜、 308はゲート側壁、 309は層間膜である。ゲート電 極 310は、ニッケルシリサイドで、 p型 MOSFETも n型 MOSFETも同じ組成である。  Next, as shown in FIG. 1E, nickel 211 is deposited on the entire surface. At this time, it is not necessary to change the thickness of the deposited nickel between the p-type MOSFET and the n-type MOSFET. Then, heat treatment is performed to completely react the nickel and polycrystalline silicon, and the unreacted nickel remaining on the interlayer film is removed by wet etching to obtain a CMOSFET as shown in FIG. In FIG. 2, 301 is a silicon support substrate, 302 is an epitaxially grown silicon layer, 303 is an SOI layer, and 304 is a buried oxide layer. The p-type MOSFET is formed on the Balta, the n-type MOSFET is formed on the SOI, 305 is an element isolation region, 306 is a source drain region, 307 is a gate insulating film, 308 is a gate sidewall, and 309 is an interlayer film. is there. The gate electrode 310 is nickel silicide, and both the p-type MOSFET and the n-type MOSFET have the same composition.
[0025] 図 3は、ニッケルシリサイド電極を HfSiON上に形成した場合の、仕事関数 (Work  [0025] Figure 3 shows the work function when a nickel silicide electrode is formed on HfSiON.
Function)を、ニッケルシリサイドの組成に対してプロットしたものである。この図力、 らわかるとおり、ニッケルシリサイドの組成を変えることによって、仕事関数が 4. 4〜4 . 8eVの範囲で変化する。  Function) is plotted against the composition of nickel silicide. As can be seen from this graph, the work function varies in the range of 4.4 to 4.8 eV by changing the composition of nickel silicide.
[0026] 図 4は、図 2に示した CMOSFETのスレッシュホールド電圧を調べるために、ゲート 絶縁膜を HfSiON (膜厚 1. 7nm)として、ゲート電極の仕事関数を 4. 7eVとした時 のスレッシュホールド電圧を、チャネルの不純物濃度を横軸にとって、バルタ基板の 場合と SOI基板（SOI膜厚 15nm)の場合とで比較したものである。図 3との比較から 、これはゲート電極材料を Ni2Siとした場合に相当する。 SOI構造とすることによって 、スレッシュホールド電圧の絶対値はバルタの場合よりも下がることがわかる。また、 p 型 MOSFETをバルタ基板に、 n型 MOSFETを SOI基板に形成した時に、図に示 すように、 p型 MOSFETはチャネル濃度約 3 X 1017cm— 3の時にスレッシュホール ド電圧が—0. 5V、 n型 MOSFETはチャネル濃度約 9 X 1016cm— 3の時にスレツ シュホールド電圧が 0· 5Vとなり、ちょうど p型 MOSFETと n型 MOSFETのスレツシ ュホールド電圧が対称、すなわち絶対値が同じで極性が反対となることがわかる。し たがって、図 2に示した構造の CMOSFETにおいて、ゲート絶縁膜を HfSiON、ゲ ート電極を Ni2Siとすることによって、 1種類のゲート電極材料で、スレッシュホールド 電圧が対称となるような CMOSFETが得られる。 [0026] FIG. 4 shows the gates to investigate the threshold voltage of the CMOSFET shown in FIG. The threshold voltage when the insulating film is HfSiON (thickness 1.7 nm) and the work function of the gate electrode is 4.7 eV, with the impurity concentration of the channel as the horizontal axis, and the SOI substrate (SOI film) This is a comparison with the case of a thickness of 15 nm. Compared with Fig. 3, this corresponds to the case where the gate electrode material is Ni2Si. It can be seen that by using the SOI structure, the absolute value of the threshold voltage is lower than that of Baltha. When the p-type MOSFET is formed on the Balta substrate and the n-type MOSFET is formed on the SOI substrate, as shown in the figure, the p-type MOSFET has a threshold voltage of -0 when the channel concentration is about 3 X 1017 cm-3. The 5V, n-type MOSFET has a threshold voltage of 0.5V when the channel concentration is about 9 X 1016cm—3. The threshold voltage of the p-type MOSFET and n-type MOSFET is exactly the same, that is, the absolute value is the same and the polarity is opposite. It turns out that it becomes. Therefore, in the CMOSFET having the structure shown in FIG. 2, the gate insulating film is made of HfSiON and the gate electrode is made of Ni2Si, so that a CMOSFET having a single gate electrode material and a symmetrical threshold voltage can be obtained. can get.
[0027] 図 2に示した CMOSFETでは p型がバルタ、 n型が SOIであった力 S、本発明の第 1 の実施形態例においては、 SOI構造にする MOSFETは p型と n型のいずれでも良 い。図 5に示すのは、図 1A〜1Eに示した方法と同様の製造方法によって、 p型 MO SFETを SOI上に、 n型 MOSFETをバルタ上に形成した、図 2の CMOSFETの変 形例である。シリコンの支持基板 601上に、ェピタキシャル成長したシリコン層 602と 、 SOI層 603、埋め込み酸化膜層 604が形成され、素子分離領域 605、ソース'ドレ イン領域 606、ゲート絶縁膜 607、ゲート側壁 608、層間膜 609、ゲート電極 610が 形成されている。 In the CMOSFET shown in FIG. 2, the force S is that the p-type is Balta and the n-type is SOI. In the first embodiment of the present invention, the MOSFET having the SOI structure is either p-type or n-type. But it ’s okay. Fig. 5 shows a variation of the CMOSFET in Fig. 2 in which a p-type MOSFET is formed on SOI and an n-type MOSFET is formed on a butter using the same manufacturing method as shown in Figs. 1A to 1E. is there. An epitaxially grown silicon layer 602, an SOI layer 603, and a buried oxide film layer 604 are formed on a silicon support substrate 601, and an element isolation region 605, a source / drain region 606, a gate insulating film 607, and a gate sidewall 608 are formed. An interlayer film 609 and a gate electrode 610 are formed.
[0028] 図 6は、図 5に示した CMOSFETのスレッシュホールド電圧を調べるために、ゲート 絶縁膜を HfSiON (膜厚 1. 7nm)として、ゲート電極の仕事関数を 4. 5eVとした時 のスレッシュホールド電圧を、チャネルの不純物濃度を横軸にとって、バルタ基板の 場合と SOI基板（SOI膜厚 15nm)の場合とで比較したものである。図 3との比較から 、これはゲート電極材料を NiSiとした場合に相当する。 SOI構造とすることによって、 スレッシュホールド電圧の絶対値はバルタの場合よりも下がることがわかる。また、 p型 MOSFETを SOI基板に、 n型 MOSFETをバルタ基板に形成した時に、図に示すよ うに、 p型 MOSFETはチャネル濃度約 5 X 1016cm— 3の時にスレッシュホールド電 圧が— 0. 5V、 n型 MOSFETはチャネル濃度約 4 X 1017cm— 3の時にスレッシュ ホールド電圧が 0· 5Vとなり、ちょうど p型 MOSFETと n型 MOSFETのスレッシュホ 一ルド電圧が対称、すなわち絶対値が実質的に同じで極性が反対となることがわか る。したがって、図 5に示した構造の CMOSFETにおいて、ゲート絶縁膜を HfSiON 、ゲート電極を NiSiとすることによって、 1種類のゲート電極材料で、スレッシュホール ド電圧が対称となるような CMOSFETが得られる。 FIG. 6 shows the threshold when the gate insulating film is HfSiON (film thickness: 1.7 nm) and the work function of the gate electrode is 4.5 eV in order to investigate the threshold voltage of the CMOSFET shown in FIG. The hold voltage is compared between the case of a Balta substrate and the case of an SOI substrate (SOI film thickness 15 nm), with the channel impurity concentration on the horizontal axis. Compared with Fig. 3, this corresponds to the case where the gate electrode material is NiSi. It can be seen that by using the SOI structure, the absolute value of the threshold voltage is lower than that of Baltha. In addition, when a p-type MOSFET is formed on an SOI substrate and an n-type MOSFET is formed on a Balta substrate, it is shown in the figure. The p-type MOSFET has a threshold voltage of -0.5 V when the channel concentration is about 5 X 1016 cm—3, and the n-type MOSFET has a threshold voltage of 0.5 V when the channel concentration is about 4 X 1017 cm—3. It can be seen that the threshold voltage of the p-type MOSFET and n-type MOSFET are symmetrical, that is, the absolute values are substantially the same and the polarities are opposite. Therefore, in the CMOSFET having the structure shown in FIG. 5, by using HfSiON as the gate insulating film and NiSi as the gate electrode, a CMOSFET having a symmetric hold voltage can be obtained with one kind of gate electrode material.
[0029] 本発明の第 1の実施形態及びその変形例では、 HfSiONをゲート絶縁膜、 Ni2Si をゲート電極とした力 ゲート絶縁膜およびゲート電極の材料は、 p型 MOSFETn型 の MOSFETのスレッシュホールド電圧がほぼ対称となれば良いので、他の材料の 組み合わせでも良い。その際、 SOI構造にしたことによるスレッシュホールド電圧の変 化量と、ゲート電極として用いる材料の仕事関数とから、最適な材料が決定できる。ま た、第 1の実施形態例では、ニッケルシリサイドをゲート電極とする場合を説明するた めに、多結晶シリコンのゲート電極を形成してから、ニッケルを堆積していた力 他の 材料、例えば、タングステンを電極とするような場合には、多結晶シリコンの代わりに 直接タングステン電極を形成しても良レ、。  [0029] In the first embodiment of the present invention and its modification, the force gate insulating film and the gate electrode material using HfSiON as the gate insulating film and Ni2Si as the gate electrode are the threshold voltages of the p-type MOSFET n-type MOSFET. Since it is sufficient if is substantially symmetrical, a combination of other materials may be used. At that time, the optimum material can be determined from the amount of change in the threshold voltage due to the SOI structure and the work function of the material used as the gate electrode. Further, in the first embodiment, in order to explain the case where nickel silicide is used as the gate electrode, the force of depositing nickel after forming the gate electrode of polycrystalline silicon, for example, other materials such as When tungsten is used as an electrode, it is also possible to form a tungsten electrode directly instead of polycrystalline silicon.
[0030] さらに、本発明においては、 SOI層の膜厚を変化させたり、チャネル部分へのドー ビング濃度を変えたりすることによって、さらに正確にスレッシュホールド電圧の値を 調整すること力 Sでさる。  [0030] Furthermore, in the present invention, the force S can be adjusted more accurately by adjusting the threshold voltage value more accurately by changing the film thickness of the SOI layer or changing the doping concentration to the channel portion. .
[0031] <第 2の実施形態例〉  <Second Embodiment>
次に、本発明の第 2の実施形態例を図 7A及び 7Bを参照して説明する。第 2の実 施形態例においては、まず、図 7Aに示すように、支持基板 801、素子分離領域 802 、第 1の埋め込み酸化膜層 803、第 2の埋め込み酸化膜層 804、第 1の SOI層 805、 および第 2の SOI層 806からなる基板を用意する。ここで、第 1の SOI層 805と第 2の SOI層 806は、それぞれ n型 MOSFETおよび p型 MOSFETが形成される領域であ り、最終的な厚さによってスレッシュホールド電圧が決定される。このような基板は、例 えば、酸素イオン注入を用いた SIMOX法において、 n型 MOSFET領域と p型 MO SFET領域とで酸素イオン注入のエネルギーおよびドーズ量を変えることによって得 ること力 Sでさる。 Next, a second embodiment of the present invention will be described with reference to FIGS. 7A and 7B. In the second embodiment, first, as shown in FIG. 7A, a support substrate 801, an element isolation region 802, a first buried oxide film layer 803, a second buried oxide film layer 804, and a first SOI A substrate comprising a layer 805 and a second SOI layer 806 is prepared. Here, the first SOI layer 805 and the second SOI layer 806 are regions where an n-type MOSFET and a p-type MOSFET are formed, respectively, and the threshold voltage is determined by the final thickness. Such a substrate can be obtained, for example, by changing the energy and dose of oxygen ion implantation between the n-type MOSFET region and the p-type MOSFET region in the SIMOX method using oxygen ion implantation. The power S
[0032] その後、第 1の実施形態例で示したのと同様の方法によって、 MOSFETを形成す ると、図 7Bに示すように、ソース'ドレイン領域 807、ゲート絶縁膜 808、ゲート電極 8 09、ゲート側壁 810、および層間膜 811を備えた CMOSFETが得られる。この CM OSFETにおいては、 n型 MOSFETと p型 MOSFETがともに SOI構造になっており 、 SOI層の厚さによってスレッシュホールド電圧が制御される。  Thereafter, when a MOSFET is formed by a method similar to that shown in the first embodiment, as shown in FIG. 7B, a source / drain region 807, a gate insulating film 808, a gate electrode 8 09 A CMOSFET having a gate sidewall 810 and an interlayer film 811 is obtained. In this CM OSFET, both the n-type MOSFET and p-type MOSFET have an SOI structure, and the threshold voltage is controlled by the thickness of the SOI layer.
[0033] なお、本実施形態例にお!/、ても、第 1の実施形態例と同様に、ゲート絶縁膜および ゲート電極の材料は特定の材料に限定されるものではなぐ p型 MOSFETn型の M OSFETのスレッシュホールド電圧がほぼ対称となるような材料の組み合わせであれ ば良い。また、スレッシュホールド電圧をさらに調整するためにチャネルドーピングの 濃度を変えることもできる。  [0033] In this embodiment example, however, the material of the gate insulating film and the gate electrode is not limited to a specific material, as in the first embodiment example. Any combination of materials that makes the MOS FET's threshold voltage almost symmetrical is acceptable. It is also possible to change the channel doping concentration to further adjust the threshold voltage.
[0034] 以上のように、本第 2の実施形態例においては、 n型 MOSFETと p型 MOSFETが ともに SOI構造になっているので、一種類の電極材料でスレッシュホールド電圧を n 型 MOSFETと p型 MOSFETとで対称に制御すると同時に、寄生容量の低下や放 射線耐性の向上を実現し、トランジスタ特性を向上させることができる。  As described above, in the second embodiment, since the n-type MOSFET and the p-type MOSFET both have the SOI structure, the threshold voltage is set to be different between the n-type MOSFET and the p-type with one kind of electrode material. At the same time as symmetrical control with the MOSFET, it is possible to improve the transistor characteristics by reducing parasitic capacitance and improving radiation resistance.
[0035] <第 3の実施形態例〉  <Third Embodiment>
本発明の第 3の実施形態例を、図 8A〜8C、図 9、図 10を参照して説明する。図 8 A〜8Cは、本発明の第 3の実施形態例の半導体装置の製造工程を順次に示したも のである。第 3の実施形態例においては、まず、図 8Aに示すように、（110)面を主面 とする支持基板 901の上に、埋め込み酸化膜層 902を挟んで（100)面を主面とする SOI層 903が具備されているような基板を用意する。このような基板は、ハイブリッド 基板と呼ばれるもので、 （110)面を主面とするゥエーハと（100)面を主面とするゥェ ーハを、酸化膜を介して張り合わせることによって得ることができる。なお、本発明に おいて（110)面または（100)面と言った場合には、面方位が実質的に（110)あるい は（100)および結晶学的にそれらと等価な面方位であることを意味しており、面方位 が（110)ある!/、は（100)と完全に一致しなければいけな!/、と!/、うものではな!/、。  A third embodiment of the present invention will be described with reference to FIGS. 8A to 8C, FIG. 9, and FIG. 8A to 8C sequentially show the manufacturing steps of the semiconductor device according to the third embodiment of the present invention. In the third embodiment, first, as shown in FIG. 8A, the (100) surface is defined as the main surface on the support substrate 901 having the (110) surface as the main surface with the buried oxide film layer 902 interposed therebetween. A substrate having an SOI layer 903 to be prepared is prepared. Such a substrate is called a hybrid substrate, and is obtained by bonding a wafer having a (110) plane as a main surface and a wafer having a (100) plane as a main surface through an oxide film. Can do. In the present invention, when referring to the (110) plane or (100) plane, the plane orientation is substantially (110) or (100) and crystallographically equivalent plane orientation. It means that there is a (110) plane orientation! /, Must match exactly (100)! /, And! /, Not a thing! /.
[0036] 次に、第 2の実施形態例で示したのと同様に、このハイブリッド基板に素子分離領 域 904を形成した後に、 p型 MOSFETが形成される領域の SOI層と埋め込み酸化 膜層をエッチングによって除去して、表面に支持基板層が現れるようにする。そして、 図 8Cに示すように、図 8Bで露出した支持基板層の上に、 Si層 905をェピタキシャノレ 成長させる。この時、 n型 MOSFETが形成される領域は、 Siがェピタキシャル成長し ないように、シリコンの酸化膜等で覆っておく。このようにすると、 p型 MOSFETが形 成される領域は（110)面を主面とするバルタ基板構造、 n型 MOSFETが形成される 領域は（100)面を主面とする SOI構造とすることができる。 Next, as shown in the second embodiment, after forming the element isolation region 904 on the hybrid substrate, the SOI layer and the buried oxide in the region where the p-type MOSFET is formed are formed. The film layer is removed by etching so that the support substrate layer appears on the surface. Then, as shown in FIG. 8C, an Si layer 905 is epitaxially grown on the support substrate layer exposed in FIG. 8B. At this time, the region where the n-type MOSFET is formed is covered with a silicon oxide film or the like so that Si does not grow epitaxially. In this way, the region where the p-type MOSFET is formed has a Balta substrate structure with the (110) plane as the main surface, and the region where the n-type MOSFET is formed has the SOI structure with the (100) plane as the main surface. be able to.
[0037] 次に、第 1および第 2の実施形態例で示したのと同様の方法によって、図 9に示す ような CMOSFETが得られる。この CMOSFETにおいては、シリコンの支持基板 10 01上に、ェピタキシャル成長したシリコン層 1002と、 SOI層 1003、埋め込み酸化膜 層 1004が形成され、素子分離領域 1005、ソース'ドレイン領域 1006、ゲート絶縁膜 1007、ゲート側壁 1008、層間膜 1009、ゲート電極 1010が形成されている。図 9に 示す構造は、 p型 MOSFETが（110)面に形成されている以外は、第 1の実施形態 例の図 2に示した CMOSFETと同じ構造であり、スレッシュホールド電圧は面方位に 依存しないことから、第 1の実施形態例と同様に、一種類の電極材料でスレッシュホ 一ルド電圧を n型 MOSFETと p型 MOSFETとで対称に制御することができる。  Next, a CMOSFET as shown in FIG. 9 is obtained by the same method as shown in the first and second embodiments. In this CMOSFET, an epitaxially grown silicon layer 1002, an SOI layer 1003, and a buried oxide layer 1004 are formed on a silicon support substrate 1011, and an element isolation region 1005, a source / drain region 1006, and a gate insulating film are formed. 1007, a gate sidewall 1008, an interlayer film 1009, and a gate electrode 1010 are formed. The structure shown in Fig. 9 is the same as the CMOSFET shown in Fig. 2 of the first embodiment except that the p-type MOSFET is formed on the (110) plane, and the threshold voltage depends on the plane orientation. Therefore, as in the first embodiment, the threshold voltage can be controlled symmetrically between the n-type MOSFET and the p-type MOSFET with one kind of electrode material.
[0038] また、第 3の実施形態例においては、第 1の実施形態例で示したのと同様に、 p型 MOSFETを SOI構造、 n型 MOSFETをバルタ構造とすることもできる。この場合に は、図 8Aの SOI基板の代わりに、支持基板が（100)面、 SOI層が（110)面を主面と する SOI基板を用意して、 CMOSFETを形成する。図 9の CMOSFETを得たのと 同様の方法で、図 10に示すような、 p型 MOSFETが SOI構造、 n型 MOSFETがバ ルク構造に形成された、図 9の CMOSFETの変形例を得ることができる。この CMO SFETは、図 9の CMOSFETと同様に、シリコンの支持基板 1101上に、ェピタキシ ャル成長したシリコン層 1102と、 SOI層 1103、埋め込み酸化膜層 1104が形成され 、素子分離領域 1105、ソース'ドレイン領域 1106、ゲート絶縁膜 1107、ゲート側壁 1108、層間膜 1109、ゲート電極 1110が形成されている力 p型 MOSFETが（110 )面を主面とする SOI構造、 n型 MOSFETが（100)面を主面とするバルタ構造に形 成されている。  [0038] In the third embodiment, the p-type MOSFET may have an SOI structure and the n-type MOSFET may have a butter structure, as in the first embodiment. In this case, instead of the SOI substrate in FIG. 8A, an SOI substrate having a (100) plane as the support substrate and a (110) plane as the SOI layer as the main surface is prepared, and a CMOSFET is formed. In the same way as the CMOSFET shown in Fig. 9 was obtained, a modified example of the CMOSFET shown in Fig. 9 was obtained, as shown in Fig. 10, with the p-type MOSFET formed in the SOI structure and the n-type MOSFET formed in the bulk structure. Can do. Like the CMOSFET of FIG. 9, this CMO SFET has an epitaxially grown silicon layer 1102, an SOI layer 1103, and a buried oxide film layer 1104 formed on a silicon support substrate 1101, an element isolation region 1105, a source 'The drain region 1106, the gate insulating film 1107, the gate sidewall 1108, the interlayer film 1109, and the gate electrode 1110 are formed. The p-type MOSFET is the SOI structure with the (110) plane as the main surface. The n-type MOSFET is (100) It is formed in a Balta structure with the main surface as the main surface.
[0039] 図 10に示す構造においても、 p型 MOSFETが（110)面に形成されている以外は 、第 1の実施形態例の図 2に示した CMOSFETと同じ構造であり、スレッシュホール ド電圧は面方位に依存しないことから、第 1の実施形態例と同様に、一種類の電極材 料でスレッシュホールド電圧を n型 MOSFETと p型 MOSFETとで対称に制御するこ と力 Sできる。 [0039] Also in the structure shown in FIG. 10, except that the p-type MOSFET is formed on the (110) plane. Since this is the same structure as the CMOSFET shown in FIG. 2 of the first embodiment and the threshold voltage does not depend on the plane orientation, one kind of electrode material is used as in the first embodiment. The force S can be controlled symmetrically between the n-type MOSFET and p-type MOSFET.
[0040] なお、本第 3の実施形態例においても、第 1および第 2の実施形態例と同様に、ゲ ート絶縁膜およびゲート電極の材料は特定の材料に限定されるものではなぐ p型 M OSFETと n型 MOSFETのスレッシュホールド電圧がほぼ対称となるような材料の組 み合わせであれば良い。また、スレッシュホールド電圧をさらに調整するために、 SOI の膜厚を変えたり、チャネルドーピングの濃度を変えたりすることもできる。  [0040] In the third embodiment, as in the first and second embodiments, the material of the gate insulating film and the gate electrode is not limited to a specific material. P Any combination of materials may be used so that the threshold voltage of the n-type MOSFET and n-type MOSFET is almost symmetrical. It is also possible to change the SOI film thickness or channel doping concentration to further adjust the threshold voltage.
[0041] 本実施形態例では、 p型 MOSFETが実質的に（110)面または（110)面と結晶学 的に等価な面を主面とする面上に形成されているため、（100)面に形成した場合よ りも移動度が増大し、結果として、一種類の電極材料でスレッシュホールド電圧を n型 MOSFETと p型 MOSFETとで対称に制御すると同時に、トランジスタの駆動電流増 加と高速化が実現できる。  [0041] In the present embodiment example, the p-type MOSFET is formed on a surface whose principal surface is a (110) plane or a crystallographically equivalent plane to the (110) plane. As a result, the threshold voltage is controlled symmetrically between the n-type MOSFET and p-type MOSFET with one type of electrode material, and at the same time, the transistor drive current is increased and the speed is increased. Can be realized.
[0042] 以上説明したように、本発明の実施形態例では、 p型 MOSFETあるいは n型 MOS FETのどちらか一方を完全空乏型の SOI構造とすることによって、しきい値電圧スレ ッシュホールド電圧を p型 MOSFETと n型 MOSFETとで対称、すなわち絶対値が 実質同一で極性が反対とすることができる。したがって、一種類の電極材料でしきい 値電圧を n型 MOSFETと p型 MOSFETとで対称に制御した、相補型電界効果型ト ランジスタを有する半導体装置を提供することができる。  As described above, in the embodiment of the present invention, the threshold voltage threshold voltage is set to p by setting either the p-type MOSFET or the n-type MOS FET to a fully depleted SOI structure. Type MOSFET and n-type MOSFET are symmetrical, that is, the absolute value is substantially the same and the polarity is opposite. Therefore, it is possible to provide a semiconductor device having a complementary field effect transistor in which the threshold voltage is controlled symmetrically by an n-type MOSFET and a p-type MOSFET with one kind of electrode material.
[0043] 以上で説明したように、本発明は、以下の構成を採用することが出来る。  [0043] As described above, the present invention can employ the following configurations.
p型 MOSFETと n型 MOSFETの両方を完全空乏型の SOI構造とすることができる 。また、ゲート電極としてメタルゲート電極を用い、ゲート絶縁膜として高誘電率絶縁 膜を用いること力できる。さらに、 p型 MOSFETを（110)面に作成することができる。 したがって、一種類の電極材料でしき!/、値電圧を n型 MOSFETと p型 MOSFETと で対称に制御すると同時に、寄生容量の低下や放射線耐性の向上を実現し、なお かつ低消費電力化や高速化を実現した半導体装置を提供することができる。  Both p-type and n-type MOSFETs can be fully depleted SOI structures. In addition, a metal gate electrode can be used as the gate electrode, and a high dielectric constant insulating film can be used as the gate insulating film. Furthermore, a p-type MOSFET can be created on the (110) plane. Therefore, the threshold voltage is controlled by one type of electrode material symmetrically between the n-type MOSFET and the p-type MOSFET, and at the same time, the parasitic capacitance is reduced and the radiation resistance is improved. A semiconductor device which achieves high speed can be provided.
[0044] p型、 n型の両方が完全空乏型 SOI構造を有する相補型 MIS半導体装置において 、前記相補型 MIS半導体装置の p型 MOSFET、 n型 MOSFETの SOI層力 それ ぞれ異なる膜厚で構成され、前記相補型 MIS半導体装置の p型、 n型のゲート電極 が同一の材料で構成され、かつ前記材料は、 p型 MOSFET、 n型 MOSFETの閾値 電圧の絶対値を実質同一とすることができる仕事関数を有する材料である構成が採 用できる。また、 p型 MOSFET、 n型 MOSFETの両方が完全空乏型 SOI構造を有 する相補型 MIS半導体装置にお!/、て、前記相補型 MIS半導体装置の p型 MOSFE T、 η型 MOSFETの SOI層力 それぞれ異なる膜厚で構成され、前記相補型 MIS 半導体装置の p型 MOSFET、 n型 MOSFETのゲート電極が同一の材料で構成さ れ、かつ前記材料は、 p型 MOSFET、 n型 MOSFETの閾値電圧の絶対値のうち、 大き!/、方の絶対値と小さレ、方の絶対値の差が、大き!/、方の絶対値の 20%以下とす ることができる仕事関数を有する材料である構成が採用できる。 SOI構造にした場合 の MOSFETのスレッシュホールド電圧は、 SOIの膜厚によっても変化するから、 p型 MOSFETと n型 MOSFETの両方を SOI構造として、 SOI膜厚によってスレッシュホ 一ルド電圧を変化させることもできる。このような構造にすることによって、 1種類のゲ ート電極材料を使って、 p型 MOSFETと n型 MOSFETのスレッシュホールド電圧の 絶対値を同じにすることができるだけでなぐ p型 MOSFETも n型 MOSFETも、短チ ャネル効果抑制、寄生容量低減、耐放射線特性向上など、 SOIの利点を生かすこと ができる。 In a complementary MIS semiconductor device in which both p-type and n-type have a fully depleted SOI structure The p-type MOSFET of the complementary MIS semiconductor device and the SOI layer force of the n-type MOSFET are configured with different film thicknesses, and the p-type and n-type gate electrodes of the complementary MIS semiconductor device are made of the same material. In addition, it is possible to adopt a configuration in which the material is a material having a work function capable of making the absolute values of the threshold voltages of the p-type MOSFET and the n-type MOSFET substantially the same. In addition, both p-type MOSFETs and n-type MOSFETs are used in complementary MIS semiconductor devices having a fully depleted SOI structure! /, P-type MOSFE T of the complementary MIS semiconductor device, SOI layer of η-type MOSFET The gate electrodes of the complementary MIS semiconductor device p-type MOSFET and n-type MOSFET are made of the same material, and the material is the threshold voltage of the p-type MOSFET and n-type MOSFET. The absolute value of the large! /, The difference between the absolute value of the smaller and the absolute value of the one, the material having a work function that can be less than 20% of the absolute value of the larger! / A configuration can be employed. When the SOI structure is used, the threshold voltage of the MOSFET also changes depending on the thickness of the SOI. Therefore, both the p-type MOSFET and the n-type MOSFET can be changed to the SOI structure, and the threshold voltage can be changed depending on the SOI thickness. it can. This structure makes it possible not only to make the absolute value of the threshold voltage of the p-type MOSFET and the n-type MOSFET the same by using one type of gate electrode material, but the p-type MOSFET is also n-type. MOSFETs can also take advantage of SOI, such as suppressing the short channel effect, reducing parasitic capacitance, and improving radiation resistance.
[0045] また、ゲート電極の材料は、 Niと Siの化合物であることが望ましい。前述したように、 MOSFETのスレッシュホールド電圧はゲート電極材料の仕事関数によって決定され るのであるから、バルタと SOIとでちようどスレッシュホールド電圧が対称となるような 仕事関数を持つ金属材料を使うことが本発明では望ましい。また、 Niと Siの化合物で あるニッケルシリサイドは、仕事関数が組成によって制御でき、従来の MOSFETの 製造プロセスとの親和性も良いので、本発明の半導体装置の電界効果トランジスタ の一部に用いられるゲート電極の材料として好ましい。  [0045] The material of the gate electrode is preferably a compound of Ni and Si. As described above, since the threshold voltage of the MOSFET is determined by the work function of the gate electrode material, use a metal material having a work function that makes the threshold voltage symmetric as in Balta and SOI. This is desirable in the present invention. In addition, nickel silicide, which is a compound of Ni and Si, can be controlled by composition and has good compatibility with the conventional MOSFET manufacturing process, so it is used as a part of the field effect transistor of the semiconductor device of the present invention. It is preferable as a material for the gate electrode.
[0046] さらに、本発明の半導体装置の電界効果トランジスタの一部は、ゲート絶縁膜が高 誘電率絶縁膜であることが好ましぐこのゲート絶縁膜は、 Hfを含む高誘電率膜であ ることが特に好ましい。ゲート絶縁膜を高誘電率絶縁膜とすることによって、 1種類の ゲート電極材料を使って、 p型 MOSFETと n型 MOSFETのスレッシュホールド電圧 の絶対値を同じにした上で、さらに、ゲートリーク電流を低減し、低消費電力の半導 体装置を提供することができる。なお、本明細書において、「高誘電率絶縁膜」とは、 一般にゲート絶縁膜として用いられている二酸化珪素（Si〇2)に比べて誘電率が高 V、絶縁膜と!/、う意味であって、その誘電率の具体的数値は限定されな!/、。 [0046] Further, in some of the field effect transistors of the semiconductor device of the present invention, the gate insulating film is preferably a high dielectric constant insulating film. The gate insulating film is a high dielectric constant film containing Hf. It is particularly preferable. By making the gate insulating film a high dielectric constant insulating film, one kind of It is possible to provide a semiconductor device with low power consumption by reducing the gate leakage current while using the gate electrode material to make the absolute value of the threshold voltage of the p-type MOSFET and n-type MOSFET the same. it can. In this specification, the term “high dielectric constant insulating film” means that the dielectric constant is higher than that of silicon dioxide (Si02), which is generally used as a gate insulating film, and that it is! / And the specific value of the dielectric constant is not limited! /
[0047] さらに、 p型 MOSFETの半導体活性層の表面が実質的な（110)面または（110) 面と結晶学的に等価な面であり、 n型 MOSFETの半導体活性層の表面が実質的な (100)面または（100)面と結晶学的に等価な面であることが好ましい。このような p型 MOSFETと n型 MOSFETとで異なる結晶面を用いた MOSFETは、ハイブリッド基 板として知られている方法を用いて作製することができる。半導体中の正孔の移動度 は、（100)面内よりも（110)面内の方が大きいので、本発明において、 p型 MOSFE Tを実質的な（110)面または（110)面と結晶学的に等価な面上に作ることによって、 1種類のゲート電極材料を使って、 p型 MOSFETと n型 MOSFETのスレッシュホー ルド電圧の絶対値を同じにした上で、さらに、駆動電流の増大によるトランジスタ性能 向上を実現することができる。  [0047] Furthermore, the surface of the semiconductor active layer of the p-type MOSFET is a substantially (110) plane or a plane that is crystallographically equivalent to the (110) plane, and the surface of the semiconductor active layer of the n-type MOSFET is substantially The (100) plane or a plane that is crystallographically equivalent to the (100) plane is preferable. Such a MOSFET using different crystal planes for the p-type MOSFET and the n-type MOSFET can be manufactured using a method known as a hybrid substrate. Since the mobility of holes in a semiconductor is larger in the (110) plane than in the (100) plane, in the present invention, the p-type MOSFE T is substantially separated from the (110) plane or the (110) plane. By making it on a crystallographically equivalent surface, using one kind of gate electrode material, making the absolute value of the threshold voltage of the p-type MOSFET and n-type MOSFET the same, and further, Transistor performance can be improved due to the increase.
[0048] 本発明を特別に示し且つ例示的な実施形態例を参照して記述したが、本発明は、 その実施形態例及びその変形に限定されるものではない。当業者に明らかなように、 添付のクレームに規定される本発明の精神及び範囲を逸脱することなぐ種々の変 更が可能である  [0048] While the invention has been particularly shown and described with reference to illustrative embodiments, the invention is not limited to these embodiments and variations thereof. It will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.
[0049] 本出願は、 2006年 9月 19日出願に係る日本特許出願 2006— 252637号を基礎 とし且つその優先権を主張するものであり、引用によってその開示の内容の全てを本 出願の明細書中に加入する。  [0049] This application is based on and claims the priority of Japanese Patent Application No. 2006-252637 filed on September 19, 2006. The entire contents of the disclosure of this application are incorporated herein by reference. Join in the book.

Claims

請求の範囲 The scope of the claims
[1] p型トランジスタ及び n型トランジスタの何れか一方が、完全空乏型 SOI構造を有す る相補型 MIS半導体装置にぉレ、て、  [1] Either a p-type transistor or an n-type transistor is connected to a complementary MIS semiconductor device having a fully depleted SOI structure.
前記 P型トランジスタ及び n型トランジスタのゲート電極が同一の材料で構成され、か つ前記材料は、 p型トランジスタ及び n型トランジスタの閾値電圧の絶対値を実質的 に同じとすることができる仕事関数を有する材料である、ことを特徴とする半導体装置  The gate electrode of the P-type transistor and the n-type transistor is made of the same material, and the material can make the absolute value of the threshold voltage of the p-type transistor and the n-type transistor substantially the same. A semiconductor device characterized by comprising a material having
[2] p型トランジスタ及び n型トランジスタの何れか一方が、完全空乏型 SOI構造を有す る相補型 MIS半導体装置にぉレ、て、 [2] Either a p-type transistor or an n-type transistor is connected to a complementary MIS semiconductor device having a fully depleted SOI structure.
前記 P型トランジスタ及び n型トランジスタのゲート電極が同一の材料で構成され、か つ前記材料は、 p型トランジスタ及び n型トランジスタの閾値電圧の絶対値のうち、大 きレ、方の絶対値と小さレ、方の絶対値との差力 大き!/、方の絶対値の 20%以下とする ことができる仕事関数を有する材料である、ことを特徴とする半導体装置。  The gate electrodes of the P-type transistor and the n-type transistor are made of the same material, and the material is larger than the absolute value of the threshold voltage of the p-type transistor and the n-type transistor. A semiconductor device characterized in that it is a material having a work function that can be set to a small difference, a large difference force with respect to the absolute value of one, and 20% or less of the absolute value of the other.
[3] p型トランジスタ及び n型トランジスタの他方が、バルタ構造を有することを特徴とす る請求項 1または 2に記載の半導体装置。  3. The semiconductor device according to claim 1, wherein the other of the p-type transistor and the n-type transistor has a Balta structure.
[4] p型トランジスタ及び n型トランジスタの双方力 完全空乏型 SOI構造を有する相補 型 MIS半導体装置において、  [4] Both power of p-type transistor and n-type transistor In complementary MIS semiconductor device with fully depleted SOI structure,
前記 P型トランジスタ及び n型トランジスタの SOI層が異なる膜厚を有し、 前記 P型トランジスタ及び n型トランジスタのゲート電極が同一の材料で構成され、か つ前記材料は、 p型トランジスタ及び n型トランジスタの閾値電圧の絶対値を実質的 に同じにすることができる仕事関数を有する材料である、ことを特徴とする半導体装 置。  The SOI layers of the P-type transistor and the n-type transistor have different film thicknesses, and the gate electrodes of the P-type transistor and the n-type transistor are composed of the same material, and the material includes the p-type transistor and the n-type transistor. A semiconductor device characterized in that it is a material having a work function capable of making the absolute value of the threshold voltage of a transistor substantially the same.
[5] p型、 n型の両方が完全空乏型 SOI構造を有する相補型 MIS半導体装置において 前記相補型 MIS半導体装置の p型、 n型の SOI層が、それぞれ異なる膜厚で構成 され、  [5] In the complementary MIS semiconductor device in which both the p-type and the n-type have a fully depleted SOI structure, the p-type and n-type SOI layers of the complementary MIS semiconductor device are configured with different film thicknesses, respectively.
前記相補型 MIS半導体装置の p型、 n型のゲート電極が同一の材料で構成され、 かつ前記材料は、 p型、 n型の閾値電圧の絶対値のうち、大きい方の絶対値と小さい 方の絶対値の差が、大きい方の絶対値の 20%以下とすることができる仕事関数を有 する材料である、ことを特徴とする半導体装置。 The p-type and n-type gate electrodes of the complementary MIS semiconductor device are made of the same material, and the material is larger and smaller of the absolute values of the p-type and n-type threshold voltages. A semiconductor device characterized by being a material having a work function in which the difference between the absolute values of the two can be 20% or less of the absolute value of the larger one.
[6] 前記ゲート電極の材料が、金属であることを特徴とする請求項 1乃至 5のいずれ力、 1 項に記載の半導体装置。 6. The semiconductor device according to any one of claims 1 to 5, wherein the material of the gate electrode is a metal.
[7] 前記ゲート電極の材料が、 Niと Siの化合物であることを特徴とする、請求項 1乃至 6 のいずれか 1項に記載の半導体装置。 [7] The semiconductor device according to any one of [1] to [6], wherein the material of the gate electrode is a compound of Ni and Si.
[8] 前記 p型トランジスタ及び n型トランジスタのゲート絶縁膜力 高誘電率絶縁膜であ ることを特徴とする、請求項 1乃至 7のいずれか 1項に記載の半導体装置。 [8] The semiconductor device according to any one of [1] to [7], wherein the p-type transistor and the n-type transistor have a high dielectric constant insulating film.
[9] 前記高誘電率絶縁膜力 fを含むことを特徴とする、請求項 8に記載の半導体装置 9. The semiconductor device according to claim 8, comprising the high dielectric constant insulating film force f.
[10] 前記 p型トランジスタの半導体活性層の表面は、（110)面または（110)面と等価な 面であり、 n型トランジスタの半導体活性層の表面力 （100)面または（100)面と等 価な面であることを特徴とする、請求項 1乃至 9のいずれか 1項に記載の半導体装置 [10] The surface of the semiconductor active layer of the p-type transistor is a (110) plane or a plane equivalent to the (110) plane, and the surface force (100) plane or (100) plane of the semiconductor active layer of the n-type transistor The semiconductor device according to claim 1, wherein the semiconductor device is an equivalent surface.
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