WO2008034310A1 - Dispositif et procédé permettant de réaliser la communication du mode de mise en correspondance - Google Patents

Dispositif et procédé permettant de réaliser la communication du mode de mise en correspondance Download PDF

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Publication number
WO2008034310A1
WO2008034310A1 PCT/CN2006/003776 CN2006003776W WO2008034310A1 WO 2008034310 A1 WO2008034310 A1 WO 2008034310A1 CN 2006003776 W CN2006003776 W CN 2006003776W WO 2008034310 A1 WO2008034310 A1 WO 2008034310A1
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WO
WIPO (PCT)
Prior art keywords
clock
module
mapping mode
locked loop
local
Prior art date
Application number
PCT/CN2006/003776
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English (en)
Chinese (zh)
Inventor
Jian Geng
Yong Tu
Peiyuan Liu
Yan Yuan
Erzhong Wu
Original Assignee
Zte Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zte Corporation filed Critical Zte Corporation
Publication of WO2008034310A1 publication Critical patent/WO2008034310A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver

Definitions

  • the present invention relates to a device for implementing a mapping mode and different service switching, and more particularly to a portion of a wavelength division multiplexing transmission device in an optical network domain, which uses a synchronous mapping mode and an asynchronous mapping mode. .
  • BACKGROUND In a synchronous optical network, clock frequencies and phases of all switching nodes in an entire optical network should be controlled within a certain tolerance range to ensure that all digital streams of switching nodes in the network are correctly and efficiently exchanged.
  • many nodes will perform clock rate conversion due to application requirements.
  • the ITU-T G.975/G.709 standard increases the service rate due to the addition of out-of-band FEC.
  • mapping payload information to an Optical Path Payload Unit (OPUk) frame there are two mapping methods when mapping payload information to an Optical Path Payload Unit (OPUk) frame: Bit Synchronous Maping and Asynchronous Mapping equipped Synchronous Mapping
  • the optical forwarding board ( ⁇ ) receives the reference clock signal provided by the upstream node or the reference clock source, and locks the phase of the OTU internal clock to the received timing reference through the OTU internal phase-locked loop (PLL), thereby The OTU clock is synchronized with the reference clock signal.
  • Asynchronous mapping mode if there is a large frequency deviation in the optical network, the OTU uses the local reference clock as the reference clock signal, and the phase of the OTU internal clock is sent to the OTU internal phase-locked loop.
  • the local reference clock should ensure that the frequency offset from the standard rate is within a certain range to ensure synchronization of the entire optical network.
  • the maximum frequency offset of the payload and OPUk must be less than that in the asynchronous mapping mode. 20ppm.
  • the actual clock unit only supports the synchronous mapping mode, or only supports the asynchronous mapping mode. The mode can not support the switching between the two modes.
  • the common implementation of the asynchronous mapping method is:
  • the service rate of the OTU processing, using the independent clock generator # is the local clock to provide the reference clock for the OTU internal phase-locked loop.
  • the service rate requires hardware to add different clock generators, and the hardware structure is more complicated.
  • the present invention provides a device for implementing mapping mode switching, which is characterized in that it comprises a receiving module, a local clock source module, a second-selecting switch, a transmitting phase-locked loop module, and a control module, and the receiving module is configured to receive from the upstream a signal, and recovering a clock from the service;
  • the local clock source module is configured to provide a receiving reference clock for the receiving module and a local reference clock for the second selected switch; Receiving the clock recovered from the service and the local reference clock, and transmitting a phase locked loop pre-clock;
  • the transmitting phase-locked loop module is configured to send a reference clock; and the control module is configured to control the rest Module.
  • the receiving module is a light receiving module, and includes a photoelectric converter and a clock recovery unit.
  • the light receiving module further includes a phase locked loop and/or a frequency divider.
  • the photoelectric converter is a 10G pin module, and the clock recovery unit is a clock and data recovery unit.
  • the local clock source module includes a local clock source and a receive phase locked loop, and the receive phase locked loop is a programmable phase locked loop.
  • the transmit phase-locked loop module includes a frequency divider 1, a phase detector, a filter, a voltage-controlled oscillator, and a frequency divider 2; the frequency divider 1 is configured to send an output signal to the phase-raiser; The phase detector is configured to send an output signal to the filter, and receive feedback of the frequency divider 2; The filter is configured to send an output signal to the voltage controlled oscillator; the voltage controlled oscillator is configured to output a transmit reference clock and a phase locked loop feedback clock; and the frequency divider 2 is configured to After the phase-locked loop feedback clock is divided, it is sent as a feedback signal to the phase detector.
  • the coefficients of the frequency divider 1 and the ratio of the frequency divider 2 conform to the Reed-Solomon (255, 237) coding scheme.
  • the control module is composed of a CPU and an FPGA.
  • the present invention provides a method for implementing mapping mode switching, including the following specific steps: Step 101: Receive a receiving reference clock provided by a local clock source, and receive a signal from the upstream, and recover a clock from the service; the local clock source Providing a local reference clock for the second selection switch; Step 102: If the optical forwarding board works in the asynchronous mapping mode, the two selected switches select the local reference clock; if the optical forwarding board works in the synchronous mapping mode, Selecting a switch selects the clock recovered from the service; Step 103: Receive an output signal of the selected switch and send a reference clock.
  • FIG. 1 is a composition of a device provided by the present invention.
  • FIG. 2 is a composition of a local clock source module provided by the present invention
  • FIG. 3 is a composition of a light receiving module provided by the present invention
  • 4 is a schematic diagram of a transmission phase locked loop module provided by the present invention
  • FIG. 5 is an example of a device provided by the present invention.
  • the device for implementing the mapping mode and the service switching according to the present invention is composed of an optical receiving module 101, a local clock source module 102, a control module 103, a second selection switch 104, and a transmission phase locked loop module 105. 1 is shown.
  • the detailed composition of the local clock source module 102 in FIG. 1 is as shown in FIG. 2. Its role is to provide high quality "local reference clock b" and "reference clock a of the light receiving module".
  • the "reference clock a of the light receiving module” provides a reference clock for the light receiving module 101.
  • the local clock source 201 has good frequency offset and temperature stability, and provides a high-precision clock.
  • the receive phase locked loop 202 can output a clock that is adapted to the traffic rate based on the local clock source.
  • the detailed composition of the light receiving module 101 in Fig. 1 is as shown in Fig. 3.
  • the photoelectric converter 301 changes the "from the upstream optical signal e" from the optical signal to the electrical signal, and with reference to the "reference clock a of the optical receiving module", the clock recovery unit 302 recovers the service clock from the service, and after processing To generate the output of the module "clock d recovered from the service", phase-locked loop 303 and frequency divider 304 can be selected to ensure the ideal clock shield.
  • the transmit pin phase loop module 105 outputs a "transmission reference clock h,.
  • the clock recovery unit employs a clock and data recovery (CDR) unit.
  • the transmit lock phase loop module 105 of FIG. 1 is composed in detail as shown in FIG.
  • the frequency divider 1 401 sends the output signal to the phase detector 402, the phase detector 402 sends the output signal to the filter 403, and the filter 403 sends the output signal to the voltage controlled oscillator 404, and the voltage controlled oscillator 404 outputs the output.
  • the phase-locked loop feedback clock c is sent as a feedback signal to the phase detector 402 via the frequency divider 2 405.
  • the selection of the two-selection switch 104 in FIG. 1 can be controlled, and the clock recovered from the service is selected.
  • d" or "local reference clock b,” provides the transmit lock ring module 105 with "send phase-locked loop pre-clock g,". Select A to implement the asynchronous mapping mode, and select B to implement the synchronous mapping mode.
  • the device can be applied to a dense wavelength division multiplexing OTU supporting STM64 services and 10GE services.
  • the device instance is composed as shown in FIG. 5:
  • the service light from the upstream enters the optical receiving module, and the optical receiving module extracts the service clock and data; the service processing part performs some overhead processing, and then the optical transponder 4 bar service data is sent out.
  • the clock unit consists of a receive phase-locked loop and a local reference clock. It also supports the creation of asynchronous and synchronous mapping OPUk signals.
  • the control module 103 in FIG. 5 is composed of a CPU and an FPGA.
  • the light receiving module 101 in Fig. 5 is composed of a 10G pin module [pin is a layer (relative;) thick intrinsic semiconductor sandwiched between a P-type semiconductor and an N-type semiconductor] and a clock recovery unit (CDR).
  • the 10G pin converts the 10G optical signal into a 10G electrical signal, and the clock recovery unit recovers the 622MHz clock from the 10G electrical signal.
  • the alternate switch 104 of Figure 5 can be controlled by a CPU or FPGA.
  • the optical receiving module selects a 10G transceiver integrated optical module that conforms to the standard.
  • RS Reed-Solomon
  • One-two is implemented by hardware, one of which is used as the reference clock of the optical receiving module, and the other is sent to the second-selecting switch 104 as the pre-clock of the phase-locked loop part when asynchronously mapping.
  • the recovered clock obtained from the light receiving module is synchronized with the reference clock signal and also sent to the second selection switch 104 as the pre-stage clock of the phase-locked loop module when synchronously mapped.
  • the CPU or FPGA controls the "two-selection switch" to determine the pre-stage clock of the phase-locked loop module, that is, the reference clock signal obtained by the phase-locked loop module, thereby determining whether the OTU operates in the synchronous mapping mode or the asynchronous mapping mode.
  • the clock rate of the optical receiving module, the division ratio of the discrete transmit phase-locked loop module, and the rate of the programmable phase-locked loop in the local clock source module are also controlled by the control module.
  • the implementation of the asynchronous mapping mode and the synchronous mapping mode and the selection of the switching two-selection switch 104 are controlled by the CPU or the FPGA, so that no hardware modification is required. It can support asynchronous mapping mode and synchronous mapping and its switching. If the OTU is required to operate in the asynchronous mapping mode, the two-select switch 104 in Figure 5' selects A. At this point, the transmit phase-locked loop module is locked to the "local reference clock b".
  • “Local reference clock b” has a small frequency offset, high quality, stable VCO output clock, small frequency offset, small jitter, suitable for asynchronous mapping to create OPUk signal, maximum frequency deviation of payload and OPUk Less than 20ppm, in line with the G.709 standard. This ensures the quality of the "send reference clock h". If the OTU is required to work in the synchronous mapping mode, when the optical network in which the OTU is located is working normally, the second selection switch 104 in FIG. 5 selects B. The transmit phase-locked loop module locks the "clock d recovered from the service" provided by the optical receiving module, from the "clock d recovered from the service” and "synchronized from the upstream optical signal e,".
  • the local clock source module 10'2 in FIG. 5 provides "reference clock a of the optical receiving module", and provides a reference clock signal "local reference clock b" in the asynchronous mapping mode, and its output
  • the frequency of the clock is variable and the frequency of the output clock can be adjusted by the FPGA. If the OTU handles the change in service rate, it is only necessary to adjust the value of the corresponding control register in the FPGA without changing the hardware. This avoids the disadvantage of using a separate fixed frequency clock generator as the local clock to provide the reference clock for the OTU internal phase-locked loop, which requires the configuration of the corresponding clock generator for different services.
  • the output clock of the local clock source module 102 in Fig. 5 is set by the FPGA. If the service type is STM64, the output is 155.52MHz. If the service type is 10GE, the output is 161.133MHz.
  • the optical receiving module 101 and the transmitting phase-locked loop module 105 in FIG. 5 perform corresponding control adjustments to adapt to the corresponding rates.
  • the clock rate of the light receiving module 101 is adjusted to STM64 The rate, that is, the 9.953 GHz or 10GE rate, that is, 10.312 GHz; the clock rate of the transmit phase locked loop module 105 is adjusted to the rate of G.709, that is, 10.709 GHz or 11.095 GHz.
  • the FPGA registers, control, etc. involved in each module in Figure 5 are set accordingly.
  • the CPU configures the division ratio coefficient m of the phase-locked loop module 105 to 79 and n to 85.
  • the CPU sets each FPGA to the ON state by setting the FPGA registers.
  • the local clock source module is used to provide two clocks, and the recovery clock in the service is selected to provide a reference clock for the phase locked loop in the device.
  • the technical measures have achieved the simplification of the hardware structure, achieving the simultaneous support of synchronous mapping and asynchronous mapping and multiple service type effects, saving hardware units and improving the reliability of the clock unit.
  • the invention enables the OTU to support both the synchronous mapping mode and the asynchronous mapping mode, and supports multiple service types.
  • the device can be applied to clock units inside the OTU.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

L'invention concerne un dispositif permettant de réaliser la commutation du mode de mise en correspondance qui comprend un module de réception (101), un module de source horloge local (102), un commutateur alternatif (104), un module de boucle à phase asservie (105) et un module de commande (103). Le module de réception (101) est utilisé pour recevoir le signal amont et récupérer l'horloge du service, le module de source horloge locale (102) est utilisé pour fournir l'horloge de référence de réception au module de réception (101) et fournir une horloge de référence locale au commutateur alternatif (104), le commutateur alternatif (104) est utilisé pour recevoir l'horloge récupérée du service et l'horloge de référence locale, et produire en sortie une horloge de la boucle à phase asservie précédente, le module de boucle à phase asservie d'émission (105) étant utilisé pour émettre une horloge de référence, le module de commande (103) étant utilisé pour commander le reste des modules.
PCT/CN2006/003776 2006-09-20 2006-12-30 Dispositif et procédé permettant de réaliser la communication du mode de mise en correspondance WO2008034310A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN 200610113254 CN101150875B (zh) 2006-09-20 2006-09-20 一种实现映射方式切换的装置及方法
CN200610113254.X 2006-09-20

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WO2008034310A1 true WO2008034310A1 (fr) 2008-03-27

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CN106550289B (zh) * 2015-09-17 2019-12-31 深圳市中兴微电子技术有限公司 一种为串并转换器提供参考时钟的方法、装置和客户端
CN109639358B (zh) * 2018-12-28 2023-09-01 杭州飞畅科技有限公司 节点光端机及基于该光端机的大规模电话传输系统和方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344077A (zh) * 2000-09-08 2002-04-10 朗迅科技公司 复用/去复用光通信信号的定时电路
EP1376915A2 (fr) * 2002-06-27 2004-01-02 Alcatel Méthode et système de synchronisation d'horloge dans un noeud d'accès échelonnable
US6839858B1 (en) * 2001-05-14 2005-01-04 Ciena Corporation System for clock synchronization

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3460118B2 (ja) * 1998-08-26 2003-10-27 富士通株式会社 同期網システムのクロック管理方法及び伝送装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1344077A (zh) * 2000-09-08 2002-04-10 朗迅科技公司 复用/去复用光通信信号的定时电路
US6839858B1 (en) * 2001-05-14 2005-01-04 Ciena Corporation System for clock synchronization
EP1376915A2 (fr) * 2002-06-27 2004-01-02 Alcatel Méthode et système de synchronisation d'horloge dans un noeud d'accès échelonnable

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CN101150875B (zh) 2010-09-08

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