WO2008027386A3 - Controlled ambient system for interface engineering - Google Patents

Controlled ambient system for interface engineering Download PDF

Info

Publication number
WO2008027386A3
WO2008027386A3 PCT/US2007/018924 US2007018924W WO2008027386A3 WO 2008027386 A3 WO2008027386 A3 WO 2008027386A3 US 2007018924 W US2007018924 W US 2007018924W WO 2008027386 A3 WO2008027386 A3 WO 2008027386A3
Authority
WO
WIPO (PCT)
Prior art keywords
ambient
transfer module
controlled
processing modules
lab
Prior art date
Application number
PCT/US2007/018924
Other languages
French (fr)
Other versions
WO2008027386A2 (en
Inventor
John Boyd
Yezdi Dordi
Tiruchirapalli Arunagiri
Benjamin W Mooring
John Parks
William Thie
Fritz C Redeker
Arthur M Howald
Alan Schoepp
David Hemker
Original Assignee
Lam Res Corp
John Boyd
Yezdi Dordi
Tiruchirapalli Arunagiri
Benjamin W Mooring
John Parks
William Thie
Fritz C Redeker
Arthur M Howald
Alan Schoepp
David Hemker
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/513,634 external-priority patent/US8771804B2/en
Priority claimed from US11/611,758 external-priority patent/US20080057182A1/en
Priority claimed from US11/639,752 external-priority patent/US9117860B2/en
Application filed by Lam Res Corp, John Boyd, Yezdi Dordi, Tiruchirapalli Arunagiri, Benjamin W Mooring, John Parks, William Thie, Fritz C Redeker, Arthur M Howald, Alan Schoepp, David Hemker filed Critical Lam Res Corp
Priority to KR1020137032044A priority Critical patent/KR101455955B1/en
Priority to CN2007800402135A priority patent/CN101529556B/en
Priority to KR1020097006393A priority patent/KR101423350B1/en
Priority to JP2009526680A priority patent/JP5417174B2/en
Publication of WO2008027386A2 publication Critical patent/WO2008027386A2/en
Publication of WO2008027386A3 publication Critical patent/WO2008027386A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Chemically Coating (AREA)

Abstract

A cluster architecture including a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules The lab-ambient controlled transfer module and the one or more wet substrate processing modules manage a first ambient environment having a vacuum transfer module coupled to the lab-ambient controlled transfer module and one or more plasma processing modules The vacuum transfer module and the one or more plasma processing modules manage a second ambient environment A controlled ambient transfer module coupled to the vacuum transfer module and one or more ambient processing modules manage a third ambient environment The cluster architecture therefore enables controlled processing of the substrate in eith the first, second or third ambient environments, as well as duπng associated transitions The embodiments also provide for efficient methods for filling a trench of a substrate
PCT/US2007/018924 2006-08-30 2007-08-28 Controlled ambient system for interface engineering WO2008027386A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020137032044A KR101455955B1 (en) 2006-08-30 2007-08-28 Controlled ambient system for interface engineering
CN2007800402135A CN101529556B (en) 2006-08-30 2007-08-28 Combined system structure for processing substrate
KR1020097006393A KR101423350B1 (en) 2006-08-30 2007-08-28 Controlled ambient system for interface engineering
JP2009526680A JP5417174B2 (en) 2006-08-30 2007-08-28 A controlled atmosphere system for engineering design of interfaces.

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/513,634 2006-08-30
US11/513,634 US8771804B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a copper surface for selective metal deposition
US11/611,758 US20080057182A1 (en) 2006-08-30 2006-12-15 Method for gap fill in controlled ambient system
US11/611,758 2006-12-15
US11/639,752 2006-12-15
US11/639,752 US9117860B2 (en) 2006-08-30 2006-12-15 Controlled ambient system for interface engineering

Publications (2)

Publication Number Publication Date
WO2008027386A2 WO2008027386A2 (en) 2008-03-06
WO2008027386A3 true WO2008027386A3 (en) 2008-08-21

Family

ID=39136542

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/018924 WO2008027386A2 (en) 2006-08-30 2007-08-28 Controlled ambient system for interface engineering

Country Status (6)

Country Link
JP (1) JP5417174B2 (en)
KR (2) KR101423350B1 (en)
CN (2) CN101529556B (en)
SG (2) SG174750A1 (en)
TW (1) TWI447831B (en)
WO (1) WO2008027386A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008027386A2 (en) * 2006-08-30 2008-03-06 Lam Research Corporation Controlled ambient system for interface engineering
US9865501B2 (en) * 2013-03-06 2018-01-09 Lam Research Corporation Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
TWI584370B (en) * 2013-08-27 2017-05-21 Tokyo Electron Ltd A substrate processing method, a substrate processing apparatus, and a memory medium
US10026649B2 (en) 2014-12-23 2018-07-17 Intel Corporation Decoupled via fill
US10249521B2 (en) * 2016-03-17 2019-04-02 Lam Research Ag Wet-dry integrated wafer processing system
US10443146B2 (en) 2017-03-30 2019-10-15 Lam Research Corporation Monitoring surface oxide on seed layers during electroplating
US10770314B2 (en) 2017-05-31 2020-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, tool, and method of manufacturing
JP6538894B2 (en) * 2018-01-10 2019-07-03 エーファウ・グループ・エー・タルナー・ゲーエムベーハー How to bond substrates together
JP2019192892A (en) 2018-04-18 2019-10-31 東京エレクトロン株式会社 Processing system and processing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627105A (en) * 1993-04-08 1997-05-06 Varian Associates, Inc. Plasma etch process and TiSix layers made using the process
US5935395A (en) * 1995-11-08 1999-08-10 Mitel Corporation Substrate processing apparatus with non-evaporable getter pump
US6319831B1 (en) * 1999-03-18 2001-11-20 Taiwan Semiconductor Manufacturing Company Gap filling by two-step plating
US20020064942A1 (en) * 1995-12-12 2002-05-30 Dixit Girish A. Low pressure, low temperature, semiconductor gap filling process
US6518203B2 (en) * 1999-09-24 2003-02-11 Applied Materials, Inc. Method and apparatus for integrating a metal nitride film in a semiconductor device

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JPH088318A (en) * 1994-06-16 1996-01-12 Hitachi Ltd Semiconductor production system
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
US20030116427A1 (en) * 2001-08-30 2003-06-26 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
SG87187A1 (en) * 1999-10-18 2002-03-19 Applied Materials Inc Pvd-imp tungsten and tungsten nitride as a liner, barrier and/or seed layer for tungsten, aluminium and copper applications
JP2001196373A (en) * 2000-01-13 2001-07-19 Mitsubishi Electric Corp Producing method for semiconductor device and semiconductor device
JP3907151B2 (en) * 2000-01-25 2007-04-18 株式会社東芝 Manufacturing method of semiconductor device
US6777327B2 (en) * 2001-03-28 2004-08-17 Sharp Laboratories Of America, Inc. Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics
US6936906B2 (en) * 2001-09-26 2005-08-30 Applied Materials, Inc. Integration of barrier layer and seed layer
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
JP3588612B2 (en) * 2002-02-19 2004-11-17 株式会社東芝 Semiconductor device
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FR2851258B1 (en) * 2003-02-17 2007-03-30 Commissariat Energie Atomique METHOD OF COATING A SURFACE, FABRICATION OF MICROELECTRONIC INTERCONNECTION USING THE SAME, AND INTEGRATED CIRCUITS
CN100593235C (en) * 2003-06-13 2010-03-03 应用材料公司 Integration of ALD tantalum nitride for copper metallization
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627105A (en) * 1993-04-08 1997-05-06 Varian Associates, Inc. Plasma etch process and TiSix layers made using the process
US5935395A (en) * 1995-11-08 1999-08-10 Mitel Corporation Substrate processing apparatus with non-evaporable getter pump
US20020064942A1 (en) * 1995-12-12 2002-05-30 Dixit Girish A. Low pressure, low temperature, semiconductor gap filling process
US6319831B1 (en) * 1999-03-18 2001-11-20 Taiwan Semiconductor Manufacturing Company Gap filling by two-step plating
US6518203B2 (en) * 1999-09-24 2003-02-11 Applied Materials, Inc. Method and apparatus for integrating a metal nitride film in a semiconductor device

Also Published As

Publication number Publication date
KR20090069278A (en) 2009-06-30
TW200832586A (en) 2008-08-01
TWI447831B (en) 2014-08-01
KR101423350B1 (en) 2014-07-24
WO2008027386A2 (en) 2008-03-06
JP2010503210A (en) 2010-01-28
CN102347210A (en) 2012-02-08
SG10201501328WA (en) 2015-04-29
KR101455955B1 (en) 2014-10-31
CN101529556B (en) 2012-05-30
JP5417174B2 (en) 2014-02-12
KR20140002811A (en) 2014-01-08
CN101529556A (en) 2009-09-09
CN102347210B (en) 2015-08-05
SG174750A1 (en) 2011-10-28

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